TWI753993B - 內連線結構及其形成方法 - Google Patents
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- TWI753993B TWI753993B TW107101964A TW107101964A TWI753993B TW I753993 B TWI753993 B TW I753993B TW 107101964 A TW107101964 A TW 107101964A TW 107101964 A TW107101964 A TW 107101964A TW I753993 B TWI753993 B TW I753993B
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
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- H10P14/432—
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762448788P | 2017-01-20 | 2017-01-20 | |
| US62/448,788 | 2017-01-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201841324A TW201841324A (zh) | 2018-11-16 |
| TWI753993B true TWI753993B (zh) | 2022-02-01 |
Family
ID=62907123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107101964A TWI753993B (zh) | 2017-01-20 | 2018-01-19 | 內連線結構及其形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US10541174B2 (enExample) |
| JP (1) | JP7027432B2 (enExample) |
| KR (1) | KR102489216B1 (enExample) |
| TW (1) | TWI753993B (enExample) |
| WO (1) | WO2018136712A1 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10833078B2 (en) | 2017-12-04 | 2020-11-10 | Tokyo Electron Limited | Semiconductor apparatus having stacked gates and method of manufacture thereof |
| TWI681537B (zh) * | 2019-05-30 | 2020-01-01 | 旺宏電子股份有限公司 | 半導體結構與連線結構的製作方法 |
| US11335592B2 (en) * | 2019-09-17 | 2022-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact resistance between via and conductive line |
| US12057322B2 (en) | 2019-10-21 | 2024-08-06 | Tokyo Electron Limited | Methods for etching metal films using plasma processing |
| CN114188302B (zh) * | 2020-02-04 | 2022-12-13 | 联芯集成电路制造(厦门)有限公司 | 具有金属间介电图案的半导体元件及其制作方法 |
| US20220093505A1 (en) * | 2020-09-24 | 2022-03-24 | Intel Corporation | Via connections for staggered interconnect lines |
| US11776895B2 (en) * | 2021-05-06 | 2023-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method for manufacturing the same |
| US11908738B2 (en) | 2021-10-18 | 2024-02-20 | International Business Machines Corporation | Interconnect including integrally formed capacitor |
| TWI855278B (zh) * | 2021-12-02 | 2024-09-11 | 南亞科技股份有限公司 | 半導體裝置與其製造方法 |
| KR20230165643A (ko) * | 2022-05-27 | 2023-12-05 | 에스케이하이닉스 주식회사 | 하드 마스크를 이용한 패턴 형성 방법 |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040094841A1 (en) * | 2002-11-08 | 2004-05-20 | Casio Computer Co., Ltd. | Wiring structure on semiconductor substrate and method of fabricating the same |
| US20040134769A1 (en) * | 2003-01-10 | 2004-07-15 | Applied Materials, Inc. | Partially filling copper seed layer |
| TW200518266A (en) * | 2003-11-25 | 2005-06-01 | Taiwan Semiconductor Mfg Co Ltd | Method for forming a multi-layer seed layer for improved Cu ECP |
| TW200610032A (en) * | 2004-09-07 | 2006-03-16 | Taiwan Semiconductor Mfg Co Ltd | Method for plasma treating an etched opening or a damascening opening formed in a porous low-k material, and semiconductor device |
| US8796853B2 (en) * | 2012-02-24 | 2014-08-05 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
| US20150206792A1 (en) * | 2014-01-22 | 2015-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming conducting via and damascene structure |
| US20160225665A1 (en) * | 2013-09-26 | 2016-08-04 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
| US20170005069A1 (en) * | 2009-09-22 | 2017-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer Backside Interconnect Structure Connected to TSVs |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6992344B2 (en) * | 2002-12-13 | 2006-01-31 | International Business Machines Corporation | Damascene integration scheme for developing metal-insulator-metal capacitors |
| JP2005191254A (ja) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | 半導体装置の製造方法 |
| US7189626B2 (en) * | 2004-11-03 | 2007-03-13 | Micron Technology, Inc. | Electroless plating of metal caps for chalcogenide-based memory devices |
| US20060097397A1 (en) * | 2004-11-10 | 2006-05-11 | Russell Stephen W | Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device |
| US7470612B2 (en) * | 2005-09-13 | 2008-12-30 | Samsung Electronics Co, Ltd. | Method of forming metal wiring layer of semiconductor device |
| KR100870271B1 (ko) | 2007-06-28 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 및 그의 형성 방법 |
| US8164190B2 (en) * | 2009-06-25 | 2012-04-24 | International Business Machines Corporation | Structure of power grid for semiconductor devices and method of making the same |
| KR101802435B1 (ko) * | 2011-03-28 | 2017-11-29 | 삼성전자주식회사 | 반도체 장치의 금속 배선 형성 방법 |
| WO2013095433A1 (en) * | 2011-12-21 | 2013-06-27 | Intel Corporation | Electroless filled conductive structures |
| KR102092863B1 (ko) * | 2013-12-30 | 2020-03-24 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
| KR102542758B1 (ko) | 2015-06-05 | 2023-06-12 | 도쿄엘렉트론가부시키가이샤 | 상호접속부를 위한 루테늄 금속 피처 충전 |
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2018
- 2018-01-19 WO PCT/US2018/014373 patent/WO2018136712A1/en not_active Ceased
- 2018-01-19 KR KR1020197024007A patent/KR102489216B1/ko active Active
- 2018-01-19 US US15/875,442 patent/US10541174B2/en active Active
- 2018-01-19 TW TW107101964A patent/TWI753993B/zh active
- 2018-01-19 JP JP2019539194A patent/JP7027432B2/ja active Active
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2019
- 2019-09-05 US US16/562,207 patent/US10923392B2/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040094841A1 (en) * | 2002-11-08 | 2004-05-20 | Casio Computer Co., Ltd. | Wiring structure on semiconductor substrate and method of fabricating the same |
| US20040134769A1 (en) * | 2003-01-10 | 2004-07-15 | Applied Materials, Inc. | Partially filling copper seed layer |
| TW200518266A (en) * | 2003-11-25 | 2005-06-01 | Taiwan Semiconductor Mfg Co Ltd | Method for forming a multi-layer seed layer for improved Cu ECP |
| TW200610032A (en) * | 2004-09-07 | 2006-03-16 | Taiwan Semiconductor Mfg Co Ltd | Method for plasma treating an etched opening or a damascening opening formed in a porous low-k material, and semiconductor device |
| US20170005069A1 (en) * | 2009-09-22 | 2017-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer Backside Interconnect Structure Connected to TSVs |
| US8796853B2 (en) * | 2012-02-24 | 2014-08-05 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
| US20160225665A1 (en) * | 2013-09-26 | 2016-08-04 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
| US20150206792A1 (en) * | 2014-01-22 | 2015-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming conducting via and damascene structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201841324A (zh) | 2018-11-16 |
| JP7027432B2 (ja) | 2022-03-01 |
| KR102489216B1 (ko) | 2023-01-16 |
| US20200006129A1 (en) | 2020-01-02 |
| WO2018136712A1 (en) | 2018-07-26 |
| US10923392B2 (en) | 2021-02-16 |
| KR20190100975A (ko) | 2019-08-29 |
| US20180211870A1 (en) | 2018-07-26 |
| JP2020505770A (ja) | 2020-02-20 |
| US10541174B2 (en) | 2020-01-21 |
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