TWI753476B - Printed circuit and testing method of copper thickness - Google Patents

Abstract

A test coupon for copper thickness test is provided, including a plurality of circuit layers and a plurality of through holes. Each of the circuit layers comprises a copper line, the top of the circuit layer comprises a plurality of pads sequentially aligned; and a plurality of conductive points sequentially aligned and corresponding to the pads. The through holes sequentially align and penetrate through the circuit layers. Two ends of each of the copper lines of the circular layers respectively and electrically connect to two of the through holes at the same layer to form a circuit.

Description

Test methods for printed circuit boards and copper thickness

The present invention relates to a test coupon, a printed circuit board and a testing method thereof, and in particular, to a test coupon for copper thickness testing, a printed circuit board and a testing method thereof.

With the continuous upgrading of the electronic information industry, especially the arrival of the 5G era, higher requirements have been placed on the signal transmission of the printed circuit board (PCB), and at the same time, higher PCB acceptance standards have also been put forward. requirements.

In the process of signal transmission, copper thickness and line width play a crucial role, which affects the attenuation of the signal, so they are strictly required by more and more customers. However, since the current monitoring of copper thickness and line width in the field is mainly carried out by means of slicing, it cannot be detected in large quantities and quickly.

In view of this, how to improve the speed of detecting the line width and copper thickness needs to be improved in the prior art.

An embodiment of the present disclosure aims to provide a test coupon for copper thickness testing, so as to achieve the effect of quickly testing the line width and copper thickness.

An embodiment of the present disclosure provides a test coupon for copper thickness test, which includes a plurality of circuit layers and a plurality of vias. Each circuit layer includes leads, wherein the uppermost circuit layer includes: a plurality of pads, which are arranged in a straight line in sequence; and a plurality of conductive points, which correspond to and electrically connect the pads in sequence. These via holes are sequentially arranged in a straight line and penetrate through the circuit layers. One end of these via holes is respectively connected to these pads in sequence; wherein, both ends of each lead of all or part of these circuit layers are respectively electrically connected to two of these via holes located in the same layer to form a loop, And each lead is not repeatedly connected to these via holes that have been connected to other circuit layers.

In some embodiments, the two ends of the lead of the uppermost circuit layer are respectively electrically connected to the two via holes that are farthest away; The holes are electrically connected; the two ends of the leads of the remaining circuit layers are electrically connected to two via holes with decreasing distances selected in sequence from top to bottom.

In some embodiments, the test coupon for copper thickness test includes eight circuit layers and sixteen vias, wherein the uppermost circuit layer includes sixteen pads and sixteen conductive points.

In some embodiments, the test coupon for copper thickness test further includes at least one positioning hole disposed at one end of the test coupon for copper thickness test.

In some embodiments, each lead is U-shaped.

In some embodiments, the test coupon for copper thickness test further includes a region of the daisy chain adjacent to the bottom of the U-shape of each lead.

An embodiment of the present disclosure further provides a printed circuit board, comprising at least one attachment test board for copper thickness test as described above, wherein the attachment test board for copper thickness test is disposed on one side of the printed circuit board.

In some embodiments, the printed circuit board includes a plurality of test coupons for copper thickness test as described above, wherein the test coupons for copper thickness test are sequentially arranged on the edge of the printed circuit board.

An embodiment of the present disclosure further provides a copper thickness testing method, which includes the following steps: detaching the test pad from the printed circuit board as described above; connecting the pads on the test pad with a resistance tester respectively Connect the two corresponding terminals on the circuit layer to form a test loop between the leads on each circuit layer and the pads connecting the leads; measure the actual resistance of each test circuit, corresponding to different circuit layers; and judge the resistance of each test circuit Whether the difference between the actual resistance and the theoretical resistance set in advance according to the copper thickness and lead information is within the threshold, if so, the copper thickness is determined to meet the standard, otherwise it is determined that the copper thickness does not meet the standard.

In some embodiments, the lead information includes the line length L and the line width W, and the formula for calculating the theoretical resistance R is: R=ρ. L/W, where ρ represents resistivity.

In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the embodiments and specific embodiments of the present invention, but this is not the only form of implementing or using the specific embodiments of the present invention. The embodiments disclosed below can be combined or substituted with each other under beneficial circumstances, and other embodiments can also be added to one embodiment without further description or explanation. In the following description, numerous specific details are set forth in detail to enable the reader to fully understand the following embodiments. However, embodiments of the invention may be practiced without these specific details.

In addition, spatially relative terms, such as "lower", "upper", etc., are used to conveniently describe the relative relationship between one element or feature and other elements or features in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

As used herein, unless the context specifically defines the article, "a" and "the" can refer to a single one or a plurality. It will be further understood that the terms "comprising", "including", "having" and similar words used herein designate the recited features, regions, integers, steps, operations, elements and/or components, but do not exclude Other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

FIG. 1 is a schematic top view of a copper thickness test attachment test board 10 located on a brushed circuit board according to an embodiment of the present disclosure. An attachment test board 10 for copper thickness test of the present disclosure is disposed on the side 21 of the printed circuit board 20 . Specifically, the test coupon 10 for copper thickness test is provided in the waste material area of the printed circuit board 20 . Therefore, when the printed circuit board 20 is cut to obtain the part containing the test coupon 10 for copper thickness test, it can be easily taken for copper thickness test, which improves the previous design of the test coupon in four areas of the printed circuit board. , the inconvenience of placing the entire printed circuit board on the test machine.

FIG. 2 is a schematic top view of the test coupon 10 for copper thickness test of the first layer according to an embodiment of the present disclosure, and FIG. 3 shows the test coupon 10 for copper thickness test according to an embodiment of the present disclosure. cross-sectional schematic diagram. In some embodiments, the test pad 10 for copper thickness test includes a plurality of circuit layers 100 , a plurality of via holes 200 and at least one positioning hole 300 .

Each wiring layer 100 includes leads 110 . In one embodiment, the leads 110 are U-shaped. The uppermost circuit layer 100 includes a plurality of pads 120 and a plurality of conductive points 130 . The pads 120 are arranged in a straight line in sequence, and the conductive points 130 correspond to and are electrically connected to the pads 120 in sequence. Specifically, the copper thickness test uses a four-terminal copper thickness tester. Since these terminals are arranged in a straight line, the copper thickness test can be performed after these terminals are correspondingly contacted with the solid conductive points 130 . These solid conductive dots 130 are located on the uppermost or lowermost circuit layer 100 (see FIG. 2 , which is the uppermost layer in this embodiment). In some embodiments, the centers of the pads 120 are hollow, and the conductive points 130 are solid. In some embodiments, leads 110 are about 3000-4000 mils in length and about 30-40 mils in width; eg, about 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900 mils in length , or any value in between any two of these values; about 31, 32, 33, 34, 35, 36, 37, 38, 39 mils wide, or any value in between any two of these values.

The vias 200 are sequentially arranged in a straight line and pass through the circuit layers 100 . One ends of the vias 200 are respectively electrically connected to the pads 120 in sequence. All or part of the two ends of the leads 110 of the circuit layers 100 are respectively electrically connected to two of the vias 200 located on the same layer to form a loop, and the leads 110 are not repeatedly connected to other circuit layers 100 that have already been connected. These vias 200 are connected. Specifically, in order to unify the testing specifications, the number of vias 200 is fixed. Therefore, if the number of layers of the circuit layer 100 multiplied by two is less than the number of vias 200, some vias 200 may not be detected. will be connected by lead 110 . For example, if the number of vias 200 is sixteen, the number of circuit layers 100 is six, and 6*2<16, there will be four vias that will not be connected by the leads 110 .

At least one positioning hole 300 is provided at one end of the test attachment board 10 for copper thickness test. In one embodiment, the test coupon 10 for copper thickness test includes two positioning holes 300 , which are respectively provided at both ends of the coupon for copper thickness test 10 .

In some embodiments, the copper thickness test coupon 10 further includes a region of the daisy chain 400 adjacent to the bottom of the U-shape of each lead 110 . Specifically, the daisy chain 400 is disposed between the positioning holes 300 adjacent to the leads 110 and away from the pads 120 . In one embodiment, in order to monitor the quality of all solder joints in the component during the reliability test, the circuit design adopts a daisy chain design, so that the assembled solder joints form a network, and the connection of the network is detected by detecting the connection of the network. Or open circuit to judge whether the solder ball solder joint fails.

In some embodiments, the two ends of the lead 110 of the uppermost circuit layer 100 are respectively electrically connected to the two via holes 200 with the farthest distance; the two ends of the lead 110 of the lowermost circuit layer 100 are respectively connected to the distance The two closest vias 200 are electrically connected; the two ends of the leads 110 of the remaining circuit layers 100 are electrically connected to the two vias 200 with decreasing distances selected in sequence from top to bottom.

In some embodiments, the test coupon 10 for copper thickness test includes eight circuit layers 100 and sixteen via holes 200 , wherein the uppermost circuit layer 100 includes sixteen pads 120 and sixteen conductive points 130 . Specifically, as shown in FIG. 2 , there are sixteen pads 120 on the uppermost layer, that is, the first circuit layer 101 , which are sequentially marked as A, B, C, D, E, F, G, H, H ', G', F', E', D', C', B' and A', wherein the two ends of the lead 110 disposed on the first circuit layer 101 are connected to A and A' respectively. FIGS. 4-9 are schematic top views of the test pad 10 for copper thickness testing of the second to seventh layers according to an embodiment of the present disclosure. As shown in FIG. 4, both ends of the lead 110 of the second circuit layer 102 are electrically connected to the two vias 200 connected to the pads B and B' respectively; as shown in FIG. 5, the third circuit layer 103 Both ends of the lead 110 of the fourth circuit layer 104 are electrically connected to the two vias 200 connected to the pads C and C' respectively; as shown in FIG. 6 , the two ends of the lead 110 of the fourth circuit layer 104 are respectively connected to the pad D The two vias 200 connected to and D' are electrically connected; as shown in FIG. 7, the two ends of the lead 110 of the fifth circuit layer 105 are electrically connected to the two vias 200 connected to the pads E and E' respectively. Connection; as shown in FIG. 8, both ends of the lead 110 of the sixth circuit layer 106 are electrically connected to the two vias 200 connected to the pads F and F' respectively; as shown in FIG. 9, the seventh circuit Both ends of the lead 110 of the layer 107 are electrically connected to the two vias 200 connected to the pads G and G' respectively. FIG. 10 is a schematic bottom view of the test pad for copper thickness test of the eighth layer. Both ends of the lead 110 of the eighth circuit layer 108 are electrically connected to the two vias 200 connected to the pads H and H' respectively. connect.

FIG. 11 is a schematic top view of a test coupon 10' for copper thickness test according to another embodiment of the disclosure. When the number of circuit layers 100 multiplied by two is greater than the number of vias 200, a plurality of test coupons 10' for copper thickness testing will be added. Such a design can use inspection fixtures of the same specification, so that the inspection specifications are unified and consistent. Specifically, FIG. 11 shows a 24-layer circuit layer, and three test coupons 10 ′ for copper thickness testing are arranged on the right side of the printed circuit board 20 , which are respectively designed to detect the first to eighth layers, The ninth to sixteenth floors, and the seventeenth to twenty-fourth floors. For example, the number of vias 200 of a test coupon 10' for copper thickness test is sixteen, the number of circuit layers 100 is twenty-four layers, and 24*2>16 requires three attach tests for copper thickness test board 10'.

In some embodiments, the copper thickness test is changed from sampling monitoring to overall monitoring by being introduced by a four-terminal copper thickness testing machine. Specifically, the theoretical resistance value is calculated by designing the attached test board 10 (or called Coupon strip). Next, the actual resistance value is obtained after verifying the attached test board 10 on the actual printed circuit board with a machine. Then compare the theoretical resistance value with the actual resistance value to find out whether the copper thickness meets the standard, so as to effectively monitor the copper thickness and line width.

The present disclosure further provides a copper thickness testing method for the above-mentioned test pad, comprising the following steps: S1: removing the test pad from the circuit board; S2: connecting the via holes or pads on the test pad with the resistors The corresponding terminals on the tester (the copper thickness tester is selected in this embodiment) are connected (with pads to connect pads and no pads to connect to vias), and then connect the leads on each circuit layer to the two leads connected to the leads. The pad forms a test loop; S3: Measure the actual resistance of each test loop, corresponding to different circuit layers; S4: Determine the difference between the actual resistance of each test loop and the theoretical resistance set in advance according to copper thickness and lead information , whether it is within the threshold, if so, the copper thickness is determined to meet the standard, otherwise the copper thickness is determined not to meet the standard.

Lead information includes line length L and line width W, and the formula for calculating resistance R is: R=ρ. L/W, where ρ represents resistivity.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure protects The scope shall be determined by the scope of the appended patent application.

10, 10': Coupon for copper thickness test

20: Printed Circuit Board

21: Sides

100: circuit layer

101: The first circuit layer

102: Second circuit layer 103: The third circuit layer 104: Fourth circuit layer 105: Fifth circuit layer 106: Sixth circuit layer 107: seventh circuit layer 108: Eighth circuit layer 110: Leads 120: Pad 130: Conductive dots 200: Via hole 300: Positioning hole 400: Daisy Chain A, B, C, D, E, F, G, H, H', G', F', E', D', C', B', A': Pads

The various aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that in accordance with industry standard operating procedures, the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic top view of a copper thickness test attaching test board located on a printed circuit board according to an embodiment of the present disclosure. FIG. 2 is a schematic top view of the test coupon for copper thickness test of the first layer according to an embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view of a test coupon for copper thickness test according to an embodiment of the present disclosure, which is cut downward from the directions of arrows on the left and right sides of FIG. 2 . FIG. 4 is a schematic top view of the test coupon for copper thickness test of the second layer according to an embodiment of the present disclosure. FIG. 5 is a schematic top view of the test coupon for copper thickness test of the third layer according to an embodiment of the present disclosure. FIG. 6 is a schematic top view of the test coupon for copper thickness test of the fourth layer according to an embodiment of the present disclosure. FIG. 7 is a schematic top view of the test coupon for copper thickness test of the fifth layer according to an embodiment of the present disclosure. FIG. 8 is a schematic top view of the test coupon for copper thickness test of the sixth layer according to an embodiment of the present disclosure. FIG. 9 is a schematic top view of the test coupon for copper thickness test of the seventh layer according to an embodiment of the present disclosure. FIG. 10 is a schematic bottom view of the test coupon for copper thickness test of the eighth layer according to an embodiment of the present disclosure. FIG. 11 is a schematic top view of a copper thickness test attachment test board located on a printed circuit board according to another embodiment of the disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

10: Coupon test board for copper thickness test 101: The first circuit layer 110: Leads 120: Pad 130: Conductive dots 300: Positioning hole 400: Daisy Chain A, B, C, D, E, F, G, H, H', G', F', E', D', C', B', A': pads

Claims (10)

A printed circuit board, comprising at least one attaching test board for copper thickness testing, which is arranged in a waste material area of the printed circuit board, the attaching testing board for copper thickness testing comprising: a plurality of circuit layers, each of which includes a Leads, wherein the uppermost circuit layer includes: a plurality of pads, arranged in a straight line in sequence; and a plurality of conductive points, corresponding to and electrically connected to the pads in sequence, wherein one of the pads is hollow in the center, The conductive point is solid; and a plurality of via holes are sequentially arranged in a straight line and penetrate through the circuit layers, wherein one end of the via holes is respectively connected to the pads in sequence; wherein, all or part of the The two ends of each lead of some circuit layers are respectively electrically connected to two of the through holes located in the same layer to form a loop, and each of the leads is not repeatedly connected to the other circuit layers that have been connected. some vias. The printed circuit board according to claim 1, wherein the two ends of the lead of the uppermost circuit layer are respectively electrically connected to the two via holes that are farthest away; the lead of the lowermost circuit layer The two ends of the wire are respectively electrically connected to the two closest via holes; the two ends of the lead wires of the other circuit layers are selected to be electrically connected to the two via holes with decreasing distances from top to bottom. The printed circuit board as claimed in claim 1, wherein the test coupon for copper thickness test includes eight circuit layers and sixteen via holes, wherein the uppermost circuit layer includes sixteen pads and sixteen vias Conductive point. The printed circuit board as claimed in claim 1, further comprising at least one positioning hole disposed at one end of the copper thickness test attachment test board. The printed circuit board of claim 1, wherein each lead is in a U-shape. The printed circuit board of claim 5, further comprising a daisy-chain region adjacent to the U-shaped bottom of each lead. A printed circuit board, comprising at least one test coupon for copper thickness test as described in any one of claims 1 to 6, wherein the test coupon for copper thickness test is provided on one side of the printed circuit board . A printed circuit board, comprising a plurality of test coupons for copper thickness testing as described in any one of claims 1 to 6, wherein the test coupons for copper thickness testing are sequentially arranged on the printed circuit board The edge. A copper thickness testing method, comprising the steps of: removing the attached test board from the printed circuit board as claimed in claim 7 or 8; Connect the pads on the attachment test board to two corresponding terminals on a resistance tester, so as to form a test loop between the leads on each circuit layer and the pads connected to the leads; measure The actual resistance of each test loop corresponds to different circuit layers respectively; and it is judged whether the difference between the actual resistance of each test loop and the theoretical resistance set in advance according to the copper thickness and a lead information is within the threshold, and if so, then It is judged that the copper thickness meets the standard, otherwise it is judged that the copper thickness does not meet the standard. The copper thickness test method as claimed in claim 9, wherein the lead information includes a line length L and a line width W, and the formula for calculating the theoretical resistance R is: R=ρ. L/W, where ρ represents resistivity.

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