1269883 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種基板及測試治具，詳言之，係關於一 種具有測試區之基板及用於該基板之測試治具。 【先前技術】 參考圖1所示，習知之基板10包括複數個線路板丨丨及 12，其係依序上下相鄰設置。每一線路板係具有一線路層 及一介電層。該線路板11具有一線路層m及一介電層 ® 112，該線路板12具有一線路層121及一介電層122。該基 板1〇具有一第一表面17，設置於該第一線路板n，該第 一表面17具有複數個連接墊114,用以與一晶片（圖未示出） 電性連接。利用連接孔113及123使得該連接墊114可與 線路層111及12 1電性連接。該連接孔丨丨3係貫穿該介電 層112，該連接孔123係貫穿該介電層122。該等連接孔 113、123内係填充導電材料，俾使上下相鄰之線路層經由 _ 該等連接孔而電性連接。 在填充導電材料於該等連接孔時，可能會產生不良之裂 縫115 ’該具裂縫之連接孔可能會造成連接孔之斷路，使得 上下相鄰之線路層無法電性連接。此外，若該裂縫丨丨5係 屬微裂縫（micro open)，意即其與正常之連接孔間電阻之差 異僅在數毫歐姆（ιηΩ)之間時，即不易量測得該連接孔之電 阻變化，因此，也就無法正確判別該連接孔是否具有微 縫。 4 再者，目刖之測試儀器可分為二線式（2 wire)測試探針及 99286.doc -1269883 四線式（4 wire)測試探針。二線式測試探針係利用單一測試 楝針，其測試範圍通常為i Ω .Λ 1〇 m之間，其測試精度 為〇. Ω°^’㈣該L試探針缺量敎常之連 :孔與：有微裂縫之連接孔其電阻之差異(數毫歐姆瓜 )’故…、去偵測基板是否存在具微裂縫之連接孔。1269883 IX. Description of the Invention: [Technical Field] The present invention relates to a substrate and a test fixture, and more particularly to a substrate having a test area and a test fixture for the same. [Prior Art] Referring to Fig. 1, a conventional substrate 10 includes a plurality of circuit boards 12 and 12 which are sequentially disposed adjacent to each other. Each circuit board has a circuit layer and a dielectric layer. The circuit board 11 has a circuit layer m and a dielectric layer ® 112. The circuit board 12 has a circuit layer 121 and a dielectric layer 122. The substrate 1 has a first surface 17 disposed on the first circuit board n. The first surface 17 has a plurality of connection pads 114 for electrically connecting to a wafer (not shown). The connection pads 114 can be electrically connected to the circuit layers 111 and 12 1 by using the connection holes 113 and 123. The connection hole 3 extends through the dielectric layer 112, and the connection hole 123 penetrates through the dielectric layer 122. The connection holes 113 and 123 are filled with a conductive material, and the adjacent circuit layers are electrically connected via the connection holes. When the conductive material is filled in the connection holes, a defective crack 115 may be generated. The cracked connection hole may cause the connection hole to be broken, so that the upper and lower adjacent circuit layers cannot be electrically connected. In addition, if the crack 丨丨 5 is a micro open, that is, the difference between the resistance and the normal connection hole is only between several milliohms (ιηΩ), that is, the connection hole is not easily measured. The resistance changes, and therefore, it is impossible to correctly determine whether the connection hole has a micro slit. 4 Furthermore, the test instruments witnessed can be divided into two-wire (2 wire) test probes and 99286.doc -1269883 four-wire (4 wire) test probes. The two-wire test probe uses a single test needle, and its test range is usually between i Ω and Λ 1〇m. The test accuracy is 〇. Ω°^' (4) The L probe probe deficiencies are often connected. : Hole and: The difference between the resistance of the connection hole with micro-cracks (several milliohms). Therefore, to detect whether there is a connection hole with micro-cracks on the substrate.
參考圖1，目線式測試探針18係利用二測試探針181及 二其：試範圍通常為_至1000Ω之間，其測試精度 為因此’利用該四線式測試探針可量測正常之連 接孔與具有微裂縫之連接孔其電阻之差異（數毫歐姆m ⑴。然而’由於目前晶片及基板之尺寸越來越小，該連接 塾m之寬度通常為dl，且二測試探針181及182之寬度 為们，大於該連接塾114之寬度di。因此，四線式測試探 針仍無法適用於㈣基板是否存在具微裂縫之連接孔。 因此’實有必要提供—種創新且富進步性之基板及測試 治具，以解決上述問題。 【發明内容】 本發明之目的在於提供—種具有測試區之基板，該基板 包括·複數個線路板、複數個測試孔及一第一表面。該等 線路板係依序上下相鄰設置’具有至少—第一線路板及一 第二線路板，每一線路板係具有一線路層、一介電層及一 測试區。該等測試孔係設置於該測試區，並貫穿該等線路 板之該等介電層，且電性連接上下相鄰之該等線路板之該 等線路層。該第-表面係設置於該第—線路板，該第一表 面具有一晶片區，該晶片區具有複數個連接墊，用以與一 99286.doc 1269883 曰曰片電性連接，該第一表面之該測試區具有至少 試塾與該等測試孔電性連接，該第-測;: 登用以供一測試器測試。 由於在測試區之製程條件完全與晶片區相同，若在 :之連接孔具有裂縫，則在測試區之該等測試孔亦會具有 1 ·’本毛明之基板在測試區將複數個測試孔電性連接， 測試墊量測’可使正常之測試孔與具有裂縫之Referring to Figure 1, the eye-line test probe 18 utilizes two test probes 181 and two: the test range is usually between _ and 1000 Ω, and the test accuracy is such that 'the four-wire test probe can be used to measure normal The difference in resistance between the connection hole and the connection hole having micro-cracks (several milliohms m (1). However, since the size of the wafer and the substrate is getting smaller and smaller, the width of the connection 塾m is usually dl, and the two test probes 181 The width of the 182 is greater than the width di of the connection 塾 114. Therefore, the four-wire test probe is still not suitable for the (four) substrate whether there is a connection hole with micro cracks. Therefore, it is necessary to provide an innovative and rich The invention relates to a substrate and a test fixture for solving the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate having a test area, the substrate comprising a plurality of circuit boards, a plurality of test holes and a first surface The circuit boards are sequentially disposed adjacent to each other with at least one first circuit board and one second circuit board, each circuit board having a circuit layer, a dielectric layer and a test area. hole Provided in the test area, and extending through the dielectric layers of the circuit boards, and electrically connecting the circuit layers of the circuit boards adjacent to each other. The first surface is disposed on the first circuit board. The first surface has a wafer area having a plurality of connection pads for electrically connecting to a 99286.doc 1269883 chip. The test area of the first surface has at least a test hole and the test holes. Electrical connection, the first test;: used for a tester test. Since the process conditions in the test area are completely the same as the wafer area, if the connection holes have cracks, the test holes in the test area are also Will have 1 · 'the base of the Mao Ming in the test area will be electrically connected to a plurality of test holes, the test pad measurement 'can make normal test holes and cracks
7 ·/、電阻之差異加大’俾使測試器可偵測基板是否存 在具裂縫之連接孔，以判斷該基板之良否。 本發明之另一目的在於提供一種測試治具，用於一基 板’该基板具有一晶片區及一測試區，該晶片區具有複數 個連接墊’該測試區具有複數個測試墊，該測試治具包括： 複數個第一測試探針及複數個第二測試探針。該等第一測 試探針係相對於該晶片區之該等連接塾，用以與該區 之該等連接塾電性連接。該等第二測試探針係相對於該測 试區之該等測試墊，用以與該測試區之該等測試墊電性 接0 本發明之該測試治具利用該等第一測試探針及第二測試 探針可同時量測§亥基板之晶片區及測試區之電氣特性，以 簡化測試流程，並可判斷該基板之良否。 【實施方式】 請參閱圖2，其顯示本發明之具測試區之基板2〇上視示 意圖。本發明具測試區之基板20包括一晶片區21及一測 試區22,該晶片區21用以承載一晶片（圖未示出）。該測試 區22可供一測試器連接，以判斷該基板之良否。該測試區 99286.doc -7 - .1269883 \ 22不一定須設置於該基板20之角落，其可設置於晶片區 2 1以外之該基板其他區域。 參考圖3，其顯示本發明第一實施例之基板20之侧視示 ' 意圖。本發明具有測試區之基板20包括：複數個線路板 23、24、25及一第^一表面26。該等線路板23、24、25係 依序上下相鄰設置，具有至少一第一線路板23及一第二線 路板25。該第一線路板23係設置於該基板20之最上層， 該第二線路板25係設置於該基板20之最下層。該基板20 ❿ 之該第一表面26具有一晶片區21及一測試區22(參考圖 2)。 每一線路板係具有一線路層、一介電層及一測試區。該 線路板23具有一線路層231及一介電層232 ;該線路板24 具有一線路層241及一介電層242 ;該線路板25具有一線 路層25 1及一介電層252。該等線路板之測試區係相對於該 第一表面26之測試區22(參考圖2)。 该第一表面26係設置於該第一線路板23上，該第一表 鲁面之該晶片區具有複數個連接墊211、212、213、214,用 以與一晶片（圖未示出）電性連接。該等連接墊211、212、 213、214係分別與連接孔21 5、216、217、218電性連接， 该等連接孔可貫穿該等線路板之介電層，使得該等連接墊 可與各線路板之線路層電性連接。 該第一表面26之該測試區具有二個第一測試墊221及 2U。二個第一測試墊22丨及222與該等測試孔224、225、 226、227及228電性連接。在圖3中係示意地表示，二個 第一測試墊22i及222間僅具有五個測試孔電性連接，實 99286.doc !269883 際應用上，二個第一測試墊22 1及222間之測試孔數目將 遠大於五個。較佳地，二個第一測試墊221及222間之測 试孔數目約為數百至數千之間。 由於在測試區之製程條件完全與晶片區相同，若在晶片 區之連接孔具有裂縫，則在測試區之該等測試孔亦會具有 裂縫。並且，如上所述，正常之連接孔與具有裂縫之連接 孔其電阻之差異僅在數毫歐姆（m Ω )之間。若以一千個測試 孔在二個第一測試墊221及222之間為例說明，經量測二 個第一測試墊221及222間之電阻值；在正常之測試孔（不 具有裂縫）之情形下，二個第一測試墊221及222之電阻值 為1歐姆（Ω)，在具有裂縫之測試孔之情形下，二個第一測 試墊221及222之電阻值為4歐姆（Q)。 因此，利用本發明具測試區之基板，在測試區將複數個 測試孔電性連接，i由㈣—測試塾量測，可使正常之測 =與具有裂縫之測試孔其電阻之差異加大，俾使測試器 可賴測基板是否存在具裂縫之連接孔，以判斷該基板 否。 卜、 t考圖3’本發明另包括-測試治具該測試治呈50 ==試該基板20。該測試治具5〇包括:複數個第一 針51、52、53、54及複數個第二測試探針55、56。 ㈣第-測試探針5卜52、53、54係 之該等連接塾211、212、213、214， 十於4日日片£ 之兮蓉遠垃航〇，！ 77別與该晶片區 之以連接塾211、212、213、214電性 片區之電氣特性。該等第—測試探針51、5 ^ —曰曰 二線式測試探針，係利用單一之測試探針進行量3測5。4係為 99286.doc 1269883 該等第二測試探針5 5、5 6係相對於該測試區之7 · /, the difference in resistance is increased '俾', so that the tester can detect whether there is a cracked connection hole in the substrate to judge whether the substrate is good or not. Another object of the present invention is to provide a test fixture for a substrate having a wafer area and a test area, the wafer area having a plurality of connection pads. The test area has a plurality of test pads. The device comprises: a plurality of first test probes and a plurality of second test probes. The first test probes are connected to the ports of the wafer region for electrical connection with the ports of the wafer region. The second test probes are electrically connected to the test pads of the test area relative to the test pads of the test area. The test fixture of the present invention utilizes the first test probes. And the second test probe can simultaneously measure the electrical characteristics of the chip area and the test area of the § hai substrate to simplify the test process and determine whether the substrate is good or not. [Embodiment] Referring to Fig. 2, there is shown a schematic view of a substrate 2 having a test area of the present invention. The substrate 20 having the test area of the present invention comprises a wafer area 21 and a test area 22 for carrying a wafer (not shown). The test area 22 can be connected by a tester to determine whether the substrate is good or not. The test area 99286.doc -7 - .1269883 \ 22 does not have to be disposed at a corner of the substrate 20, and may be disposed in other areas of the substrate other than the wafer area 2 1 . Referring to Fig. 3, there is shown a side view of the substrate 20 of the first embodiment of the present invention. The substrate 20 having the test area of the present invention comprises: a plurality of circuit boards 23, 24, 25 and a first surface 26. The circuit boards 23, 24, and 25 are sequentially disposed adjacent to each other, and have at least one first circuit board 23 and one second line board 25. The first circuit board 23 is disposed on the uppermost layer of the substrate 20, and the second circuit board 25 is disposed on the lowermost layer of the substrate 20. The first surface 26 of the substrate 20 has a wafer region 21 and a test region 22 (refer to Fig. 2). Each circuit board has a circuit layer, a dielectric layer and a test area. The circuit board 23 has a circuit layer 231 and a dielectric layer 232. The circuit board 24 has a circuit layer 241 and a dielectric layer 242. The circuit board 25 has a wiring layer 25 1 and a dielectric layer 252. The test zones of the boards are relative to the test zone 22 of the first surface 26 (see Figure 2). The first surface 26 is disposed on the first circuit board 23, and the wafer area of the first surface of the first surface has a plurality of connection pads 211, 212, 213, 214 for being used with a wafer (not shown). Electrical connection. The connection pads 211, 212, 213, and 214 are electrically connected to the connection holes 21 5 , 216 , 217 , and 218 , respectively , and the connection holes can penetrate through the dielectric layers of the circuit boards, so that the connection pads can be The circuit layers of each circuit board are electrically connected. The test zone of the first surface 26 has two first test pads 221 and 2U. The two first test pads 22 and 222 are electrically connected to the test holes 224, 225, 226, 227 and 228. As shown schematically in FIG. 3, there are only five test holes electrically connected between the two first test pads 22i and 222, and the first test pads 22 1 and 222 are used in the application. The number of test holes will be much larger than five. Preferably, the number of test holes between the two first test pads 221 and 222 is between several hundred and several thousand. Since the process conditions in the test area are completely the same as those in the wafer area, if the connection holes in the wafer area have cracks, the test holes in the test area may also have cracks. Also, as described above, the difference between the normal connection hole and the connection hole having the crack is only a few milliohms (m Ω ). If one thousand test holes are used as an example between the two first test pads 221 and 222, the resistance between the two first test pads 221 and 222 is measured; in the normal test hole (without cracks) In the case where the resistance values of the two first test pads 221 and 222 are 1 ohm (Ω), in the case of a test hole having a crack, the resistance values of the two first test pads 221 and 222 are 4 ohms (Q). ). Therefore, by using the substrate with the test area of the present invention, a plurality of test holes are electrically connected in the test area, and i is measured by (4)-test ,, so that the difference between the normal test and the test hole having the crack is increased. The tester can measure whether the substrate has a cracked connection hole to determine whether the substrate is not.卜, t考图3' The invention further comprises - a test fixture, the test is 50 == the substrate 20 is tested. The test fixture 5 includes a plurality of first needles 51, 52, 53, 54 and a plurality of second test probes 55, 56. (4) The first test probe 5, 52, 53, 54 series of these ports 塾 211, 212, 213, 214, 10 on the 4th day of the film of the Chow Chow far away,! 77 is electrically connected to the wafer region to electrically connect the electrical regions of the electrodes 211, 212, 213, and 214. The first-test probe 51, 5 ^ - 曰曰 two-line test probe is measured by a single test probe, the amount of 3 is measured. 5 is 99286.doc 1269883 The second test probe 5 5 , 5 6 series relative to the test area
測試孔其電阻之差異加大。並且， 可使正常之測試孔與具有裂縫之 5並且’該等第二測試探針5 5及 56係為四線式測試探針，係利用二測試探針進行量測，例 如該第二測試探針55具有二測試探針55卜552，該四線式 測試探針之精度為〇·1πιΩ，故可順利偵測基板是否存在具 裂縫之測試孔，以判斷該基板之良否。 為配合該等第二測試探針55及56之寬度，將第一測試 墊221及222之寬度加大，俾使該等第二測試探針”及％ 之二測試探針551、552及561、562可分別與第一測試墊 221及222電性連接。在晶片區之該等連接墊211、212、 213、214則維持正常設計之尺寸。 ^本發明之該測試治具利用該等第一測試探針及第二測試 〜十了门時里測该基板之晶片區及測試區之電氣特性，以 簡化測試流程，並可判斷該基板之良否。 立參考圖4，其顯示本發明第二實施例之基板之側視示 意圖。本發明具有測試區之基板3〇包括：複數個線路板 33、34、ls 卜η 33及一第二線路板35。該第一線路板33係設置於該基板The difference in resistance of the test hole is increased. Moreover, the normal test hole and the cracked 5 and the second test probes 5 5 and 56 are four-wire test probes, and the second test probe is used for measurement, for example, the second test The probe 55 has two test probes 55 552. The accuracy of the four-wire test probe is 〇·1πιΩ, so that the substrate can be smoothly detected whether there is a cracked test hole to judge whether the substrate is good or not. To match the width of the second test probes 55 and 56, the widths of the first test pads 221 and 222 are increased to enable the second test probes and the second test probes 551, 552 and 561. The 562 can be electrically connected to the first test pads 221 and 222 respectively. The connection pads 211, 212, 213, and 214 in the wafer area maintain the normal design size. ^ The test fixture of the present invention utilizes the same A test probe and a second test are used to measure the electrical characteristics of the wafer area and the test area of the substrate to simplify the test flow and determine whether the substrate is good or not. Referring to FIG. 4, the present invention is shown. 2 is a side view of the substrate of the second embodiment. The substrate 3 having the test area of the present invention comprises: a plurality of circuit boards 33, 34, ls η 33 and a second circuit board 35. The first circuit board 33 is disposed on The substrate
一第一表面36及一第二表面37。該等線路板 33 34、35係依序上下相鄰設置，具有至少一第一線路板 30之最上層， 99286.doc 1269883 每一線路板係具有一線路層、一介電層及一測試區。該 線路板33具有一線路層331及一介電層332 ;該線路板34 具有一線路層341及一介電層342。該等線路板之測試區係 相對於該第一表面36及該第二表面37之測試區。 該第一表面3 6係設置於該第一線路板3 3上，該第一表 面36之該測試區具有一第一測試墊321。該第二表面37 設置於該第二線路板35,該第二表面37之該測試區具有一 第二測試墊322。該第一測試墊321與該第二測試墊322 | 間以複數個測試孔324 ' 325、326電性連接。該第一測試 墊321及該第二測試墊322用以供該測試器之二測試探針 電性連接測試。 在圖4中係示意地表示，該第一測試墊3 21及該第二測 試墊322間僅具有三個測試孔電性連接，實際應用上，該 第一測試墊321及該第二測試墊322間之測試孔數目將遠 大於三個。較佳地，該第一測試墊321及該第二測試墊322 間之測試孔數目約為數百至數千之間。 | 與弟一實施例之基板2 0不同之處在於，該第一測試塾 321及該第二測試墊322分別設置於該第一表面36及該第 二表面37。因此，本發明可適用於測試該第二實施例基板 30之測試治具60 ’該測試治具60另需包括一組第二測試 探針66，設置於相對該第二測試墊322，俾使該等第二測 試探針65、66分別相對於該測試區之該第一測試塾321及 該第二測試墊322，用以分別與該測試區之該第一測試墊 32 1及該第一測試墊322電性連接，以量測該測試區之電氣 特性’以判斷該基板之良否。 99286.doc -11 - ⑧ 1269883A first surface 36 and a second surface 37. The circuit boards 33 34, 35 are sequentially disposed adjacent to each other, and have at least one uppermost layer of the first circuit board 30, 99286.doc 1269883 each circuit board has a circuit layer, a dielectric layer and a test area . The circuit board 33 has a circuit layer 331 and a dielectric layer 332. The circuit board 34 has a circuit layer 341 and a dielectric layer 342. The test zones of the boards are relative to the test areas of the first surface 36 and the second surface 37. The first surface 36 is disposed on the first circuit board 33. The test area of the first surface 36 has a first test pad 321. The second surface 37 is disposed on the second circuit board 35. The test area of the second surface 37 has a second test pad 322. The first test pad 321 and the second test pad 322 | are electrically connected by a plurality of test holes 324 325, 326. The first test pad 321 and the second test pad 322 are used for the test probe electrical connection test of the tester. The first test pad 321 and the second test pad 322 are electrically connected to each other. In practical applications, the first test pad 321 and the second test pad are shown in FIG. The number of test holes in 322 will be much larger than three. Preferably, the number of test holes between the first test pad 321 and the second test pad 322 is between several hundred and several thousand. The second test pad 321 and the second test pad 322 are respectively disposed on the first surface 36 and the second surface 37, respectively. Therefore, the present invention is applicable to testing the test fixture 60 of the second embodiment substrate 30. The test fixture 60 further includes a set of second test probes 66 disposed opposite to the second test pad 322. The first test probes 65 and 66 are respectively opposite to the first test pad 321 and the second test pad 322 of the test area for the first test pad 32 1 and the first of the test area, respectively. The test pad 322 is electrically connected to measure the electrical characteristics of the test area to determine whether the substrate is good or not. 99286.doc -11 - 8 1269883
參考圖5 ’其顯示本發明第三實施例之基板4〇之側視示 意圖。本發明具有測試區之基板4〇包括··複數個線路板 43 ' 44、45、一第一表面46及一第二表面47。該等線路板 43、44、45係依序上下相鄰設置，具有至少一第一線路板 43及一第二線路板45。該第一線路板43係設置於該基板 40之最上層，該第二線路板45係設置於該基板4〇之最下 層。每一線路板係具有一線路層、一介電層及一測試區。 該線路板44具有一線路層441及一介電層442。該等線路 板之測試區係相對於該第二表面47之測試區。 該第一表面46係設置於該第一線路板43上，該第一表 面46之該晶片區具有複數個連接墊，用以與一晶片（圖未 不出）電性連接。該第二表面47設置於該第二線路板45， 該第二表面47之該測試區具有二個第二測試墊421及 422。二個第二測試墊421及422間以複數個測試孔424、 425、426電性連接。二個第二測試墊421及422用以供該 測試器之二測試探針電性連接測試。 在圖5中係示意地表示，二個第二測試墊42丨及A。間 僅具有三個測試孔電性連接，實際應用上，二個第二測試 墊421及422間之測試孔數目將遠大於三個。較佳地^二 個第二測試墊421及422間之測試孔數目約為數百至數千 之間。 與第-實施例之基板20不同之處在於，二個第二琪"式墊 421及422係設置於該第二表面47。因此，本發明可適用 於測試該第三實施例基板40之測試治具7〇，該測試=且 70另需包括二組第二測試探針75、76，分別設置於相= 99286.doc • 12 · 1269883 - 個第二測試墊421及422之位置，俾使該等第二測試探針 75、76相對於該測試區之二個第二測試塾421及422，用 以與該測試區之二個第二測試墊421及422電性連接，以 1測该測試區之電氣特性，以判斷該基板之良否。 本發明之基板在測試區將複數個測試孔電性連接，可使 正常之測試孔與具有裂縫之測試孔其電阻之差異加大，並 將測試塾之寬度加大，以利於測試精度較佳之四線式測試 探針量測，俾使測試器可偵測基板是否存在具裂縫之連接 藝孔，以判斷該基板之良否。 惟上述實施例僅為說明本發明之原理及其功效，而非限 制本發明。因此，習於此技術之人士可在不違背本發明之 精神對上述實施例進行修改及變化。本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1為習知之基板結構示意圖； 圖2為本發明具測試區之基板之上視示意圖； _ 圖3為本發明第一實施例具測試區基板之侧視示意圖； 圖4為本發明第二實施例具測試區基板之側視示意 圖；及 圖5為本發明第三實施例具測試區基板之側視示意圖。 【圖式元件符號說明】 10 11、12 111 、 121 112 、 122 習知之基板 線路板 線路層 介電層f 99286.doc ·13· 1269883Referring to Fig. 5', there is shown a side view of a substrate 4 of a third embodiment of the present invention. The substrate 4 having the test area of the present invention comprises a plurality of circuit boards 43' 44, 45, a first surface 46 and a second surface 47. The circuit boards 43, 44, and 45 are sequentially disposed adjacent to each other, and have at least one first circuit board 43 and one second circuit board 45. The first circuit board 43 is disposed on the uppermost layer of the substrate 40, and the second circuit board 45 is disposed on the lowermost layer of the substrate 4. Each circuit board has a circuit layer, a dielectric layer and a test area. The circuit board 44 has a wiring layer 441 and a dielectric layer 442. The test zones of the boards are relative to the test zone of the second surface 47. The first surface 46 is disposed on the first circuit board 43. The chip area of the first surface 46 has a plurality of connection pads for electrically connecting to a chip (not shown). The second surface 47 is disposed on the second circuit board 45. The test area of the second surface 47 has two second test pads 421 and 422. The two test pads 421 and 422 are electrically connected by a plurality of test holes 424, 425, and 426. Two second test pads 421 and 422 are used for the test probe electrical connection test of the tester. Shown schematically in Figure 5, two second test pads 42 and A are shown. There are only three test holes electrically connected. In practical applications, the number of test holes between the two second test pads 421 and 422 will be much larger than three. Preferably, the number of test holes between the two second test pads 421 and 422 is between several hundred and several thousand. The difference from the substrate 20 of the first embodiment is that two second slabs 421 and 422 are disposed on the second surface 47. Therefore, the present invention is applicable to testing the test fixture 7 of the substrate 40 of the third embodiment, and the test = 70 further includes two sets of second test probes 75, 76, respectively disposed at phase = 99286.doc • 12 · 1269883 - the positions of the second test pads 421 and 422, such that the second test probes 75, 76 are opposite to the second test pads 421 and 422 of the test area for use with the test area The two second test pads 421 and 422 are electrically connected to measure the electrical characteristics of the test area to determine whether the substrate is good or not. The substrate of the invention electrically connects a plurality of test holes in the test area, so that the difference between the resistance of the normal test hole and the test hole having the crack is increased, and the width of the test file is increased, so as to facilitate the test precision. The four-wire test probe is measured, so that the tester can detect whether there is a cracked connecting hole in the substrate to judge whether the substrate is good or not. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic top view of a substrate having a test area according to the present invention; FIG. 3 is a schematic side view of a substrate having a test area according to a first embodiment of the present invention; 4 is a side view of a substrate with a test area according to a second embodiment of the present invention; and FIG. 5 is a side view of a substrate with a test area according to a third embodiment of the present invention. [Graphic Symbol Description] 10 11, 12 111 , 121 112 , 122 Conventional substrate Circuit board Circuit layer Dielectric layer f 99286.doc ·13· 1269883
113 、123 連接孔 114 連接墊 115 裂缝 17 第一表面 18 四線式測試探針 181 、182 測試探針 20 本發明具測試區之基板 21 晶片區 22 測試區 23、 24 > 25 線路板 26 第一表面 211 、212 、 213 、 214 連接墊 215 、216 、 217 、 218 連接孔 221 、m 第一測試墊 224 、225 、 226 ' 227 、 228 測試孔 231 、241 、 251 線路層 232 ' 242 、 252 介電層 30 本發明具測試區之基板 33 > 34、35 線路板 36 第一表面 ， 37 第二表面 321 第一測試墊 322 第二測試整 324 、325 、 326 測試孔 331 、341 線路層 99286.doc -14-113, 123 connection hole 114 connection pad 115 crack 17 first surface 18 four-wire test probe 181, 182 test probe 20 substrate 21 with test area of the present invention wafer area 22 test area 23, 24 > 25 circuit board 26 First surface 211, 212, 213, 214 connecting pads 215, 216, 217, 218 connecting holes 221, m first test pads 224, 225, 226' 227, 228 test holes 231, 241, 251 circuit layer 232 ' 242, 252 dielectric layer 30 substrate 17 with test area of the present invention 34, 35 circuit board 36 first surface, 37 second surface 321 first test pad 322 second test 324, 325, 326 test hole 331, 341 line Layer 99286.doc -14-
1269883 332 、 342 40 43 、 44 、 45 46 47 421 、 422 423 - 424 > 425 441 442 50 51 、 52 、 53 、 54 55、56 551 、 552 、 561 、 562 60 65 > 66 70 75 ^ 76 介電層 本發明具測試區之基板 線路板 第一表面 第二表面 第二測試墊 測試孔 線路層 介電層 測試治具 第一測試探針 第二測試探針 測試探針 測試治具 第二測試探針 測試治具 第二測試探針 99286.doc -15-1269883 332 , 342 40 43 , 44 , 45 46 47 421 , 422 423 - 424 > 425 441 442 50 51 , 52 , 53 , 54 55 , 56 551 , 552 , 561 , 562 60 65 > 66 70 75 ^ 76 Dielectric layer The substrate of the invention has a test area, the first surface, the second surface, the second test pad, the test hole, the circuit layer, the dielectric layer, the test fixture, the first test probe, the second test probe, the test probe, the test fixture, the second test probe. Test probe test fixture second test probe 99286.doc -15-