CN100474577C - Substrate and electrical testing method thereof - Google Patents
Substrate and electrical testing method thereof Download PDFInfo
- Publication number
- CN100474577C CN100474577C CNB2006100029166A CN200610002916A CN100474577C CN 100474577 C CN100474577 C CN 100474577C CN B2006100029166 A CNB2006100029166 A CN B2006100029166A CN 200610002916 A CN200610002916 A CN 200610002916A CN 100474577 C CN100474577 C CN 100474577C
- Authority
- CN
- China
- Prior art keywords
- test
- substrate
- conductive material
- probe
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H10W70/655—
Landscapes
- Measurement Of Resistance Or Impedance (AREA)
Abstract
Description
技术领域 technical field
本发明涉及一种基板及其电测方法,特别是涉及一种将基板的测试垫电性导通的基板结构及其电测方法。The invention relates to a substrate and an electrical measurement method thereof, in particular to a substrate structure and an electrical measurement method for electrically conducting test pads of the substrate.
背景技术 Background technique
请参考图1,其为现有的基板电测方法的示意图。首先,提供一基板10,该基板10具有一第一表面101及一第二表面102,该第一表面101具有多个第一测试垫103,该第二表面102具有多个第二测试垫104。第一测试垫103及第二测试垫104电连接形成多个电路105。接着,以一测试夹具11测试该基板10,该测试夹具11具有一第一测试探针12及多个第二测试探针13。该第一测试探针12具有两个测试探针121、122。每一第二测试探针13具有两个测试探针131、132。该第一测试探针12与该第一测试垫103电连接,每一第二测试探针13与每一第二测试垫104电连接。Please refer to FIG. 1 , which is a schematic diagram of a conventional electrical measurement method for a substrate. First, a
由于现有的基板电测方法必须对该第一表面101的第一测试垫103逐一地作测试,且该第一测试探针12的测试探针121、122必须在同一个第一测试垫103上,而该第一测试垫103尺寸极小,故该第一测试探针12的测试探针121、122不容易置于同一第一测试垫103上,因此,会产生漏测的问题,且必须耗费大测量试时间。Because the existing substrate electrical testing method must test the
因此,有必要提供一种基板及其电测方法,以解决上述问题。Therefore, it is necessary to provide a substrate and an electrical testing method thereof to solve the above problems.
发明内容 Contents of the invention
本发明的目的在于提供一种基板电测方法,该基板电测方法包括:(a)提供一基板,该基板具有一第一表面及一第二表面,该第一表面具有多个第一测试垫,该第二表面具有多个第二测试垫;(b)形成一导电材料于该第一表面上,以电连接至少两个第一测试垫;(c)以一测试夹具测试该基板,该测试夹具具有至少一第一测试探针及多个第二测试探针。The purpose of the present invention is to provide a substrate electrical testing method, the substrate electrical testing method includes: (a) providing a substrate, the substrate has a first surface and a second surface, the first surface has a plurality of first test Pad, the second surface has a plurality of second test pads; (b) forming a conductive material on the first surface to electrically connect at least two first test pads; (c) testing the substrate with a test fixture, The test fixture has at least one first test probe and a plurality of second test probes.
本发明的另一目的在于提供一种基板,该基板具有一第一表面、一第二表面及一导电材料。该第一表面具有多个第一测试垫。该第二表面具有多个第二测试垫,该第一测试垫及该第二测试垫电连接形成多个电路。该导电材料形成于该第一表面上,以电连接至少两个第一测试垫。Another object of the present invention is to provide a substrate having a first surface, a second surface and a conductive material. The first surface has a plurality of first test pads. The second surface has a plurality of second test pads, and the first test pads and the second test pads are electrically connected to form a plurality of circuits. The conductive material is formed on the first surface to electrically connect at least two first test pads.
本发明所提供的基板及基板电测方法是利用该导电材料于该第一表面上导通该第一测试垫,使该第一测试探针及第二测试探针可容易地测量该基板的电气特性,并可以简化测试流程及节省测试时间,且可判断该基板是否良好。The substrate and the electrical testing method of the substrate provided by the present invention are to use the conductive material to conduct the first test pad on the first surface, so that the first test probe and the second test probe can easily measure the substrate. Electrical characteristics, and can simplify the test process and save test time, and can determine whether the substrate is good or not.
附图说明 Description of drawings
图1为现有的基板电测方法的示意图;FIG. 1 is a schematic diagram of an existing electrical measurement method for a substrate;
图2至图4为本发明基板电测方法的第一实施例的示意图;2 to 4 are schematic diagrams of the first embodiment of the method for electrical measurement of the substrate of the present invention;
图5为本发明基板电测方法的第二实施例的示意图;5 is a schematic diagram of a second embodiment of the substrate electrical measurement method of the present invention;
图6为本发明的基板的第一实施例的示意图;6 is a schematic diagram of a first embodiment of the substrate of the present invention;
图7A为本发明的基板的第二实施例的侧视图;7A is a side view of a second embodiment of the substrate of the present invention;
图7B为本发明的基板的第二实施例的俯视图;7B is a top view of a second embodiment of the substrate of the present invention;
图8为本发明的基板的第三实施例的示意图。FIG. 8 is a schematic diagram of a third embodiment of the substrate of the present invention.
其中,附图标记:Among them, reference signs:
10 现有的基板 101 第一表面10 existing
102 第二表面 103 第一测试垫102
104 第二测试垫 105 电路104
11 测试夹具 12 第一测试探针11 Test Fixture 12 First Test Probe
121 探针 122 探针121
13 第二测试探针 131 探针13
132 探针 20 本发明的基板132
201 第一表面 202 第二表面201
203 第一测试垫 204 第二测试垫203
205 电路 21 导电材料205
22 测试夹具 23 第一测试探针22
231 探针 232 探针231
24 第二测试探针 241 探针24
242 探针 30 本发明的基板242
301 第一表面 303 第一测试垫301
304 第二测试垫 31 导电材料304
40 本发明的基板 401 第一表面40 substrate of the
403 第一测试垫 404 第二测试垫403
405 电路 41 导电材料405
50 本发明的基板 501 第一表面50 substrate of the present invention 501 first surface
503 第一测试垫 51 导电材料503 first test pad 51 conductive material
60 本发明的基板 601 第一表面60 substrate of the
603 第一测试垫 61 导电材料603
具体实施方式 Detailed ways
请参考图2至图4,其为本发明的基板电测方法的第一实施例的示意图。如图2所示,首先,提供一基板20,该基板20具有一第一表面201及一第二表面202。该第一表面201具有多个第一测试垫203,该第二表面202具有多个第二测试垫204。该第一测试垫203及该第二测试垫204电连接形成多个电路205。如图3所示,以一导电材料21于该第一表面201导通两个第一测试垫203。该导电材料是以导线形式电连接至少两个第一测试垫203。Please refer to FIG. 2 to FIG. 4 , which are schematic diagrams of a first embodiment of the substrate electrical testing method of the present invention. As shown in FIG. 2 , firstly, a
如图4所示,以一测试夹具22测试基板20,该测试夹具22具有至少一个第一测试探针23及多个第二测试探针24。该第一测试探针23具有两个测试探针231、232。每一第二测试探针24具有两个测试探针241、242。该第一测试探针23与该第一测试垫203电连接,该第二测试探针24与该第二测试垫204电连接,以测量该基板20的电气特性。在本实施例中,该第一测试探针23的两个测试探针231、232的间距须依照两个第一测试垫203的间距而调整。As shown in FIG. 4 , a
本发明第一实施例的基板电测方法是利用该导电材料21于该第一表面201上导通该第一测试垫203,使该第一测试探针23的测试探针231、232更容易与该第一测试垫203电连接,以及更容易测量该基板20的电气特性,并可以简化测试流程及节省测试时间,且可判断该基板20是否良好。The substrate electrical test method of the first embodiment of the present invention is to use the
请参考图5,其为本发明的基板电测方法的第二实施例的示意图。该第二实施例的基板电测方法与上述第一实施例的基板电测方法,不同之处在于该导电材料31是以电镀方式于该第一表面301完全覆盖该第一测试垫303。该第一测试探针23可与任一部位的该导电材料31电连接,且该第二测试探针24是与该第二测试垫304电连接,以测量该基板30的电气特性。Please refer to FIG. 5 , which is a schematic diagram of a second embodiment of the substrate electrical testing method of the present invention. The substrate electrical testing method of the second embodiment is different from the substrate electrical testing method of the first embodiment above in that the
本发明第二实施例的基板电测方法,该导电材料31是利用电镀方式形成于该第一表面301上,覆盖所有该第一测试垫303,用以电连接该第一测试垫303,使该第一测试探针23的测试探针231、232,能于导电材料31上任一位置测量该基板30的电气特性,并可以简化测试流程及节省测试时间,且可判断该基板30是否良好。In the substrate electrical testing method according to the second embodiment of the present invention, the
请参考图6,其为本发明的基板的第一实施例的示意图。该基板40具有一第一表面401及一第二表面402,该第一表面401具有多个第一测试垫403,该第二表面402具有多个第二测试垫404,该第一测试垫403及该第二测试垫404电连接形成多个电路405。以一导电材料41于该第一表面401上导通两个第一测试垫403,该导电材料41为银胶。该导电材料41是以导线形式电连接至少两个第一测试垫403。在其它的应用中,也可借助两个第一测试垫403的导通,用以电连接该基板40的电路405。Please refer to FIG. 6 , which is a schematic diagram of a first embodiment of the substrate of the present invention. The
该基板40是利用该导电材料41于该第一表面401上导通两个第一测试垫403,使测试夹具可容易地测量该基板40的电气特性,并可以简化测试流程及节省测试时间,以判断该基板40是否良好。The
请参考图7A及图7B,其为本发明的基板的第二实施例的示意图。该第二实施例的基板50与上述第一实施例的基板40的结构,不同之处在于该第二实施例中是利用一导电材料51于该第一表面501上导通所有第一测试垫503。Please refer to FIG. 7A and FIG. 7B , which are schematic diagrams of a second embodiment of the substrate of the present invention. The difference between the structure of the substrate 50 of the second embodiment and the
该基板50是利用该导电材料51于该第一表面501上导通所有该第一测试垫503,以形成一测试面,使测试夹具经由该测试面更容易地测量该基板50的电气特性,并可以简化测试流程及节省测试时间,以判断该基板60是否良好。The substrate 50 uses the conductive material 51 to conduct all the first test pads 503 on the first surface 501 to form a test surface, so that the test fixture can measure the electrical characteristics of the substrate 50 more easily through the test surface, And it can simplify the testing process and save testing time to judge whether the
请参考图8,其为本发明的基板的第三实施例的示意图。该第三实施例的基板60与上述第一实施例的基板40的结构,不同之处在于该实施例中是利用一导电材料61以电镀方式于该第一表面601完全覆盖该第一测试垫603,该导电材料61为铜。Please refer to FIG. 8 , which is a schematic diagram of a third embodiment of the substrate of the present invention. The difference between the structure of the
该基板60是利用该导电材料61于该第一表面601上覆盖该第一测试垫603,以形成一测试面,使测试夹具经由该测试面更容易地测量该基板60的电气特性,并可以简化测试流程及节省测试时间,以判断该基板60是否良好。The
以上所述仅为本发明其中的较佳实施例而已,并非用来限定本发明的实施范围;即凡依本发明权利要求所作的均等变化与修饰,皆为本发明专利范围所涵盖。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the implementation scope of the present invention; that is, all equivalent changes and modifications made according to the claims of the present invention are covered by the patent scope of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100029166A CN100474577C (en) | 2006-01-27 | 2006-01-27 | Substrate and electrical testing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100029166A CN100474577C (en) | 2006-01-27 | 2006-01-27 | Substrate and electrical testing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101009268A CN101009268A (en) | 2007-08-01 |
| CN100474577C true CN100474577C (en) | 2009-04-01 |
Family
ID=38697575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100029166A Expired - Lifetime CN100474577C (en) | 2006-01-27 | 2006-01-27 | Substrate and electrical testing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100474577C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101499458B (en) * | 2008-02-02 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Test structure and method for detecting disc trap and corrosion caused by CMP |
| CN102472792B (en) * | 2010-05-19 | 2014-11-12 | 松下电器产业株式会社 | Ic current measurement device and ic current measurement adapter |
| TWI455222B (en) * | 2011-08-25 | 2014-10-01 | 南茂科技股份有限公司 | Semiconductor component stack structure test method |
| TWI593970B (en) * | 2016-07-25 | 2017-08-01 | 日月光半導體製造股份有限公司 | Testing device |
| DE102016114142A1 (en) * | 2016-08-01 | 2018-02-01 | Endress+Hauser Flowtec Ag | Printed circuit board with contacting arrangement |
| KR102840537B1 (en) * | 2022-05-03 | 2025-07-31 | 주식회사 나노엑스 | Probe-head for electrical device inspection and manufacturing method thereof |
-
2006
- 2006-01-27 CN CNB2006100029166A patent/CN100474577C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN101009268A (en) | 2007-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9030216B2 (en) | Coaxial four-point probe for low resistance measurements | |
| TW201435348A (en) | Probe card, probe structure and method for manufacturing the same | |
| JP2012198189A5 (en) | Wiring board for electronic component inspection apparatus and manufacturing method thereof | |
| TW201825920A (en) | Vertical ultra-low leakage current probe card for dc parameter test | |
| CN110398657A (en) | Measured value needle and measuring mechanism | |
| CN100474577C (en) | Substrate and electrical testing method thereof | |
| KR102195561B1 (en) | Electrical connection device | |
| CN106206338A (en) | Printed circuit board (PCB) and method of testing thereof and the method manufacturing semiconductor packages | |
| JP4847907B2 (en) | Semiconductor inspection equipment | |
| WO2007133467A3 (en) | Air bridge structures and methods of making and using air bridge structures | |
| CN109786265B (en) | A packaged device, preparation method and signal measurement method | |
| JP2010025765A (en) | Contact structure for inspection | |
| JP2012018116A (en) | Probe unit for circuit board checkup and circuit board checkup device | |
| US7523369B2 (en) | Substrate and testing method thereof | |
| CN103985701A (en) | Package substrate and detection method thereof | |
| CN201069462Y (en) | Measuring device for circuit board | |
| JPH0829475A (en) | Contact probe of mounted substrate inspection device | |
| JP2013161553A (en) | Conductive sheet and substrate inspecting device | |
| JP6259254B2 (en) | Inspection apparatus and inspection method | |
| JP2004259750A (en) | Wiring board, connection wiring board and its inspection method, electronic device and its manufacturing method, electronic module and electronic equipment | |
| TWI274165B (en) | Probe card interposer | |
| CN102386144A (en) | Chip | |
| CN201352221Y (en) | Array type lug for detection | |
| CN101285863A (en) | Method and device for measuring circuit substrate | |
| JP2002311048A (en) | Guide for probe card, probe card equipped with the same, and method of inspecting electronic circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090401 |