TWI750895B - Electronic device - Google Patents

Abstract

An electronic device including a substrate, gate lines, a data line, a transfer line and pixel structures is provided. The gate lines, the data line, the transfer line and pixel structures are disposed on the substrate. The gate lines are disposed along a first direction. The data line is disposed along a second direction, wherein the first direction is interlaced with the second direction. The transfer line is parallel to the data line and adjacent to each other. The height of the transfer line on the substrate is smaller than the height of the data line on the substrate. Accordingly, it is possible to facilitate reduction of a coupling effect between lines and quality improvement of the electronic device.

Description

electronic device

The present invention relates to an electronic device.

With the popularization of electronic products, circuit layouts in various electronic devices are also complicated. Therefore, many adjacent lines may be used to carry different types of signals. However, the coupling effect between adjacent lines often affects the quality of signal transmission, resulting in the final performance not meeting expectations. Therefore, the planning of circuit layout is often one of the design priorities in electronic products.

The present invention provides an electronic device whose design can help reduce coupling between lines to provide improved quality.

The electronic device of the present invention includes a substrate, a plurality of gate lines, a data line, an adapter line and a plurality of pixel structures. A plurality of gate lines, data lines, transition lines and a plurality of pixel structures are all disposed on the substrate. A plurality of gate lines extend along the first direction. The data line extends along a second direction, wherein the first direction intersects the second direction. The transfer line is parallel to the data line and adjacent to each other, the transfer line is connected to one of the plurality of gate lines, and the material of the transfer line includes the material of the data line. One of the plurality of pixel structures is surrounded by two adjacent ones of the plurality of gate lines and the connecting line, and includes a pixel electrode and an active element. The height of the patch wire on the substrate is smaller than the height of the data wire on the substrate.

In an embodiment of the present invention, the above-mentioned electronic device further includes at least one insulating layer, wherein the at least one insulating layer includes a first opening. The vertical projection range of the first opening on the substrate covers the vertical projection range of the pixel electrode on the substrate, the connecting wire is arranged in the first opening, and the data wire is arranged on at least one insulating layer.

In an embodiment of the present invention, the above-mentioned insulating layers are formed by stacking insulating materials of different materials.

In an embodiment of the present invention, the material of the patch cable is the same as the material of the data cable.

In an embodiment of the present invention, in the pixel structure, the patch wires are in contact with the substrate, and the height difference between the patch wires and the data wires on the substrate is the thickness of at least one insulating layer. In some embodiments, at least one insulating layer includes a buffer layer, a gate insulating layer and an interlayer insulating layer, wherein the buffer layer is in contact with the substrate, and the film layer where the gate insulating layer is located is located between the film layer and the gate electrode of the active layer of the active element. Between the film layers, the film layer of the interlayer insulating layer is located between the film layer of the gate line and the film layer of the data line, and the height difference between the transfer line and the data line is the buffer layer, the gate insulating layer and the interlayer insulating layer. the sum of the film thicknesses.

In an embodiment of the present invention, in the pixel structure, a buffer layer is included between the transition line and the substrate, and a buffer layer and at least one insulating layer are included between the data line and the substrate. In some embodiments, at least one insulating layer includes a gate insulating layer and an interlayer insulating layer, the film layer where the gate insulating layer is located is located between the film layer of the active layer of the active element and the film layer of the gate electrode, and the interlayer insulating layer is The film layer is located between the film layer of the gate line and the film layer of the data line, and the height difference between the transfer line and the data line is the sum of the film thicknesses of the gate insulating layer and the interlayer insulating layer.

In an embodiment of the present invention, a light-shielding conductor layer is further included between the active element and the substrate, the data line is formed by the second conductive layer, and the patch wire is formed by directly stacking the light-shielding conductor layer and the second conductive layer.

In an embodiment of the present invention, the at least one insulating layer includes an interlayer insulating layer located between the gate line and the data line, and the interlayer insulating layer further includes a first through hole and a first conduction structure penetrating the first through hole , the transfer line is connected to one of the plurality of gate lines through the first conduction structure. In some embodiments, the above-mentioned interlayer insulating layer may further include a second through hole and a second conduction structure penetrating the second through hole, and the source electrode of the active element is connected to the data line through the second conduction structure. In some embodiments, the above-mentioned interlayer insulating layer may further include a third through hole and a third conduction structure passing through the third through hole, and the drain electrode of the active element is connected to the pixel electrode through the third conduction structure.

In an embodiment of the present invention, the patch lines and the data lines have zigzag patterns parallel to each other.

In an embodiment of the present invention, the pixel electrodes overlap the patch lines in a direction perpendicular to the substrate.

In an embodiment of the present invention, in the top view of the electronic device, the edge of the pixel electrode is located between the patch line and the data line, the edge of the pixel electrode and the patch cable are separated by a first distance on the substrate projection, and the drawing The edge of the pixel electrode and the data line are projected on the substrate by a second distance, the first distance is at least 2 microns, and the second distance is at least 3 microns.

Based on the above, in the electronic device of the embodiment of the present invention, the height of the patch wire on the substrate is smaller than the height of the data wire on the substrate, so that the patch cable and the data cable that transmit different signals and are adjacent to each other can be arranged separately in The non-coplanarity of the substrate helps to reduce the signal coupling between the patch cord and the data line. In addition, in some embodiments, the patch cable can be formed by stacking different conductive layers in parallel, thereby further reducing the impedance of the patch cable and improving the quality of signal transmission. the possibility of disconnection.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present between the two elements. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specific amount of measurement-related error (ie, a measurement system limit). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic partial top view of an electronic device according to the present invention. In FIG. 1 , the electronic device 100 includes a substrate 110 , a plurality of gate lines GL, a data line DL, a transition line TL, and a plurality of pixel structures 120 . As shown in FIG. 1 , the pixel structures 120 are arranged on the substrate 110 in an array arrangement. In other words, the pixel structure 120 presents an array arrangement along the first direction D1 and the second direction D2 intersecting the first direction D1, wherein in this embodiment, the first direction D1 can be understood as a lateral direction, and the second direction D2 Can be understood as the longitudinal direction. As shown in FIG. 1 , the lines extending in the lateral direction are gate lines GL, and the lines extending in the longitudinal direction can be divided into data lines DL directly connected to the pixel structure 120 and transitions not directly connected to the pixel structure 120 Line TL. The data lines DL and the transfer lines TL are parallel to each other. It is worth noting that, in this embodiment, although the transition line TL and the data line DL are represented by straight lines, in some embodiments, the transition line TL and the data line DL may also partially include a zigzag pattern, and the present invention does not This is the limit. As shown in FIG. 1 , the pixel structures 120 arranged in a row along the second direction D2 are sandwiched between two data lines DL, and each pixel structure 120 is connected to one of the data lines DL. In this embodiment, each transfer line TL is only disposed between the 3n-th data line DL and the pixel electrode 124 to which it is connected. For example, as shown in the dotted box in FIG. 1 , three pixel structures 120 (eg, red pixel, green pixel, and blue pixel) are used as one pixel unit 10, and the transition line TL is set at the rightmost pixel. Between the pixel electrode 124 of the structure 120 and the data line DL.

In some embodiments, each pixel structure 120 may include an active element 122 and a pixel electrode 124 connected to the active element 122 . Each active element 122 may be a transistor having a gate, a source and a drain, the gate may be connected to one of the data lines DL, the source may be connected to one of the data lines DL, and the drain may be connected to the pixel electrode 124 . In addition, each gate line GL is connected to one of the transition lines TL. Therefore, the signal of the gate electrode of the active element 122 can be transmitted to the gate electrode line GL through the transition line TL, and then input to the gate electrode through the gate electrode line GL. In addition, in order to avoid a short circuit between the gate line GL and the data line DL, or between the gate line GL and the transfer line TL, the gate line GL and the data line DL can be composed of different film layers, and the gate line GL and the transfer line TL can be formed by different layers. The wiring TL can be composed of different film layers. For example, the material of the gate line GL can be composed of the first conductive layer C1, and the material of the data line DL and the transition line TL can include the second conductive layer C2, and the material between the gate line GL and the data line DL, or the gate One or more insulating layers may be sandwiched between the pole line GL and the transition line TL. The film stacking relationship of the above circuit will be described in detail below.

In some embodiments, the electronic device 100 may further include a driving circuit IC, and the driving circuit IC is located at one end of the adapter line TL. The data line DL and the transfer line TL can directly receive the signal provided by the driving circuit IC, and the gate line GL can receive the corresponding signal through the transfer line TL. In this way, the electronic device 100 does not need to provide signal transmission lines or related circuits at both ends of the first direction D1 to achieve a narrow frame design, and the outline of the electronic device 100 does not need to be limited. For example, from a top-view perspective, the electronic device 100 may have a non-rectangular outline. In some embodiments, the electronic device 100 may further include another signal transfer line (not shown), and the other signal transfer line may not be used to transmit the signal required by the gate line GL, but is input with DC power bit. For example, the other signal transfer line may not be connected to any gate line GL, and is used for the realization of touch or other functions.

FIG. 2 is a schematic diagram of an enlarged embodiment of the dotted frame in the electronic device of FIG. 1 . FIG. 3 is a schematic diagram of an embodiment of the cross section along the section line A-A and the section line B-B in the electronic device of FIG. 2 . The electronic device 100A of FIG. 2 has a layout design substantially similar to that of the electronic device 100 of FIG. 1 , so the same reference numerals are used to denote the same components in the description of the two. In FIG. 2 , the electronic device 100A includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of pixel structures 120 and a transition line TL disposed on the substrate 110 . The layout and connection relationships of the plurality of gate lines GL, the plurality of data lines DL, the transition lines TL and the plurality of pixel structures 120 are as shown in FIG. 1 , and will not be repeated here.

In the electronic device 100A of FIG. 2 , the extension direction of the gate line GL is, for example, the first direction D1 shown in FIG. 1 , and the extension direction of the data line DL and the transition line TL is, for example, the second direction shown in FIG. 1 . D2, wherein the first direction D1 and the second direction D2 intersect each other, but the intersecting angle between the two is not limited to 90 degrees. As shown in FIG. 2 , the transition lines TL and the data lines DL in this embodiment have a zigzag pattern parallel to each other, that is, the transition lines TL and the data lines DL in this embodiment are not straight lines, but are meandering patterns on the substrate 110 . The serpentine manner extends in the second direction D2. As shown in FIG. 2 , one of the pixel structures 120 is located between two adjacent gate lines GL and between two adjacent data lines DL. For the convenience of description, the following mainly describes the signal lines around the single pixel structure 120 on the far right in FIG. 2 . The pixel structure 120 may include an active element 122 and a pixel electrode 124 , wherein three terminals of the active element 122 are respectively connected to the corresponding gate line GL, data line DL and the pixel electrode 124 . The edge of the pixel electrode 124 in this embodiment is parallel to the meandering pattern of the transition line TL and the data line DL.

As shown in FIG. 2 , in the periphery of the single pixel structure 120 on the far right, in addition to the data line DL connected to the active element 122 , a transition line TL is provided on the side of the data line DL close to the pixel electrode 124 . That is, the edge of the pixel electrode 124 is located between the transition line TL and the data line DL. In addition, the pixel electrodes 124 overlap the transition lines TL in the direction perpendicular to the substrate 110 . In other words, the transition line TL passes directly under the pixel electrode 124 . More specifically, as shown in the single pixel structure 120 on the far right of FIG. 2 , the edge of the pixel electrode 124 and the transition line TL on the left can be separated by a first distance DIS1 on the projection of the substrate 110 , and the first distance DIS1 It may be at least 2 microns, preferably 3 to 5 microns. On the other hand, the edge of the pixel electrode 124 and the right data line DL on the projection of the substrate 110 may be separated by a second distance DIS2, which may be at least 3 μm, preferably 4 μm to 6 μm.

FIG. 3 is a schematic diagram of an embodiment of the cross-section along the section line AA and the section line BB in the electronic device of FIG. 2 , and in the cross-sectional view of FIG. A component or film layer, such as a touch electrode, may exist between the pixel electrode and the flat layer as required. Referring to FIG. 2 and FIG. 3 at the same time, in this embodiment, the transition line TL is in contact with the substrate 110 . On the other hand, at least one insulating layer 130 is sandwiched between the data line DL and the substrate 110 . Thus, cable TL height H _T of the substrate 110 is less than the height H _D data lines DL (in the present example embodiment is zero _T H) on the substrate 110. In addition, since the transition line TL and the data line DL are not coplanar on the substrate 110, the distance between the transition line TL and the data line DL can be lengthened by the height difference on the premise of maintaining the horizontal distance between the two lines. In this way, the signal coupling between the transition line TL and the data line DL can be reduced.

In order to clearly illustrate the more specific film layer relationship between the data line DL and the transfer line TL in the film layer of the electronic device 100A, FIG. 4 intentionally enlarges a part of the film layer below the data line in FIG. 3 to clearly illustrate the relationship between the data line and the transfer line. The film layer where the wiring height difference originates. Please also refer to Figure 2 to Figure 4. More specifically, in this embodiment, the at least one insulating layer 130 between the data line DL and the substrate 110 includes three types of stacks of insulating layers formed in different processes, such as the buffer layer I0 and the gate insulating layer. I1 and the interlayer insulating layer I2.

The manufacturing method of the at least one insulating layer 130 in this embodiment is described below. Please refer to FIG. 2 , FIG. 3 and FIG. 4 at the same time, a light-shielding conductor layer SM is formed on the predetermined formation area of the active element 122 of the substrate 110 . In addition, the buffer layer I0 may be selectively formed before the active device 122 is fabricated on the substrate 110 . Next, the active layer of the active element 122 composed of the semiconducting layer S, the gate insulating layer I1 between the active layer and the gate of the active element 122, and the first conductive layer C1 are sequentially formed on the buffer layer I0 The gate and gate line GL of the active element 122 formed, the interlayer insulating layer I2 between the gate line GL and the data line DL, the source and drain of the active element 122 formed by the second conductive layer C2, and The data line DL and the transition line TL, the flat layer I3 between the pixel electrode 124 and the data line DL, and the pixel electrode 124 formed by the third conductive layer C3. In other words, the steps of forming the transition lines TL of the present invention can be integrated into the steps of forming the data lines DL and the source and drain electrodes of the active device 122 , and there is no need to add another mask or process to form the transition lines TL . In addition, since the patch cord TL is integrated in the forming step of the data line DL, the material of the patch cord TL includes the material of the data line DL. In this embodiment, for example, the patch cord TL and the data line DL are made of the same material. All are composed of the second conductive layer. In some embodiments, in addition to the material of the data line DL, the material of the transition line TL may further include other conductive layers (described in detail in the following embodiments).

In this embodiment, the gate line GL is the first conductive layer C1, and the transition line TL and the data line DL are formed by the second conductive layer C2 different from the first conductive layer C1. Based on the consideration of conductivity, in this embodiment, the first conductive layer C1 and the second conductive layer C2 are made of metal materials. Specifically, the material of the first conductive layer C1 in this embodiment is, for example, molybdenum, and the material of the second conductive layer C2 is, for example, titanium/aluminum/titanium. However, the present invention is not limited to this. The conductive layer C2 can also use other metal materials or stacks of other metal materials or other conductive materials. The metal is, for example, titanium (Ti), aluminum (Al), silver (Ag), iron (Fe), nickel (Ni), molybdenum (Mo), tungsten (W). Other conductive materials are, for example, alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials, but the invention is not limited thereto.

In addition, the height of the transition line TL or the data line DL on the substrate 110 is defined as, for example, the vertical distance from the bottom of the transition line TL or the data line DL to the surface of the substrate 110 . For example, in FIG. 4, cable TL bottom surface 110 in direct contact with the substrate, so that the height H _T switch wiring TL on the substrate 110 is zero. On the other hand, the data lines DL according to the height H _D of the present embodiment is substantially equivalent to the buffer layer I0, a gate insulating layer, the total thickness of the interlayer insulating layers I1 and I2 layer. In some embodiments, the buffer layer I0, the gate insulating layer I1, the interlayer insulating layer I2 and the planarization layer I3 can be made of inorganic insulating materials or organic insulating materials, wherein the inorganic insulating materials include silicon oxide and silicon nitride Or silicon oxynitride, etc., and organic insulating materials include polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP) or polyimide (PI) and the like.

A manufacturing process of the first opening 130H of the at least one insulating layer 130 is further described below. The buffer layer I0, the active layer of the active element 122, the gate insulating layer I1, the gate and gate lines GL, the interlayer insulating layer I2, etc. are formed on the substrate 110 in the same manner as described above. Next, before the step of forming the second conductive layer C2, a stack of the buffer layer I0, the gate insulating layer I1 and the interlayer insulating layer I2 is formed on the predetermined region of the substrate 110 for forming the data lines DL. Next, a patterning process is performed on the stack of the buffer layer I0 , the gate insulating layer I1 and the interlayer insulating layer I2 to form the exposed substrate 110 in the display area of the pixel structure 120 (ie, the area covered by the pixel electrode 124 ). the first opening 130H. In this step, a process of patterning the interlayer insulating layer I2 may also be included, so as to form the first via VIA1 , the second via via VIA2 and the third via via VIA3 shown in FIG. 2 in the interlayer insulating layer I2 .

Next, a second conductive layer C2 is formed on the substrate 110, and a patterning process is performed on the second conductive layer C2, so as to directly form the transition lines TL disposed on the display area on the substrate 110, and at the same time in the aforementioned stack ( A data line DL is formed on the buffer layer I0, the gate insulating layer I1 and the interlayer insulating layer I2). In this way, the transition line TL can be disposed in the first opening 130H and directly contact with the substrate 110 . After that, the planarization layer I3 covering the first opening 130H is formed. Next, the pixel electrode 124 is formed on the flat layer I3.

The electronic device produced by the above process is made, cable TL height H _T of the substrate 110 is less than the height H _D data line DL on the substrate 110. In addition, in some embodiments, as shown in FIG. 2 , in the step of forming the second conductive layer C2 , a first conduction structure penetrating through the first through hole VIA1 may be further formed in the first through hole VIA1 , and the transfer The line TL is connected to one of the plurality of gate lines GL through the first conduction structure. In this step, a second conduction structure penetrating through the second through hole VIA2 can also be formed in the second through hole VIA2, and the source electrode of the active element 122 is connected to the data line DL through the second conduction structure. In this step, a third conduction structure penetrating through the third through hole VIA3 can also be formed in the third through hole VIA3, and the drain electrode of the active element 122 is connected to the pixel electrode 124 through the third conduction structure.

Here, the gate line GL and the transition line TL are used for providing scan signals to the pixel structure 120 , and the data line DL is used for providing data signals to the pixel structure 120 . In other words, although the transition line TL and the data line DL are adjacent to each other, they are used to transmit different types of signals. Under such a circuit arrangement, the coupling of the transition line TL and the data line DL may affect the signal transmission quality of each other. Especially, when the transition line TL and the data line DL are coplanar, the interference of signal coupling is more serious. However, in the electronic device 100A of the present invention, before forming the data lines DL and the transition lines TL, the film layer under the transition lines TL is removed in advance, so that the transition formed by the second conductive layer C2 can be achieved. line TL and the data lines DL is disposed on the substrate 110 are not coplanar, e.g. patch cord TL embodiment according to the present embodiment the height H _T is zero on the substrate 110, data line DL is less than the height H _D of the substrate 110. Therefore, the height difference between the patch line TL and the data line DL helps to reduce the interference between the patch cable TL and the data line DL, and helps to ensure the signal transmission quality of the patch cable TL and the data line DL, so that the The functions performed by the electronic device (eg, screen display, touch sensing, etc.) can meet expectations.

FIG. 5 is a schematic diagram of another embodiment of the cross-section along the section line AA and the section line BB in the electronic device of FIG. 2 . The cross-sectional view of the electronic device 100B in FIG. 5 is substantially similar to the cross-sectional view of the electronic device 100A in FIG. 4 , and the relative relationship between each film layer and each circuit can be referred to the previous embodiment, and will not be repeated here. Specifically, the present embodiment is different from the embodiment of FIG. 4 in that the electronic device 100B has a buffer layer I0 between the transition line TL and the substrate 110 , which is not in direct contact. Thus, cable TL embodiment of the height H _T of the present embodiment on the substrate 110 substantially corresponds to the thickness of the buffer layer is I0, and the height H _D data line DL on the substrate 110 substantially corresponds I0 buffer layer, the gate electrode interlayer insulating layer I1 and the total thickness of the insulating layer I2, cable TL height H on the substrate 110 is less than the thickness of _T data line DL on the substrate 110. In this embodiment, the height difference between the transition line TL and the data line DL is substantially equivalent to the sum of the film thicknesses of the gate insulating layer I1 and the interlayer insulating layer I2 .

The electronic device 100B of the present embodiment helps to reduce the interference between the patch cable TL and the data line DL, and helps to ensure the signal transmission quality of the patch cable TL and the data cable DL. The buffer layer I0 is disposed on the substrate 110 , so that the adhesion between the transition line TL and the substrate 110 can be increased, and the reliability of the electronic device 100 can be improved.

FIG. 6 is a schematic diagram of another embodiment of the cross-section along the section line A-A and the section line B-B in the electronic device of FIG. 2 . The cross-sectional view of the electronic device 100C in FIG. 6 is substantially similar to the cross-sectional view of the electronic device 100A in FIG. 4 , and the relative relationship between each film layer and each circuit can be referred to the previous embodiment, and will not be repeated here. Specifically, the present embodiment is different from the embodiment of FIG. 4 in that, in the electronic device 100C, the transition line TL is formed by directly stacking and paralleling the light-shielding conductive layer SM and the second conductive layer C2 of different film layers. Specifically, in the present embodiment, the transfer line TL can be formed by directly stacking the upper and lower layers of the transfer bottom layer TL1 and the transfer top layer TL2 in parallel. The transition bottom layer TL1 is, for example, a light-shielding conductor layer SM formed on the substrate 110 in advance before the active element 122 is formed. Next, each film layer of the active element 122 is formed on the light-shielding semiconductor SM by the same manufacturing process of the aforementioned electronic device 100A. In addition, in the above-mentioned display area of the pixel structure 120 , the stack of the buffer layer I0 , the gate insulating layer I1 and the interlayer insulating layer I2 is patterned to form a first opening 130H to be exposed in the first opening 130H Transfer the bottom layer TL1. After that, a second conductive layer C2 is formed on the substrate 110, and a patterning process is performed on the second conductive layer C2 to form a transfer top layer TL2 on the transfer bottom layer TL1, and the transfer top layer TL2 and the transfer bottom layer TL1 are directly stacked. In this step, the data lines DL disposed on the stack of the buffer layer I0 , the gate insulating layer I1 and the interlayer insulating layer I2 are simultaneously formed. In this way, the material of the transition line TL in this embodiment includes the transition bottom layer TL1 formed by the light-shielding conductor layer SM and the transition top layer TL2 formed by the second conductive layer C2.

The electronic device 100C of this embodiment helps to reduce the interference between the patch line TL and the data line DL, and helps to ensure the signal transmission quality of the patch cable TL and the data line DL. Different conductive layers are directly stacked and connected in parallel, so the impedance of the patch cable TL can be further reduced, and the signal transmission quality of the patch cable TL can be further improved. In addition, since the overall thickness of the patch cord TL is increased, the topography difference between the patch cord TL and the data line DL can be reduced, and the possibility of disconnection of the patch cord TL due to the difference in topography can be reduced. improve the process yield.

FIG. 7 is a schematic partial top view of an electronic device according to the present invention. The electronic device 100D of FIG. 7 is substantially similar to the electronic device 100 of FIG. 1 , and the relative relationship between each film layer and each circuit can be referred to the foregoing content. The electronic device 100D includes a substrate 110 , gate lines GL1 to GL3 , data lines DL1 to DL4 , a transition line TL, and a plurality of pixel structures 120R, 120G, and 120B. The pixel structures arranged in a row along the second direction D2, for example, the pixel structure 120B are sandwiched between the two data lines DL1 and DL2. The transition line TL is disposed between the data line DL1 and the pixel electrode 124 to which it is connected. The relative relationship between the gate lines GL1 to GL3, the data lines DL1 to DL4, the transition lines TL, the pixel structure 120, and the height H _{T of the} transition lines TL on the substrate 110 is smaller than the height H of the data lines DL on the substrate 110 _{The film layer relationship of D} can be referred to the foregoing embodiments, and will not be repeated here. This embodiment is different from the embodiment of FIG. 1 in that the design types of the active elements 122 of the pixel structures 120 in the first row and the second row of the electronic device 100D are different, and the active elements of the pixel structures 120 located in the same row 122 are respectively electrically connected with the data lines on different sides. Specifically, taking the leftmost pixel structure 120R as an example, the pixel structure 120R in the first row is electrically connected to the data line DL3 on the right through the active element 122 extending to the right. The pixel structure 120R in the second row is electrically connected to the data line DL4 on the left through the active element 122 extending to the left, and in the same row of pixel structures, the active elements in the first row and the second row of pixel structures are electrically connected to the left data line DL4. 122 are left and right mirrored to each other.

In the electronic device 100 of this embodiment, in addition to helping to reduce the interference between the patch line TL and the data line DL, and helping to ensure the signal transmission quality of the patch line TL and the data line DL, the resistive-capacitive load (RC loading) can be reduced.

To sum up, in the electronic device of the embodiment of the present invention, the height of the patch wires on the substrate is smaller than the height of the data wires on the substrate, so that adjacent patch wires and data wires that transmit different signals can be arranged on the substrates separately are not coplanar to reduce the adverse effects caused by the coupling between lines. In addition, in some embodiments, the patch cord may be formed by stacking different conductive layers in parallel, thereby further reducing the impedance of the patch cord, or reducing the possibility of the patch cord being disconnected due to the influence of terrain. Therefore, the electronic device of the embodiment of the present disclosure can have better quality.

100, 100A, 100B, 100C, 100D: electronic device 110: substrate 120, 120R, 120G, 120B: pixel structure 124: pixel electrode 122: active element 124: pixel electrode 130: insulating layer 130H: first opening C1 : C2 first conductive layer: the second conductive layer the DL: data line D1: a first direction D2: DIS1 second direction: the first distance DIS2: second distance GL: gate line H _T, H _D: height I0: buffer Layer I1: Gate insulating layer I2: Interlayer insulating layer I3: Flat layer S: Semi-conductive layer SM: Light-shielding conductor layer TL: Transfer line TL1: Transfer bottom layer TL2: Transfer top layer VIA1: The first through hole VIA2: The first The second through hole VIA3: the third through hole

FIG. 1 is a schematic partial top view of an electronic device according to the present invention. FIG. 2 is a schematic diagram of an enlarged embodiment of the dotted frame in the electronic device of FIG. 1 . FIG. 3 is a schematic diagram of an embodiment of the cross section along the section line A-A and the section line B-B in the electronic device of FIG. 2 . FIG. 4 is a partial enlarged view of the film layer below the data line in FIG. 3 . FIG. 5 is a schematic diagram of another embodiment of the cross-section along the section line A-A and the section line B-B in the electronic device of FIG. 2 . FIG. 6 is a schematic diagram of another embodiment of the cross-section along the section line A-A and the section line B-B in the electronic device of FIG. 2 . FIG. 7 is a schematic partial top view of an electronic device according to the present invention.

100A: Electronics

110: Substrate

124: pixel electrode

130: Insulation layer

C1: The first conductive layer

C2: second conductive layer

C3: the third conductive layer

DL: data line

DIS1: first distance

DIS2: Second distance

GL: gate line

I0: buffer layer

I1: gate insulating layer

I2: Interlayer insulating layer

I3: flat layer

S: semiconducting layer

SM: light-shielding conductor layer

TL: transfer cable

H _T, H _D: Height

VIA3: The third through hole

Claims (14)

An electronic device, comprising: a substrate; a plurality of gate lines arranged on the substrate and extending along a first direction; data lines arranged on the substrate and extending along a second direction, wherein the first The direction intersects the second direction; the patch cord is arranged on the substrate, the patch cord is parallel to the data line and adjacent to each other, and the patch cord connects the gate lines of the plurality of gate lines. In one of them, at least a part of the patch line and the data line are formed in the same second conductive layer, and in the top view of the electronic device, the data line and the patch cable are staggered; a plurality of pixel structures, Disposed on the substrate, one of the plurality of pixel structures is surrounded by the adjacent two of the plurality of gate lines and the transition line and includes a pixel electrode and an active element, wherein the The height of the patch wire on the substrate is smaller than the height of the data wire on the substrate; and at least one insulating layer, wherein the at least one insulating layer includes a first opening, and the first opening is on the substrate The vertical projection range of the pixel electrode covers the vertical projection range of the pixel electrode on the substrate, the transfer wire is arranged in the first opening, and the data wire is arranged on the at least one insulating layer. The electronic device of claim 1, wherein the at least one insulating layer is formed by stacking insulating materials of different materials. The electronic device according to claim 1, wherein the material of the patch cable is the same as the material of the data cable. The electronic device according to claim 1, wherein in the pixel structure, the patch cords are in contact with the substrate, and the height difference between the patch cords and the data cables on the substrate is the film thickness of the at least one insulating layer. The electronic device according to claim 4, wherein the at least one insulating layer comprises a buffer layer, a gate insulating layer and an interlayer insulating layer, the buffer layer is in contact with the substrate, and the film layer where the gate insulating layer is located It is located between the film layer of the active layer of the active element and the film layer of the gate electrode, and the film layer where the interlayer insulating layer is located is located between the film layer of the gate line and the film layer of the data line. The height difference between the transition line and the data line is the sum of the film thicknesses of the buffer layer, the gate insulating layer and the interlayer insulating layer. The electronic device according to claim 1, wherein in the pixel structure, a buffer layer is included between the patch wire and the substrate, the buffer layer is included between the data wire and the substrate, and the at least one insulating layer. The electronic device according to claim 6, wherein the at least one insulating layer comprises a gate insulating layer and an interlayer insulating layer, and the film layer where the gate insulating layer is located is located between the film layer and the gate electrode of the active layer of the active element. Between the film layers of the poles, the film layer of the interlayer insulating layer is located between the film layer of the gate line and the film layer of the data line, and the height difference between the transfer line and the data line is The sum of the film thicknesses of the gate insulating layer and the interlayer insulating layer. The electronic device according to claim 1, wherein a light-shielding conductor layer is further included between the active element and the substrate, the data line is composed of a second conductive layer, and the patch line is composed of the light-shielding conductor layer It is directly stacked with the second conductive layer. The electronic device of claim 1, wherein the at least one insulating layer comprises an interlayer insulating layer located between the gate line and the data line, and the interlayer insulating layer further comprises a first through hole and a through hole. the first conduction structure of the first through hole, and the connecting wire is connected to one of the plurality of gate lines through the first conduction structure. The electronic device according to claim 9, wherein the interlayer insulating layer further comprises a second through hole and a second conduction structure passing through the second through hole, and the source of the active element passes through the second conduction structure Connect the data line. The electronic device according to claim 10, wherein the interlayer insulating layer further comprises a third through hole and a third conduction structure passing through the third through hole, and the drain of the active element passes through the third conduction structure Connect the pixel electrodes. The electronic device of claim 1, wherein the patch cords and the data lines have zigzag patterns parallel to each other. The electronic device of claim 1, wherein the pixel electrodes overlap the patch lines in a direction perpendicular to the substrate. The electronic device according to claim 1, wherein in a top view of the electronic device, the edge of the pixel electrode is located between the patch line and the data line, and the edge of the pixel electrode is connected to the The patch cords are projected on the substrate at a distance of A distance is a second distance between the edge of the pixel electrode and the data line projected on the substrate, the first distance is at least 2 microns, and the second distance is at least 3 microns.

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