TWI759127B - Substrate package structure - Google Patents

Abstract

A substrate package structure includes a substrate, an insulation layer, an electrode, and a sealant. The substrate has a display area and a peripheral area. The insulation layer is disposed over the substrate. The insulation layer has a protruding portion positioned in the peripheral area and surrounding the display area. The electrode is disposed on the protruding portion. The sealant has a first portion and a second portion. The first portion is disposed on the insulation layer outside the protruding portion, and the second portion is disposed on the electrode.

Description

Substrate package structure

The present invention relates to a substrate packaging structure.

With the advancement of science and technology, touch display devices have been widely used in various fields, especially liquid crystal display devices. Because of their superior characteristics such as thin body, low power consumption and no radiation, they have gradually replaced traditional cathode ray tube displays. The device is used in many types of electronic products, such as mobile phones, portable multimedia devices, notebook computers, LCD TVs, and LCD screens.

A common liquid crystal display device mainly includes an array substrate, an opposite substrate, and a liquid crystal layer sandwiched between the two substrates. The array substrate and the opposite substrate are bonded by a sealant, and the liquid crystal layer is sealed on the two substrates by the sealant. between. On the one hand, the sealant can be a UV-curable sealant, which must be irradiated with UV light in a sufficient light-transmitting space to provide the adhesive effect. However, with the market demand, the display device is stimulated to develop towards a narrow bezel design. Therefore, the use of UV-curable sealant is in conflict with the narrow bezel design.

On the other hand, the sealant may be a heat-curable sealant. Generally speaking, the heat-curing sealant has an extremely slow heating and curing speed, which may easily cause problems such as liquid crystal contamination and liquid crystal puncture. Therefore, how to improve the curing speed of sealant under the requirement of narrow frame design has become an important topic.

The present invention provides a substrate packaging structure for improving the curing speed of the sealant, thereby avoiding the risks of liquid crystal contamination and liquid crystal puncture.

An aspect of the present invention provides a substrate packaging structure, including a substrate, an insulating layer, an electrode, and a sealant. The substrate has a display area and a peripheral area surrounding the display area. The insulating layer is disposed above the substrate, and has a raised portion located in the peripheral area and surrounding the display area. The electrodes are arranged on the protrusions. The sealant has a first part and a second part. The first portion is on the insulating layer around the protrusion, and the second portion is on the electrode.

In one or more embodiments of the present invention, the sealant completely covers the electrodes.

In one or more embodiments of the present invention, the top-view shape of the electrode is a comb shape, a snake shape or a grid shape.

In one or more embodiments of the present invention, the electrode completely covers the raised portion.

In one or more embodiments of the present invention, the distance between the inner side of the raised portion and the display area is at least 50 microns.

In one or more embodiments of the present invention, the sealant has an upper width and a lower width, and the upper width is greater than the lower width.

In one or more embodiments of the present invention, the second portion has a width, and the width is between 1/3 times and 1/2 times the width of the upper portion.

In one or more embodiments of the present invention, the substrate packaging structure further includes a pair of opposing substrates disposed opposite to the substrates, and the insulating layer, the electrodes and the sealant are sandwiched between the substrates and the opposing substrates.

In one or more embodiments of the present invention, the first portion of the sealant has a first thickness, the second portion of the sealant has a second thickness, and the second thickness is 1/4 times to 3/4 times the first thickness. between.

In one or more embodiments of the present invention, the substrate packaging structure further includes a black matrix disposed under the opposite substrate, and the black matrix is located between the opposite substrate and the sealant.

In one or more embodiments of the present invention, the substrate package structure further includes a flat layer disposed between the black matrix and the sealant.

In one or more embodiments of the present invention, the electrodes comprise metal oxides or metals.

In one or more embodiments of the present invention, the substrate package structure further includes an integrated circuit on one side of the substrate.

In one or more embodiments of the present invention, the substrate package structure further includes a plurality of scan lines, a plurality of data lines, a plurality of data lines, a plurality of pixel electrodes, and a plurality of pixel electrodes. Multiple selection lines. A plurality of scan lines are arranged in the display area of the substrate. A plurality of data lines are arranged in the display area of the substrate and are staggered with the scan lines. A plurality of active elements are arranged in the display area of the substrate. Each active element is electrically connected to one of the scan lines and one of the data lines. A plurality of pixel electrodes are arranged in the display area of the substrate. Each pixel electrode is electrically connected to one of the active elements. A plurality of selection lines are disposed in the display area of the substrate, and are interlaced with the scan lines to form a plurality of first interlaces and a plurality of second interlaces. The selection line is electrically connected to the scan line at the first interlace, and is electrically insulated from the scan line at the second interlace.

The following will clearly illustrate the spirit of the present invention with drawings and detailed descriptions. After understanding the preferred embodiments of the present invention, anyone with ordinary knowledge in the technical field can make changes and modifications by the techniques taught in the present invention. without departing from the spirit and scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The same reference numerals refer to the same elements throughout the specification. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" may include an orientation of "lower" and "upper", depending on the particular orientation of the figures. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can include an orientation of above and below.

FIG. 1 is a schematic top view of an embodiment of the substrate package structure 10 of the present invention. FIG. 2 is a schematic cross-sectional view of the substrate package structure 10 of FIG. 1 along the section line 2-2'. Please refer to FIG. 1 and FIG. 2 at the same time, the substrate package structure 10 includes a substrate 110 , an insulating layer 120 , an electrode 130 and a sealant 140 . Specifically, the substrate 110 has a display area AA and a peripheral area PA surrounding the display area AA. In various embodiments, the substrate 110 can be a single-layer or multi-layer structure, and its material can be glass, quartz, transparent polymer material or other suitable materials. In various embodiments, the substrate 110 may be a rigid substrate or a flexible substrate. In various embodiments, the substrate 110 is an array substrate.

Please continue to refer to FIG. 1 and FIG. 2 , the insulating layer 120 is disposed above the substrate 100 . More specifically, the insulating layer 120 has a raised portion 122 located in the peripheral area PA and surrounding the display area AA. In some embodiments, the raised portion 122 has a substantially flat surface. This design can reduce the thickness of the subsequent sealant on it, thereby speeding up the pre-curing speed of this part of the sealant. In some embodiments, the material of the insulating layer 120 may include polymer materials such as polyimide-based resin, epoxy-based resin, or acrylic-based resin, but is not limited thereto. In some embodiments, the insulating layer 120 may be firstly deposited over the substrate 100 comprehensively using physical vapor deposition or chemical vapor deposition. Next, the insulating layer 120 having the protrusions 122 is formed by an etching process. In various embodiments, there is a distance D between the inner side of the protruding portion 122 and the display area AA, and the distance D is at least 50 microns. It should be noted that the distance D is defined to prevent the subsequent sealant disposed on the raised portion 122 from directly or indirectly contacting the liquid crystal in the display area AA before being cured, thereby causing liquid crystal contamination and puncturing.

In various embodiments, the substrate package structure 10 may further include a gate dielectric layer 210 and a protective layer 220 disposed on the substrate 110 in sequence. In some embodiments, the gate dielectric layer 210 may be a single-layer or multi-layer structure, which may include organic dielectric materials, inorganic dielectric materials, or a combination thereof. The organic dielectric material is, for example, polyimide (PI), other suitable materials, or a combination of the above; the inorganic dielectric material is, for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination of the above . In certain embodiments, the protective layer 220 may be a single-layer or multi-layer structure, which may include an organic dielectric material. Organic dielectric materials are, for example, colorless or colored photoresist, polyimide, polyester, benzocyclobutene (BCB), polymethylmethacrylate (PMMA), polyvinylphenol (poly(4) -vinylphenol), PVP), polyvinyl alcohol (PVA), polytetrafluoroethylene (PTFE), or other suitable organic insulating materials.

Please continue to refer to FIG. 1 and FIG. 2 , the electrode 130 is disposed on the protruding portion 122 . In various embodiments, electrode 130 includes a metal oxide or metal. For example, metal oxides include indium tin oxide (ITO). For example, metals include copper, aluminum, nickel, silver, chromium, titanium, molybdenum, composite layers of the above materials, or alloys of the above materials. In some embodiments, the method of forming the electrode 130 includes metal chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or other suitable methods.

3A, 3B, 3C, and 3D are schematic top views illustrating various embodiments of the electrode 130 of the present invention. As shown in FIG. 3A , the electrode 130 covers the entire surface of the protruding portion 122 . As shown in FIG. 3B , the planar shape of the electrode 130 is a comb shape. As shown in FIG. 3C , the planar shape of the electrode 130 is a serpentine shape. As shown in FIG. 3D, the planar shape of the electrode 130 is a grid shape.

FIG. 4 is a schematic top view illustrating an embodiment of the wiring of the electrode 130 of the present invention. In order to effectively manufacture a plurality of liquid crystal display panels based on the consideration of mass production efficiency, in the process, the unit area of the pre-formed liquid crystal display panel is usually planned on the large mother substrate 410 , as shown in FIG. 4 . During the manufacturing process, the electrodes 130 (shown by thick lines in the figure) in each substrate package structure 10 may be extended to the periphery of the mother substrate 410 . Next, the electrodes 130 extending around the mother substrate 410 can be contacted with probes (not shown), and a voltage can be applied at the same time. After the voltage is applied, the temperature of the electrode 130 can be further increased rapidly, so that the sealant (the second part 144 ) located above the electrode 130 is rapidly heated and pre-cured. In this way, even if the first part 142 of the sealant has not been cured, it will not have any influence on the liquid crystal in the display area AA. For example, in the embodiment in which the electrode 130 comprises ITO, applying a voltage of 25V to the ITO electrode can raise the temperature to about 90°C within 1 minute. This design can reduce the contact area between the sealant and the liquid crystal in the display area, thereby reducing the risks of liquid crystal puncture and liquid crystal contamination. In addition, unnecessary regions may be cut off along the cutting line SL. It should be noted that the cutting step can be performed before or after the voltage is applied.

Please return to FIG. 1 and FIG. 2 , the sealant 140 has a first part 142 and a second part 144 , wherein the first part 142 is located on the insulating layer 120 around the protrusion 122 , and the second part 144 is located on the electrode 130 . In various embodiments, the sealant 140 is a heat-curable sealant. In various embodiments, the sealant 140 has an upper width W _up and a lower width W _Lo , and the upper width W _up is greater than the lower width W _Lo . In various embodiments, the second portion 144 has a width W ₁₄₄ , and the width W ₁₄₄ is between 1/3 times to 1/2 times the upper width W _up .

FIG. 5 is a schematic cross-sectional view of another embodiment of the substrate packaging structure 10 of the present invention. In another alternative embodiment, the second portion 144 of the sealant 140 completely covers the electrode 130 , as shown in FIG. 5 .

Returning to FIG. 2, in various embodiments, the first portion 142 of the sealant 140 has a first thickness TH1, the second portion 144 of the sealant 140 has a second thickness TH2, and the second thickness TH2 is the first thickness TH2. 1/4 times to 3/4 times the thickness of TH1. As mentioned above, since the second thickness TH2 is smaller than the first thickness TH1 and the second portion 144 is located on the electrode 130 , the effect of pre-curing the second portion 144 of the sealant 140 is excellent. It should be noted that, according to the thickness and width of the second part 144 , an appropriate material and operating voltage of the electrode 130 must be selected, in order to achieve the best heating effect to achieve the pre-curing of the sealant of the second part 144 . It should be noted that, in order to avoid substantial collision or friction when the subsequent substrate 110 is joined to the opposite substrate, an embodiment of the present disclosure defines the relationship between the first thickness and the second thickness.

As shown in FIG. 2 , in various embodiments, the substrate package structure 10 may further include a pair of facing substrates 230 disposed opposite to the substrate 110 . More specifically, the insulating layer 120 , the electrodes 130 and the sealant 140 are sandwiched between the substrate 110 and the opposite substrate 230 . In various embodiments, the opposite substrate 230 is a light-transmitting substrate, and its material includes, for example, glass, polycarbonate, polyethylene terephthalate, cycloolefin polymer, polyethylene, polyetheretherketone, polyethylene Imide, cyclic olefin copolymer, polyetherimide, polymethyl methacrylate, polyethylene naphthalate, or a combination thereof.

As shown in FIG. 2, in various embodiments, the substrate package structure 10 may further include a black matrix (BM) 240 disposed under the opposite substrate 230, and the black matrix 240 is located between the opposite substrate 230 and the frame glue between 140. Since the opposite substrate 230 can be used as a carrier for carrying the black matrix 240 , the black matrix 240 can be directly formed on the flat surface of the opposite substrate 230 by a general printing method. For example, the printing method is spin coating, screen printing, gravure printing, slot die coating, ink jet printing ), deposition, spray coating, or sputtering and other suitable methods. In other alternative embodiments, in order to meet various design requirements, the black matrix 240 can be replaced by other colors, such as white and the like.

As shown in FIG. 2 , in various embodiments, the substrate package structure 10 may further include a planarization layer 250 disposed under the black matrix 240 , and the planarization layer 250 is located between the black matrix 240 and the sealant 140 . Generally speaking, the planarization layer 250 may include siloxane, polyimide (PI), epoxy resin (Epoxy), polymethyl methacrylate (PMMA), acryl (Acryl), phenolic resin (Novolak) or other suitable materials. In some embodiments, the planarization layer 250 may be a single film layer. In some other embodiments, the planarization layer 250 may also be formed by stacking a plurality of film layers. In various embodiments, the planarization layer 250 may be fully deposited on the surface of the black matrix 240 using physical vapor deposition, chemical vapor deposition, or photoresist coating. Since the black matrix 240 in the display area AA has a patterned shape, the flat layer 250 provides a relatively flat surface to facilitate the bonding between the subsequent substrate 110 and the opposite substrate 230 .

Returning to FIG. 1 , in various embodiments, the substrate package structure 10 may further include an integrated circuit 260 located beside one side of the substrate 110 . For example, FIG. 1 shows that the integrated circuit 260 is disposed on the lower side of the substrate 110 . In various embodiments, the integrated circuit 260 has a plurality of pads (or pins) (not shown). In some embodiments, the integrated circuit 260 can selectively use a chip on film (COF) packaging process, a chip on glass (COG) packaging process, a chip on board (COB) packaging process , Tape Automated Bonding (TAB) packaging process or other suitable process is arranged on the lower side of the substrate 110 and is linearly connected with the peripheral circuits.

FIG. 6 is a schematic top view of an embodiment of the substrate package structure 10 of the present invention. As shown in FIG. 6 , the substrate package structure 10 further includes a plurality of scan lines 510 , a plurality of data lines 520 , a plurality of active elements 530 , a plurality of pixel electrodes 540 and a plurality of selection lines 550 , all of which are disposed on the display of the substrate 110 . District AA. Specifically, the scan lines 510 and the data lines 520 are staggered with each other. In some embodiments, the scan lines 510 extend along the first direction D1 and are arranged along the second direction D2. The data lines 520 extend along the second direction D2 and are arranged along the first direction D1. It should be noted that the first direction D1 is different from the second direction D2. In some embodiments, the first direction D1 is substantially perpendicular to the second direction D2.

Please continue to refer to FIG. 6 , each active element 530 is electrically connected to one of the scan lines 510 and one of the data lines 520 . In some embodiments, the active element 530 is, for example, a thin film transistor. In more detail, the thin film transistor may at least include a gate electrode, a source electrode, a drain electrode and a semiconductor layer. Furthermore, the active element 530 may be a bottom gate type thin film transistor, a top gate type thin film transistor, a multi-gate type thin film transistor or other suitable types of thin film transistors. In some embodiments, the material of the semiconductor layer may include polysilicon, amorphous silicon, monocrystalline silicon, microcrystalline silicon, nanocrystalline silicon, organic semiconductor, metal oxide semiconductor, carbon nanotube, other suitable semiconductor materials or A combination of the above materials.

Please continue to refer to FIG. 6 , each pixel electrode 540 is electrically connected to one of the active elements 530 . For example, each pixel electrode 540 can be electrically connected to the corresponding scan line 510 and the corresponding data line 520 , wherein the gate electrode of the active element 530 can be electrically connected to the scan line 510 , and the gate of the active element 530 can be electrically connected to The source electrode is electrically connected to the data line 520 . In some embodiments, the material of the pixel electrode 540 may include a transparent metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or indium germanium zinc oxide, But not limited to this. In addition, in some embodiments, the pixel electrode 540 may be formed through a lithography etching process. The shape of the pixel electrode 540 shown in FIG. 6 is for illustration only, and the shape of the pixel electrode 540 can be adjusted according to different layout design requirements.

Please continue to refer to FIG. 6 , the select lines 550 and the scan lines 510 are interleaved to form a plurality of first interlaces X1 and a plurality of second interlaces X2. More specifically, the selection lines 550 are electrically connected to the scan lines 510 at the first intersections X1 , and are electrically insulated from the scan lines 510 at the second intersections X2 . In some embodiments, the select line 550 and the data line 520 extend in the same direction. It should be noted that the data line 520 and the select line 550 are electrically connected to the integrated circuit 260 to receive signals from the integrated circuit 260 .

To sum up, the substrate package structure of the present disclosure basically includes an insulating layer with a protruding portion in the peripheral region, and the protruding portion is provided with electrodes and surrounds the display region to form an electrode wall. The raised portion can reduce the thickness of the sealant disposed thereon, thereby increasing the curing speed of the sealant. In addition, the design of the electrodes can also rapidly heat the sealant above the raised portion after applying a voltage, which further improves the curing effect of the sealant. Therefore, the risk of liquid crystal puncture and liquid crystal contamination caused by excessive contact time between the uncured sealant and the liquid crystal can be avoided.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the appended patent application.

10: Substrate packaging structure 110: Substrate 120: Insulating layer 122: Protrusion 130: Electrode 140: Sealant 142: First part 144: Second part 210: Gate dielectric layer 220: Protective layer 230: Opposing substrate 240 : Black matrix 250: Flat layer 260: IC 2-2' : Line 410: Mother substrate 510: Scan line 520: Data line 530: Active element 540: Pixel electrode 550: Select line AA: Display area PA: Peripheral area D: distance D1: first direction D2: second direction SL: cutting line TH1: first thickness TH2: second thickness W ₁₄₄ : width W _up : upper width W _Lo : lower width X1: first intersection X2: second two staggered

FIG. 1 is a schematic top view showing an embodiment of the substrate packaging structure of the present invention. FIG. 2 is a schematic cross-sectional view of the substrate packaging structure of FIG. 1 along the section line 2-2'. 3A, 3B, 3C, and 3D are schematic top views illustrating various embodiments of the electrodes of the present invention. FIG. 4 is a schematic top view showing an embodiment of the electrode wiring of the present invention. FIG. 5 is a schematic cross-sectional view illustrating another embodiment of the substrate packaging structure of the present invention. FIG. 6 is a schematic top view illustrating an embodiment of the substrate packaging structure of the present invention.

Domestic storage information (please note in the order of storage institution, date and number) without Foreign deposit information (please note in the order of deposit country, institution, date and number) without

10: Substrate packaging structure 110: Substrate 120: Insulating layer 122: Protrusion 130: Electrode 140: Sealant 142: First part 144: Second part 210: Gate dielectric layer 220: Protective layer 230: Opposing substrate 240 : black matrix 250: flat layer 2-2' : line AA: display area PA: peripheral area D: distance TH1: first thickness TH2: second thickness W ₁₄₄ : width W _up : upper width W _Lo : lower width

Claims (16)

A substrate packaging structure, comprising: a substrate having a display area and a peripheral area surrounding the display area; an insulating layer disposed above the substrate, the insulating layer having a raised portion located in the peripheral area and surrounding the display an electrode disposed on the raised portion; and a sealant having a first portion and a second portion, the first portion is located on the insulating layer on the periphery of the raised portion, and the second portion is located on the On the electrodes, the sealant has an upper width and a lower width, and the upper width is larger than the lower width. The substrate package structure of claim 1, wherein the second portion of the sealant completely covers the electrode. The substrate packaging structure according to claim 1, wherein the top view shape of the electrode is a comb shape, a snake shape or a grid shape. The substrate package structure as claimed in claim 1, wherein the electrode fully covers the protruding portion. The substrate package structure according to claim 1, wherein a distance between the inner side of the raised portion and the display area is at least 50 microns. The substrate package structure as claimed in claim 1, wherein the first The two parts have a width, and the width is between 1/3 times and 1/2 times the width of the upper part. The substrate package structure of claim 1, wherein the first portion of the sealant has a first thickness, the second portion of the sealant has a second thickness, and the second thickness is 1/1 of the first thickness /4 times to 3/4 times. The substrate packaging structure of claim 1 further comprises a pair of opposing substrates disposed opposite to the substrate, and the insulating layer, the electrodes and the sealant are sandwiched between the substrate and the opposing substrate. The substrate package structure of claim 8, further comprising a black matrix disposed under the opposite substrate, and the black matrix is located between the opposite substrate and the sealant. The substrate package structure according to claim 9, further comprising a flat layer disposed between the black matrix and the sealant. The substrate package structure of claim 1, wherein the electrode comprises metal oxide or metal. The substrate package structure as claimed in claim 1, further comprising an integrated circuit located beside one side of the substrate. The substrate packaging structure according to claim 1, further comprising: a plurality of scan lines disposed in the display area of the substrate; a plurality of data lines disposed in the display area of the substrate and staggered with the scan lines; An active element is disposed in the display area of the substrate, each active element is electrically connected to one of the scan lines and one of the data lines; a plurality of pixel electrodes are disposed on the substrate In the display area, each of the pixel electrodes is electrically connected to one of the active elements; and a plurality of selection lines are disposed in the display area of the substrate and are interlaced with the scan lines to form a plurality of first interlaces and a plurality of second staggered places, the selection lines are electrically connected to the scan lines at the first staggered places, and electrically insulated from the scan lines at the second staggered places. A substrate packaging structure, comprising: a substrate having a display area and a peripheral area surrounding the display area; an insulating layer disposed above the substrate, the insulating layer having a raised portion located in the peripheral area and surrounding the display area, wherein a distance of at least 50 microns between the inner side of the raised portion and the display area; an electrode disposed on the raised portion; and a sealant having a first portion and a second portion, the first portion is located on the on the insulating layer on the periphery of the raised portion, and the second portion is located on the electrode. A substrate packaging structure, comprising: a substrate having a display area and a peripheral area surrounding the display area; an insulating layer disposed above the substrate, the insulating layer having a raised portion located in the peripheral area and surrounding the display area; an electrode disposed on the raised part; a sealant having a first part and a second part, the first part is located on the insulating layer on the periphery of the raised part, and the second part is located on the electrode a pair of opposite substrates, which are arranged opposite to the substrate, the insulating layer, the electrodes and the sealant are sandwiched between the substrate and the opposite substrate; and a black matrix is arranged under the opposite substrate, the black The matrix is located between the opposite substrate and the sealant. A substrate packaging structure, comprising: a substrate having a display area and a peripheral area surrounding the display area; an insulating layer disposed above the substrate, the insulating layer having a raised portion located in the peripheral area and surrounding the display area; an electrode disposed on the raised portion, wherein the electrode comprises metal oxide or metal; and a sealant having a first portion and a second portion, the first portion is located on the insulating periphery of the raised portion layer, and the second portion is located on the electrode.

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