CN204596792U - Display floater - Google Patents
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- CN204596792U CN204596792U CN201520225940.0U CN201520225940U CN204596792U CN 204596792 U CN204596792 U CN 204596792U CN 201520225940 U CN201520225940 U CN 201520225940U CN 204596792 U CN204596792 U CN 204596792U
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Abstract
The utility model discloses a kind of display floater, comprises: a substrate; One first light shield layer is positioned on substrate; Semi-conductor layer is positioned on the first light shield layer; One insulating barrier is positioned on semiconductor layer; One gate line is positioned on insulating barrier; One contact hole runs through insulating barrier, to expose semiconductor layer; And a metal level, be positioned on insulating barrier, and be electrically connected with semiconductor layer by contact hole, wherein the first light shield layer includes an overlapping region of overlying metal layer, overlapping region has one first width on a first direction, and metal level bottom an edge and contact hole of adjacent gate line between beeline on first direction be one second width, and wherein first direction is perpendicular to a bearing of trend of gate line, and the ratio of the first width and the second width is between 0.2 to 0.8.
Description
Technical field
The utility model relates to a kind of Display Technique, and particularly relates to a kind of pixel cell for display floater.
Background technology
Display unit (such as, liquid crystal display (liquid crystal display, LCD), active matrix organic light emitting display (active matrix organic light-emitting display, etc. AMOLED) be usually assemblied in electronic installation, such as laptop computer, personal digital assistant (personal digitalassistants, PDA), e-book (electronic books), projector and mobile phone etc.
In general, display floater utilizes thin-film transistor (thin film transistor, TFT) as the switch element of pixel region usually.Moreover periphery circuit region (that is, drive circuit area) also needs to use the cmos circuit be made up of TFT.The material used according to active layers is divided into amorphous silicon (a-Si) and polysilicon (poly-Si) TFT.Compared to non-crystalline silicon tft, multi-crystal TFT has the advantage of high carrier mobility and high drive circuit integrated level and is usually used in the product of high speed operation.Therefore, low temperature polycrystalline silicon (low temperature polysilicon, LTPS) becomes a kind of application newly of display technology.
Thin-film transistor as the switch element of pixel region has upper grid (top gate) or lower grid (bottom gate) structure usually.On having the thin-film transistor of grid structure display floater in, light from backlight module can by the infrabasal plate of display unit (such as, TFT substrate) irradiate below grid active layers on, thus in active layers, produce leakage current, reduce the electrical characteristics of thin-film transistor.In order to solve the problem, can a light shield layer be set below active layers.But above-mentioned light shield layer also cannot effectively stop the scattered beam produced by backlight module, and cannot maintain the electrical characteristics of thin-film transistor.
Therefore, be necessary to seek a kind of display floater, it effectively can stop that light irradiates the active layers below grid, to improve or to maintain the electrical characteristics of TFT.
Utility model content
The purpose of this utility model is to provide a kind of display floater, to solve the problem.
For reaching above-mentioned purpose, the utility model provides a kind of display floater, Bao Han ︰ mono-substrate; One first light shield layer, is positioned on substrate; Semi-conductor layer, is positioned on the first light shield layer; One insulating barrier, is positioned on semiconductor layer; One gate line, is positioned on insulating barrier; One contact hole, runs through insulating barrier, to expose semiconductor layer; And a metal level, be positioned on insulating barrier, and be electrically connected with semiconductor layer by contact hole; Wherein the first light shield layer includes an overlapping region of overlying metal layer, overlapping region has one first width on a first direction, and metal level bottom an edge and contact hole of adjacent gate line between beeline on first direction be one second width, wherein first direction is perpendicular to a bearing of trend of gate line, and the ratio of the first width and the second width is between 0.2 to 0.8.
This first light shield layer has an overlapping region overlapping with this gate line, this overlapping region has two overlapping line segments overlapping with these gate line opposite edges and one first middle section between these two overlapping line segments, these two overlapping line segments of this first light shield layer one of them there is one first length in a second direction, and this first middle section has one second length in this second direction, and wherein this second direction is parallel to this bearing of trend of this gate line, and this first length is greater than this second length.
This first light shield layer has an overlapping region overlapping with this semiconductor layer, this overlapping region has two overlapping line segments overlapping with these semiconductor layer opposite edges and one second middle section between these two overlapping line segments, these two overlapping line segments of this first light shield layer one of them there is one the 3rd length on this first direction, and this second middle section has one the 4th length on this first direction, and wherein the 3rd length is greater than the 4th length.
This display floater also comprises: the second light shield layer, between this substrate and this semiconductor layer, and has the region that a part is overlapped in this semiconductor layer and this gate line.
This display floater also comprises a resilient coating, between this first light shield layer and this semiconductor layer.
Another embodiment of the utility model provides a kind of display floater, Bao Han ︰ mono-substrate; One first light shield layer, is positioned on substrate; Semi-conductor layer, is positioned on the first light shield layer; One insulating barrier, is positioned on semiconductor layer; One gate line, is positioned on insulating barrier, and has a protuberance overlapping with semiconductor layer, and protuberance extends along a first direction, and first direction is perpendicular to a bearing of trend of gate line; One contact hole, runs through insulating barrier, to expose semiconductor layer; And a metal level, be positioned on insulating barrier, and be electrically connected with semiconductor layer by contact hole; Wherein the first light shield layer includes an overlapping region of overlying metal layer, overlapping region has one first width in a second direction, and metal level bottom an edge and contact hole of contiguous protuberance between beeline in second direction be one second width, wherein second direction is parallel to the bearing of trend of gate line, and the ratio of the first width and the second width is between 0.2 to 0.8.
This display floater also comprises one second light shield layer, between this substrate and this semiconductor layer, wherein this first light shield layer has one first curved edge overlapping with this semiconductor layer, and this second light shield layer has one second curved edge overlapping with this semiconductor layer, and this first curved edge this second curved edge adjacent.
This first light shield layer has a part and is overlapped in this semiconductor layer region crossing with this gate line.
This first light shield layer has a part and is overlapped in this protuberance, and this second light shield layer has a part is overlapped in this semiconductor layer another region crossing with this gate line.
This display floater also comprises a resilient coating, between this first light shield layer and this semiconductor layer.
The utility model has the advantage of, due to in the pixel cell of display floater, metal level and the first light shield layer have suitable overlapping region, therefore can not formed under excessive stray capacitance, effective stop is irradiated on semiconductor layer from the scattered beam of backlight module, and then improves or reduce leakage current.Moreover, because the first light shield layer and/or the second light shield layer have at least two relatively and the edge contour of indent, light shield layer and gate line and/or the stray capacitance between light shield layer and semiconductor layer therefore can be reduced further.In addition, in the situation of gate line with protuberance, first and second light shield layer has toward each other and adjacent curved edge, therefore can shorten the distance between first and second light shield layer, and then increases the aperture opening ratio of pixel cell.
Accompanying drawing explanation
Fig. 1 be the utility model one embodiment on the pixel cell of display floater, look signal;
Fig. 2 is the generalized section along 2-2 ' line in Fig. 1;
Fig. 3 A be the utility model one embodiment for looking schematic diagram at the bottom of the pixel cell of display floater;
Fig. 3 B be the utility model one embodiment for looking schematic diagram at the bottom of the pixel cell of display floater;
Fig. 4 be the utility model one embodiment for looking schematic diagram at the bottom of the pixel cell of display floater.
Symbol description
10,10 ', 10 ", 20 pixel cells
100 substrates
102a, 202a first light shield layer
102b, 202b second light shield layer
104 resilient coatings
106,206 semiconductor layers
108 insulating barriers
110,210 gate lines
110 ', 106 ', 114 ', 214 ', 220 ' edge
111a first middle section
The overlapping line segment of 111a ', 111b '
111b second middle section
112 interlayer dielectric layers
113,117,121 contact holes
114a data wire
114b, 114c metal level
116 planarization layers
118 lower floor's transparency electrodes
120 passivation protection layers
124 top transparent electrode
203 first curved edges
204 second curved edges
220 protuberances
A, C first width
B, D second width
D1 first direction
D2 second direction
L1 first length
L2 second length
L3 the 3rd length
L4 the 4th length
P pixel region
Embodiment
The display floater of the utility model embodiment is below described.But, embodiment provided by the utility model can be understood easily only for illustration made from ad hoc approach and using the utility model, and be not used to limit to scope of the present utility model.
Please refer to Fig. 1 and Fig. 2, wherein Fig. 1 shows pixel cell 10 upper schematic diagram for display floater according to the utility model one embodiment, and Fig. 2 shows the generalized section along 2-2 ' line in Fig. 1.In one embodiment, pixel cell 10 may be implemented in a display panels.Pixel cell 10 comprises: substrate 100, a 1 first light shield layer 102a and one second light shield layer 102b, semi-conductor layer 106, insulating barrier 108, contact hole 113, pair of grid lines 110, a pair of data lines 114a and metal level 114b.Substrate 100 has the pixel region P defined by pair of grid lines 110 and pair of data lines 114a.Herein, in order to simplify accompanying drawing, in Fig. 1, only show pair of data lines 114a and a gate line 110.Moreover substrate 100 can be made up of transparent material, such as glass, quartz or plastic cement, in order to the TFT substrate as display floater.
First light shield layer 102a and the second light shield layer 102b (not being illustrated in Fig. 2) is arranged on substrate 100, wherein the first light shield layer 102a and gate line 110 have an overlapping region, and the second light shield layer 102b then has a part and is overlapped in the data wire 114a region crossing with a gate line 110.In the present embodiment, the first light shield layer 102a and one second light shield layer 102b is used for covering the light from backlight module in display floater (not illustrating), and can be made up of metal material or other lighttight nonmetallic materials.
In the present embodiment, pixel cell 10 also comprises a resilient coating 104 (not being illustrated in Fig. 1) and is arranged on substrate 10, and covers the first light shield layer 102a and the second light shield layer 102b.In the present embodiment, resilient coating 104 can be an individual layer or has a sandwich construction, and comprises silica, silicon nitride, silicon oxynitride or its combination.
Semiconductor layer 106 is arranged on resilient coating 104, in order to the active layers as thin-film transistor (that is, the switch element of pixel cell 10).Moreover it is overlapping with the first light shield layer 102a that semiconductor layer 106 has a part, and it is overlapping with the second light shield layer 102b to have another part.In one embodiment, semiconductor layer 106 can comprise a low temperature polycrystalline silicon (Low temperature poly-silicon, LTPS).
Insulating barrier 108 to be arranged on resilient coating 104 and to cover semiconductor layer 106, in order to the gate dielectric as thin-film transistor.In the present embodiment, insulating barrier 108 can be an individual layer or has a sandwich construction, and comprises silica, silicon nitride, silicon oxynitride, hafnium oxy-nitride (HfON) or its combination.
Gate line 110 is arranged on insulating barrier 108, in order to the gate electrode as thin-film transistor.Moreover it is overlapping with semiconductor layer 106 and the first light shield layer 102a that gate line 110 has a part, and it is overlapping with semiconductor layer 106 and the second light shield layer 102b to have another part.In one embodiment, gate line 110 can by metal material such as molybdenum, aluminium, copper, titanium or its combination, or the material of other suitable electrodes formed.
In the present embodiment, pixel cell 10 also comprises an interlayer dielectric (interlayer dielectric, ILD) layer 112 (not being illustrated in Fig. 1) and is arranged on insulating barrier 108, and covering gate polar curve 110.In the present embodiment, contact hole 113 runs through interlayer dielectric layer 112 and insulating barrier 108, to expose semiconductor layer 106.Moreover in the present embodiment, interlayer dielectric layer 112 can be an individual layer or has a sandwich construction, and comprise silica, silicon nitride, silicon oxynitride or its combination.
Each data wire 114a to be arranged on interlayer dielectric layer 112 and to be positioned at above gate line 110, makes each data wire 114a have a region crossing with each gate line 110.Moreover the second light shield layer 102b has the region that a part is overlapped in wherein a data wire 114a and a gate line 110, as shown in Figure 1.
Metal level 114b is arranged at above interlayer dielectric layer 112 and insulating barrier 108, and compliance extends sidewall and the bottom of contact hole 113, and metal level 114b is electrically connected with the semiconductor layer 106 being exposed to contact hole 113 by contact hole 113.In one embodiment, metal level 114b and data wire 114a is made up of same material layer, such as molybdenum, aluminium, copper, titanium or its combination.
In the present embodiment, as shown in Figures 1 and 2, the first light shield layer 102a includes an overlapping region of overlying metal layer 114b.This overlapping region can help the first light shield layer 102a to stop to irradiate on semiconductor layer 106 from the scattered beam of backlight module (not illustrating), and then improves or reduce the leakage current because scattered beam is formed in semiconductor layer 106.But if this overlapping region is too little, then metal level 114b cannot effectively help the first light shield layer 102a to stop to irradiate on semiconductor layer 106 from the scattered beam of backlight module; If this overlapping region is too large, then can form excessive stray capacitance (parasitic capacitor).
Therefore, in the present embodiment, as shown in Figure 1, metal level 114b has an edge 114 ', and it is adjacent to an edge 110 ' of gate line 110.Moreover, in a first direction D1, (it is perpendicular to a bearing of trend of gate line 110 in this overlapping region, and this bearing of trend is parallel to a second direction D2) on there is one first width A, and bottom the edge 114 ' of metal level 114b and contact hole 113 between beeline on first direction D1 be one second width B, wherein the ratio of the first width A and the second width B is between 0.2 to 0.8.
In the present embodiment, pixel cell 10 also comprises planarization layer 116 and a contact hole 117 (not being illustrated in Fig. 1).Planarization layer 116 is arranged on interlayer dielectric layer 112, and cover data line 114a and metal level 114b, and insert in contact hole 113.Moreover contact hole 117 runs through planarization layer 116, to expose metal level 114b.In one embodiment, planarization layer 116 can comprise an insulating material, such as perfluoroalkoxy resin (perfluoroalkoxy (PFA) polymer resin).
In the present embodiment, pixel cell 10 also comprises lower floor's transparency electrode 118, top transparent electrode 124 and the passivation protection layer 120 (not being illustrated in Fig. 1) between two transparency electrodes 118 and 124.In the present embodiment, lower floor's transparency electrode 118 is arranged on planarization layer 116, in order to the common electrode as pixel cell 10.Moreover passivation protection layer 120 is arranged on planarization layer 116, and cover the sidewall of lower floor's transparency electrode 118 and contact hole 117, and in contact hole 117, form the contact hole 121 exposing metal level 114b.Top transparent electrode 124 is arranged on passivation protection layer 120, and is electrically connected with the metal level 114b exposed bottom contact hole 121 by contact hole 121, and by passivation protection layer 120 and lower floor's transparency electrode 118 electrical isolation.Top transparent electrode 124 is as the pixel electrode of pixel cell 10.In the present embodiment, lower floor's transparency electrode 118 and top transparent electrode 124 can by transparent conductive material (such as, indium tin oxide (indium tin oxide, ITO) or indium-zinc oxide (indium zinc oxide, IZO) layer) formed.Moreover passivation protection layer 120 can be made up of silicon nitride.
In other are implemented, lower floor's transparency electrode 118 is arranged on planarization layer 116, and is electrically connected with the metal level 114b exposed bottom contact hole 117, in order to the pixel electrode as pixel cell 10 by contact hole 117.Moreover passivation protection layer 120 covers lower floor's transparency electrode 118.Top transparent electrode 124 is arranged on passivation protection layer 120, in order to as pixel cell 10 common electrode and by passivation protection layer 120 and lower floor's transparency electrode 118 electrical isolation.
Please refer to Fig. 3 A, its show according to the utility model one embodiment for looking schematic diagram at the bottom of the pixel cell of display floater, the parts being wherein same as Fig. 1 use identical label and the description thereof will be omitted.In the present embodiment, the structural similarity of pixel cell 10 ' is in pixel cell 10 structure shown in Fig. 1.Difference is only pixel cell 10 " the first light shield layer 102a have two relatively and the edge of indent, to reduce the area of the first light shield layer 102a.For example, first light shield layer 102a has an overlapping region overlapping with gate line 110, the one first middle section 111a that overlapping region has two overlapping line segment 111as ' (be represented by dotted lines) overlapping with the opposite edges 110 ' of gate line 110 and is positioned between two double line section 111a ', one of them of the two double line section 111a ' of the first light shield layer 102a has one first length L1 on a second direction D2, and the first middle section 111a has one second length L2 on second direction D2, wherein the first length L1 is greater than the second length L2.Thus, the stray capacitance between the first light shield layer 102a and gate line 110 can effectively be reduced.In other embodiments, the second light shield layer 102b (not illustrating) also can have same or similar in the external form profile of the first light shield layer 102a.
Please refer to Fig. 3 B, its show according to the utility model one embodiment for looking schematic diagram at the bottom of the pixel cell of display floater, the parts being wherein same as Fig. 1 use identical label and the description thereof will be omitted.In the present embodiment, pixel cell 10 " structural similarity in pixel cell 10 structure shown in Fig. 1.Difference is only pixel cell 10 " the first light shield layer 102a have two relatively and the edge of indent, to reduce the area of the first light shield layer 102a.For example, first light shield layer 102a has an overlapping region overlapping with semiconductor layer 106, the one second middle section 111b that overlapping region has two overlapping line segment 111bs ' (be represented by dotted lines) overlapping with semiconductor layer 106 opposite edges 106 ' and is positioned between two double line section 111b ', one of them of the two double line section 111b ' of the first light shield layer 102a has one the 3rd length L3 on first direction D1, and the first middle section 111b has one the 4th length L4 on first direction D1, wherein the 3rd length L3 is greater than the 4th length L4.Thus, the stray capacitance between the first light shield layer 102a and semiconductor layer 106 can effectively be reduced.In other embodiments, the second light shield layer 102b (not illustrating) also can have same or similar in the external form profile of the first light shield layer 102a.
Be understandable that, in the pixel cell 10 of Fig. 1, first light shield layer 102a and/or the second light shield layer 102b can have overlapping line segment 111a ' and the first middle section 111a (Fig. 3 A shown in) and have overlapping line segment 111b ' and the second middle section 111b (shown in Fig. 3 B), and wherein the first length L1 is greater than the second length L2 and the 3rd length L3 is greater than the 4th length L4.
Please refer to Fig. 4, its show according to the utility model one embodiment for looking schematic diagram at the bottom of the pixel cell of display floater, the parts being wherein same as Fig. 1 use same or analogous label and the description thereof will be omitted.In the present embodiment, the structural similarity of pixel cell 20 is in pixel cell 10 structure shown in Fig. 1, and it comprises: substrate 100, a 1 first light shield layer 202a and one second light shield layer 202b, semi-conductor layer 106, insulating barrier 108, contact hole 113, pair of grid lines 210, a pair of data lines 114a and metal level 114b.Substrate (not illustrating) has the pixel region P defined by pair of grid lines 210 and pair of data lines 114a.Herein, in order to simplify accompanying drawing, in Fig. 4, only show a data wire 114a and a gate line 210.
In the present embodiment, be different from the gate line 110 of Fig. 1, gate line 210 has a protuberance 220 (also referred to as gate electrode) overlapping with semiconductor layer 206.Protuberance 220 extends along first direction D1 (that is, perpendicular to a bearing of trend of gate line 210).
Moreover as shown in Figure 4, the first light shield layer 202a has a part and is overlapped in protuberance 220, and includes an overlapping region of overlying metal layer 114c.Similarly, this overlapping region can help the first light shield layer 202a to stop to irradiate on semiconductor layer 206 from the scattered beam of backlight module (not illustrating), and then improves or reduce the leakage current because scattered beam is formed in semiconductor layer 206.In the present embodiment, metal level 114c has an edge 214 ', and it is adjacent to an edge 220 ' of protuberance 220.Moreover, this overlapping region in second direction D2 (namely, be parallel to the bearing of trend of gate line 210) on there is one first width C, and bottom the edge 214 ' of metal level 114c and contact hole 113 between beeline on second direction D2 be one second width D, wherein the ratio of the first width C and the second width D is between 0.2 to 0.8.
In the present embodiment, the second light shield layer 202b has the region that a part is overlapped in data wire 114a and gate line 210.Be different from first and second light shield layer 102a and 102b of Fig. 1, first light shield layer 202a has one first curved edge 203 overlapping with semiconductor layer 206, and the second light shield layer 202b has one second curved edge 204 overlapping with semiconductor layer 206, and adjacent second curved edge 204 of the first curved edge 203.Because first and second light shield layer 202a and 202b has the first curved edge 203 and the second curved edge 204, therefore can shorten the distance between first and second light shield layer 202a and 202b, and then increase the aperture opening ratio of pixel cell 20.
Be understandable that, the structure of pixel cell 20 also comprises resilient coating 104, insulating barrier 108, interlayer dielectric layer 112, planarization layer 116, contact hole 117 and 121, lower floor's transparency electrode 118, passivation protection layer 120 and the top transparent electrode 124 shown in the pixel cell 10 similar in appearance to Fig. 2.At this, for the purpose of simplifying the description, no longer repeated.
According to above-described embodiment, due to in the pixel cell of display floater, metal level and the first light shield layer have suitable overlapping region, therefore can not formed under excessive stray capacitance, effective stop is irradiated on semiconductor layer from the scattered beam of backlight module, and then improves or reduce leakage current.Moreover, because the first light shield layer and/or the second light shield layer have at least two relatively and the edge contour of indent, light shield layer and gate line and/or the stray capacitance between light shield layer and semiconductor layer therefore can be reduced further.In addition, in the situation of gate line with protuberance, first and second light shield layer has toward each other and adjacent curved edge, therefore can shorten the distance between first and second light shield layer, and then increases the aperture opening ratio of pixel cell.
Claims (10)
1. a display floater, is characterized in that, this display floater bag is containing ︰
Substrate;
First light shield layer, is positioned on this substrate;
Semiconductor layer, is positioned on this first light shield layer;
Insulating barrier, is positioned on this semiconductor layer;
Gate line, is positioned on this insulating barrier;
Contact hole, runs through this insulating barrier, to expose this semiconductor layer; And
Metal level, is positioned on this insulating barrier, and is electrically connected with this semiconductor layer by this contact hole;
Wherein this first light shield layer includes an overlapping region of this metal level overlapping, this overlapping region has one first width on a first direction, and this metal level bottom an edge and this contact hole of this gate line contiguous between beeline on this first direction be one second width, and wherein this first direction is perpendicular to a bearing of trend of this gate line, and the ratio of this first width and this second width is between 0.2 to 0.8.
2. display floater as claimed in claim 1, it is characterized in that, this first light shield layer has an overlapping region overlapping with this gate line, this overlapping region has two overlapping line segments overlapping with these gate line opposite edges and one first middle section between these two overlapping line segments, these two overlapping line segments of this first light shield layer one of them there is one first length in a second direction, and this first middle section has one second length in this second direction, and wherein this second direction is parallel to this bearing of trend of this gate line, and this first length is greater than this second length.
3. display floater as claimed in claim 1, it is characterized in that, this first light shield layer has an overlapping region overlapping with this semiconductor layer, this overlapping region has two overlapping line segments overlapping with these semiconductor layer opposite edges and one second middle section between these two overlapping line segments, these two overlapping line segments of this first light shield layer one of them there is one the 3rd length on this first direction, and this second middle section has one the 4th length on this first direction, and wherein the 3rd length is greater than the 4th length.
4. display floater as claimed in claim 1, it is characterized in that, this display floater also comprises:
Second light shield layer, between this substrate and this semiconductor layer, and has the region that a part is overlapped in this semiconductor layer and this gate line.
5. display floater as claimed in claim 1, it is characterized in that, this display floater also comprises resilient coating, between this first light shield layer and this semiconductor layer.
6. a display floater, is characterized in that, this display floater bag is containing ︰
Substrate;
First light shield layer, is positioned on this substrate;
Semiconductor layer, is positioned on this first light shield layer;
Insulating barrier, is positioned on this semiconductor layer;
Gate line, is positioned on this insulating barrier, and has the protuberance overlapping with this semiconductor layer, and this protuberance extends along a first direction, and this first direction is perpendicular to a bearing of trend of this gate line;
Contact hole, runs through this insulating barrier, to expose this semiconductor layer; And
Metal level, is positioned on this insulating barrier, and is electrically connected with this semiconductor layer by this contact hole;
Wherein this first light shield layer includes an overlapping region of this metal level overlapping, this overlapping region has one first width in a second direction, and this metal level bottom an edge and this contact hole of this protuberance contiguous between beeline in this second direction be one second width, and wherein this second direction is parallel to this bearing of trend of this gate line, and the ratio of this first width and this second width is between 0.2 to 0.8.
7. display floater as claimed in claim 6, it is characterized in that, this display floater also comprises the second light shield layer, between this substrate and this semiconductor layer, wherein this first light shield layer has one first curved edge overlapping with this semiconductor layer, and this second light shield layer has one second curved edge overlapping with this semiconductor layer, and this first curved edge this second curved edge adjacent.
8. display floater as claimed in claim 7, it is characterized in that, this first light shield layer has a part and is overlapped in this semiconductor layer region crossing with this gate line.
9. display floater as claimed in claim 8, it is characterized in that, this first light shield layer has a part and is overlapped in this protuberance, and this second light shield layer has a part is overlapped in this semiconductor layer another region crossing with this gate line.
10. display floater as claimed in claim 6, it is characterized in that, this display floater also comprises resilient coating, between this first light shield layer and this semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520225940.0U CN204596792U (en) | 2015-04-15 | 2015-04-15 | Display floater |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520225940.0U CN204596792U (en) | 2015-04-15 | 2015-04-15 | Display floater |
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| CN204596792U true CN204596792U (en) | 2015-08-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158879A (en) * | 2015-04-15 | 2016-11-23 | 群创光电股份有限公司 | Display floater |
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2015
- 2015-04-15 CN CN201520225940.0U patent/CN204596792U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158879A (en) * | 2015-04-15 | 2016-11-23 | 群创光电股份有限公司 | Display floater |
| CN106158879B (en) * | 2015-04-15 | 2019-10-01 | 群创光电股份有限公司 | Display panel |
| CN110571227A (en) * | 2015-04-15 | 2019-12-13 | 群创光电股份有限公司 | Display panel |
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