JP2006286773A - Thin film transistor device and its fabrication process, thin film transistor array and thin film transistor display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive thin film transistor device having good characteristics of a large ON current and a small OFF current while decreasing the number of times of photolithography, and to provide a thin film transistor array employing that thin film transistor device and a thin lightweight thin film transistor display in which the image is stabilized. <P>SOLUTION: In the thin film transistor device, a gate electrode and a capacitor lower electrode are provided, a source electrode and a drain electrode are arranged through a gate insulating film formed thereon in contact therewith, a semiconductor layer is arranged to fill the gap between the source electrode and the drain electrode, and a pixel electrode is arranged through an interlayer insulating film formed thereon. In the plan view arrangement, the source electrode is formed in isolated insular pattern, the drain electrode is formed between the source electrode and the gate electrode in C-shape substantially surrounding the source electrode, the drain electrode is formed in C-shape substantially surrounding the gate electrode, and the capacitor lower electrode is provided in the source electrode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thin film transistor device used for an image display device or the like.

Based on the transistor and integrated circuit technology based on the semiconductor itself, amorphous silicon (a-Si) and polysilicon (p-Si) thin film transistors (Tin) are manufactured on a glass substrate. Applied to electronic books. In these transistors, the semiconductor layer in the operation region is also formed by photoetching after a silicon film is formed by the CVD method or PVD method, so that the process is complicated and the manufacturing cost is inevitable.
An example of a conventional TFT display device is shown in FIGS. FIG. 14 is a plan view, and FIG. 15 is a cross-sectional view taken along line DD ′. The outline of the manufacturing method of this display device will be described. First, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1 by metal film formation, photolithography, and etching. Next, the SiNx insulating layer 3 and the semiconductor layer 6 made of amorphous silicon (a-Si) are formed by plasma CVD. A thin n ⁺ doping layer 6 ′ is formed on the top of the amorphous silicon (a-Si). Then, the semiconductor layer 6 made of a-Si is patterned into an island shape by photolithography. Subsequently, an ITO (Indium Thin Oxide) film is formed as the pixel electrode 8 and patterned into a predetermined shape by photolithography etching. Further, Si films for the source electrode 4 and the drain electrode 5 are formed, patterned by photolithography and etching, and the n ⁺ -Si layer in the channel portion is etched.
Thus, the current semiconductor manufacturing process makes full use of a vacuum process and a large number of photo processes, and the apparatus becomes large, so that the manufacturing cost is high.

In recent years, IC cards, electronic paper, RFID tags, and the like have attracted attention. For these, semiconductor devices are used. Semiconductor devices are becoming more and more multifunctional year by year, but conversely, they are becoming thinner and lighter, and in order to realize them, integration in a limited space and thinning of elements are required.
If the substrate used in the semiconductor device is thinned to reduce the thickness, the element is easily broken. For example, IC cards are stored and carried in card holders and wallets, etc., but they are often bent and twisted by external force in pockets and bags, and are strongly demanded to be flexible and resistant to breakage. It has been. In addition, since it is necessary to perform wiring by wire bonding or the like, there is a problem that the reliability is remarkably lowered, for example, the element itself or wiring is broken by bending or twisting.
Recently, TFTs using oxide semiconductors and organic semiconductors have appeared, and the formation temperature of the semiconductor layer can be lowered from room temperature to about 200 ° C. Therefore, it is possible to use a plastic substrate, and a lightweight and flexible display Is expected to be obtained at low cost (see, for example, Patent Document 1).

In the shape of a conventional semiconductor device, the upper limit of the channel width is the length of one pixel, and the on-current cannot be increased. In addition, since a leak current flows between the source and drain or between other pixels, the off-current cannot be reduced.
Alternatively, in order to increase the on-current, it is necessary to reduce the channel length, the off-current increases, the semiconductor characteristics vary due to the variation in channel length, and the risk of a short circuit between the source and drain increases.
Thus, in the conventional semiconductor device, the on-current cannot be increased and the off-current cannot be decreased, and it has been difficult to obtain good characteristics.

In addition, in the conventional semiconductor device, there is a problem that electric charges leak even when the TFT is in an off state. In addition, charge may leak inside the capacitance, but leakage from the TFT is generally about one digit larger. When this leak is severe, a phenomenon called flicker occurs in which the brightness of an image changes at the same cycle as the frame frequency.
By the way, it is said that the leak current is generated at an edge portion formed by intersecting the semiconductor layer of the TFT and the gate electrode. As a cause of this, the gate electrode causes a short circuit between the source electrode and the drain electrode due to poor insulation of the gate electrode at this edge portion. Alternatively, the periphery of the semiconductor layer may not have a crystal structure due to damage caused by etching or ion doping.

For example, consider a case where the gate insulating film does not completely cover the semiconductor layer. When an insulating film is formed on the surface of the semiconductor layer in order to insulate the gate electrode from the semiconductor layer, the insulating film is hardly formed on the side surface due to a step, and the side surface may be exposed. In this state, the gate electrode and the semiconductor layer are short-circuited on the side surface. For this reason, when a voltage lower than the threshold is applied to the gate electrode, the drain electrode and the source electrode are always short-circuited by the gate electrode even when the channel is not formed, and a leak current is generated. .
In general, in a conventional TFT, a thin film is difficult to be formed on the side surface of the stepped portion of the semiconductor layer in the manufacturing process, so that a phenomenon in which the side surface of the semiconductor layer is not completely covered with the insulating film easily occurs. For this reason, a leak current flows through the edge portion. In other words, the leakage current can be reduced if there is no structural portion such as an edge portion.

In order to obtain a TFT with a small leakage current, a liquid crystal display including a TFT in which a source electrode and a gate electrode are arranged in a circular shape has been proposed (for example, see Patent Document 2). As shown in FIG. 16, in the thin film transistor of this liquid crystal display, a gate electrode 502 is disposed so as to surround the source electrode 501, and a drain electrode 503 is disposed outside the gate electrode 502 so as to substantially surround the gate electrode 502. Have a structure. In the figure, reference numeral 504 denotes a semiconductor layer. In other words, electrodes having a substantially similar outer shape of the TFT are arranged concentrically on the semiconductor layer. A gate electrode and an electrode having a shape lacking a part of the ring are arranged so as to surround the outside of the circular electrode. The electrode having a shape lacking a part of the ring is arranged in a layer different from the wiring metal constituting the gate electrode, and the two electrodes are composed of the same wiring metal. As a result, since the edge portion of the semiconductor layer does not exist on the line connecting the source electrode and the drain electrode, the drain electrode and the source electrode are not short-circuited by the gate electrode. It is said that can be reduced.
Republished patent WO 98-29261 Japanese Patent Laid-Open No. 08-160469

The present invention has been made in view of the state of the related art, and an object of the present invention is to provide a thin film transistor device having a large on-state current and a small off-state current and having good characteristics with little variation.
Another object of the present invention is to provide a thin film transistor device as described above at a low cost by reducing the number of times of photolithography.
It is another object of the present invention to provide a thin film transistor array using the thin film transistor device as described above, thereby providing a light and thin thin film transistor display having a stable image.

The present invention has a gate electrode and a capacitor lower electrode formed on an insulating substrate, and a source electrode and a drain electrode are arranged in contact with the gate insulating film through a gate insulating film formed thereon. And a semiconductor layer is disposed so as to fill a gap between the source electrode and the drain electrode, and a pixel electrode is disposed via an interlayer insulating film formed thereon, and in the interlayer insulating film, A thin film transistor device in which the pixel electrode and the source electrode are connected by a via hole, wherein the source electrode is an isolated island pattern in plan view, and the gate electrode is between the source electrode and the drain electrode. And the drain electrode has a C shape substantially surrounding the gate electrode, and the source electrode has a front C shape. And a thin film transistor device having a capacitor bottom electrode.
In this way, the source electrode 4 is formed in an isolated island pattern when the thin film transistor device is viewed in plan, the gate electrode 2 substantially surrounds it, and the drain electrode 5 substantially surrounds it, so that the gate potential is between the source and drain. Can be substantially cut off, and the off-current can be reduced. Further, by forming the capacitor under the source electrode 4, it is not necessary to provide a separate capacitor area in a portion other than the TFT portion, and the source electrode 4 can be enlarged. Accordingly, the channel width is increased, and the on-current can be increased. In particular, the source electrode 4 is formed in a square shape with rounded corners, and the gate electrode 2 and the drain electrode 5 are formed in a C shape by cutting out a part of the square shape with rounded corners. It can be made large and the channel length can be made uniform.
As a result, it is possible to provide a thin film transistor device with favorable characteristics having a large on-state current and a small off-state current.

In the thin film transistor device of the present invention, the source electrode may also serve as a capacitor upper electrode.
In the planar arrangement, the source electrode is a quadrangular shape with rounded corners, and the gate electrode and the drain electrode have a C-shape in which one side of a uniform quadrilateral is cut off. it can.
With such a structure, a channel width can be increased and a thin film transistor device having a large on-state current and a small off-state current can be obtained.

In the thin film transistor device of the present invention, the semiconductor layer is preferably made of an oxide semiconductor or an organic semiconductor.
If the thin film transistor device is configured in this manner, an inexpensive printing method can be used, and the etching process can be reduced.

The thin film transistor array of the present invention comprises a plurality of thin film transistor devices of the present invention arranged in a matrix on an insulating substrate, and the plurality of thin film transistor devices are electrically connected by gate wiring, source / drain wiring, and capacitor wiring. It is a thing. In the thin film transistor display of the present invention, the thin film transistor array and the counter substrate are bonded to each other by a sealing material having a substantially rectangular frame shape in plan view, and a liquid crystal layer is sealed in a region surrounded by the sealing material. is there. Alternatively, it is bonded to a counter substrate including an electrophoresis capsule.
Since the thin film transistor display of the present invention uses the thin film transistor device of the present invention, there is an advantage that an image is stable, and a thin and lightweight display is provided at low cost.

According to the method of manufacturing the thin film transistor device of the present invention, a gate electrode made of a conductive film and a capacitor lower electrode are formed on an insulating substrate, a gate insulating film is formed thereon, and then a source made of the conductive film is formed on the gate insulating film. An electrode and a drain electrode are formed, a semiconductor layer is formed on a part of the gate insulating film so as to be in contact with the source electrode and the drain electrode, and the source electrode, the drain electrode, and the gate insulating film including the semiconductor layer are formed. Forming a via hole at a predetermined position of the interlayer insulating film, forming a conductor layer in the via hole, and further forming a pixel electrode on the interlayer insulating film including the via hole. The production method having at least was adopted. The formation order of the semiconductor layer and the source / drain electrodes may be reversed.
In the thin film transistor device manufacturing method of the present invention, at least a printing step is included in the step of forming the semiconductor layer, the step of forming the source electrode, the drain electrode and the capacitor lower electrode, or the step of forming a conductor layer in the via hole. Can be included.
According to such a manufacturing method, a thin film transistor device including an effective capacitor with little leakage current can be reliably manufactured.
In particular, if a printing method is employed, conductors can be formed only in necessary portions, so that the manufacturing process is greatly reduced, and a large amount can be manufactured at low cost.

As can be understood from the above description, the present invention has the following effects.
By turning the source electrode into an isolated island pattern and surrounding it with the gate electrode, off current can be reduced. Further, by providing the capacitor under the source electrode, the channel width can be increased and the on-current can be increased. Since the source electrode has a square shape with rounded corners and the drain electrode has a uniform width at a part of the side of the rounded square shape, the channel length can be kept small and uniform. For these reasons, it is possible to obtain a thin film transistor device with good characteristics having a large on-state current and a small off-state current.
In addition, the above thin film transistor device can be provided at a low cost by reducing the number of times of photolithography.
Furthermore, a thin film transistor array using the thin film transistor device as described above can be obtained, so that a light and thin thin film transistor display with stable images can be obtained.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings used below, the scale is not accurately drawn for easy understanding.
(First embodiment)
A thin film transistor device according to a first embodiment of the present invention is shown in FIGS. FIG. 1 is a plan view showing one pixel region of a thin film transistor array, and FIG. 2 is a cross-sectional view taken along line AA ′.
As shown in FIG. 1, in the thin film transistor device 50 according to the first embodiment, the source electrode 4 has an isolated island pattern and the gate electrode 2 has a C shape substantially surrounding the source electrode 4 as viewed in a plan view. The drain electrode 5 is formed in a C shape substantially surrounding the gate electrode 2. The source electrode 4 has a capacitor lower electrode 10, the source electrode 4 has a square shape with rounded corners, and the gate electrode 2 and the drain electrode 5 have a square C shape with a uniform width. .
A semiconductor layer 6 is formed between the source electrode 4 and the drain electrode 5 at a position substantially overlapping with the gate electrode 2 to form a transistor.

As shown in FIG. 2, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1, and the top is covered with the gate insulating film 3. A source electrode 4 and a drain electrode 5 are formed thereon. Here, the source electrode 4 also serves as a capacitor upper electrode. A semiconductor layer 6 is formed in a channel portion between the source electrode 4 and the drain electrode 5 to form a transistor.
Further, a pixel electrode 8 is arranged through an interlayer insulating film 7 formed thereon, and the pixel electrode 8 and the source electrode 4 are connected by a via hole 9 in the interlayer insulating film 7.

In this way, the source electrode 4 is formed in an isolated island pattern in plan view, the gate electrode 2 substantially surrounds it, and the drain electrode 5 substantially surrounds it. Almost can be cut off, and the off-current can be reduced. Further, by forming the capacitor lower electrode 10 below the source electrode 4, it is not necessary to provide a separate capacitor area in a portion other than the TFT portion, and the source electrode 4 can be enlarged. Accordingly, the channel width between the source electrode 4 and the drain electrode 5 is increased, and the on-current can be increased. In particular, the source electrode 4 is formed in a square shape with rounded corners, and the gate electrode 2 and the drain electrode 5 are formed in a C shape using a part of the side of the square shape with rounded corners. It can be made large and the channel length can be made uniform.
Alternatively, by increasing the channel width, the channel length can be increased without reducing the on-current, the off-current can be reduced, and the variation in channel length can be reduced. Risk can be reduced.

  In the thin film transistor device of the present invention, as an insulating substrate, depending on the material of the semiconductor and conductor used, in addition to quartz and glass, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI) ), Polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon and the like can be used. These plastic substrates have the advantage that they can be used as an insulating substrate in the form of a thin film.

The gate electrode, the capacitor lower electrode, the source electrode, the drain electrode, the capacitor upper electrode, and the gate wiring, source wiring, and capacitor wiring that connect them have good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, etc. A metal film or a transparent conductive film such as ITO can be used. These conductive films are formed using a CVD method or a PVD method.
Alternatively, a conductive paste such as an Ag paste or Ni paste can be used. It is desirable to form by printing Ag paste or Ni paste and then firing.
By forming the source electrode, drain electrode, capacitor upper electrode, or the gate wiring, source wiring, and capacitor wiring connecting them using a printing method, film formation and patterning can be performed in a single process, thus simplifying the process. Capital investment can be greatly reduced.
Further, when screen printing is used as a printing method, the source electrode, the drain electrode or the capacitor upper electrode can be formed thick. Therefore, when forming a via hole, there is an advantage that the conditions for squeezing which reach the electrode and do not penetrate are wide. .

As the gate insulating layer and the interlayer insulating film, inorganic substances such as SiO ₂ , Al ₂ O ₃ , and SiN, and organic substances such as polyvinyl phenol, epoxy, and polyimide can be used. In general, the inorganic material film can be formed using a CVD method or a PVD method, and can be formed using an organic material spin coating method or a printing method. As a printing method, for example, a screen printing method can be used.

As a semiconductor constituting the semiconductor layer, in addition to commonly used silicon, an oxide semiconductor such as InGaZnO-based, InZnO-based, ZnGaO-based, InGaO-based, In ₂ O ₃ , ZnO, SnO ₂ , or a mixture thereof, Organic semiconductors such as polythiophene derivatives, polyphenylene vinylene derivatives, polythienylene vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, and oligothiophene derivatives can be used.

The oxide semiconductor layer can be obtained by metal organic chemical vapor deposition, film formation by sputtering or laser ablation, but can also be obtained by baking after applying and printing a raw material.
In the case of using an organic semiconductor film, it can be obtained by vapor deposition as well as by applying and baking raw materials.
When an oxide semiconductor or an organic semiconductor is used, a printing method can be used, and a temperature required for forming a semiconductor layer can be lowered to 200 ° C. or lower, so that a plastic film can be used as an insulating substrate.

It is preferable to use a UV-YAG laser beam for forming the via hole formed in the interlayer insulating film. If a UV-YAG laser beam is used, it can be suitably used for both inorganic and organic interlayer insulating films, and minute via holes can be formed accurately.
In addition to using the Al or Ag film formed in the via hole by sputtering, it can also be formed by printing an Ag paste or Ni paste and then pushing it in with a doctor blade.
As the pixel electrode, an Al or Ag thin film or an ITO film is preferably used.
Note that the interlayer insulating film, the pixel electrode, and the via hole can be omitted, and the source electrode can be used as the pixel electrode.

An image display such as a liquid crystal display or electronic paper can be manufactured using such a TFT. For example, an oxide semiconductor is used for the semiconductor layer 6, a transparent electrode such as ITO is used for the gate electrode 2, the source electrode 4, the drain electrode 5, and the capacitor lower electrode 10, and an inorganic material such as SiO ₂ is used for the gate insulating layer 3 and interlayer insulation is used. By using a transparent epoxy resin or polyimide resin for the film 7, a thin film transistor display having a large aperture ratio can be manufactured. Further, even when non-transparent, such as by using an Ag paste for the source electrode 4 or the drain electrode 5, it can be used for a guest-host liquid crystal display, electronic paper, or the like.

  Next, a method for manufacturing the thin film transistor device of the present embodiment will be described with reference to cross-sectional process diagrams of FIGS. For example, a polyethylene naphthalate (PEN) having a thickness of 125 μm is prepared as the substrate 1, C is formed using a part of a quadrilateral with rounded corners at predetermined positions by photolithography and etching after Al is sputtered on the entire surface. A gate electrode 2 and a capacitor lower electrode 10 having a letter shape are formed (see FIG. 3A). It is appropriate that the thickness of the Al film is about 100 nm, the outer diameter of the gate electrode 2 is about 460 μm, the inner diameter is 390 μm, and the size of the capacitor lower electrode is about 200 μm. At this time, the gate wiring 2 'and the capacitor wiring 10' are also formed at the same time.

Next, for example, a polyvinyl phenol solution is spin-coated and baked to form the gate insulating film 3 (see FIG. 3B). The thickness is about 1 μm.
Next, the source electrode 4 and the drain electrode 5 are formed by screen printing using an Ag conductive paste or the like (see FIG. 3C). The thickness is about 10 μm, and the source electrode 4 is a quadrangle with an outer shape of about 400 μm and rounded corners. The drain electrode 5 is a quadrangle with an outer shape of 500 μm and an inner shape of about 450 μm with rounded corners. At this time, the drain wiring 5 'is also formed at the same time.
Then, for example, a polythiophene solution is applied to the gap between the source electrode 4 and the drain electrode 5 by a dispenser and baked to form the semiconductor layer 6 (see FIG. 3D).

Further, an interlayer insulating film 7 is formed by applying and baking an epoxy resin (see FIG. 4E). The thickness is about 100 μm.
Next, a via hole 9 having a diameter of 50 μm is formed in the interlayer insulating film 7 by the UV-YAG laser (see FIG. 4F), and the Ag paste is buried by a doctor blade, followed by firing (see FIG. 4G). . Here, it is preferable to make the surface lightly flattened.
Finally, for example, Al or ITO is vapor-deposited as the pixel electrode 8 and patterned into a square of about 490 μm square by photolithography / etching (see FIG. 4H).
In this way, the thin film transistor device of the first embodiment is obtained.

Here, as a process of forming the gate electrode 2, the source electrode 4, and the drain electrode 5, it is not necessary to use photolithography for patterning by using screen printing. However, depending on the pattern shape, the distance (channel length) d between the source electrode 4 and the drain electrode 5 may not be kept constant.
For example, in the case of forming a quadrangle as shown in FIG. 5A, rounding of corners and thickening of lines occur in the printing process, resulting in the shape as shown in FIG. 5B, and the channel length d changes to d ′. Variations in characteristics occur. Therefore, as a result of intensive studies to form the distance (channel length) d between the source electrode 4 and the drain electrode 5 with high accuracy, the gate electrode 2, the source electrode 4 and the drain electrode 5 are obtained as shown in FIG. In the case of a C-shape obtained by cutting out a part of a quadrangular side having an arc with a rounded radius R, and when the centers are made to coincide, the channel length d as shown in FIG. It was found that the channel length can be kept uniform because it can be finished in a certain shape.

Using such a thin film transistor device, an image display element such as a liquid crystal display or electronic paper can be manufactured. For example, an oxide semiconductor is used for the semiconductor layer 6, a transparent electrode such as ITO is used for the gate electrode 2, the source electrode 4, the drain electrode 5, the capacitor lower electrode 10, and the capacitor upper electrode 11, and SiO ₂ is used for the gate insulating layer 3. By using a transparent epoxy resin or polyimide resin for the film 7, a liquid crystal display with a large aperture ratio can be manufactured. Further, by using an Ag paste for the source electrode 4 and the drain electrode 5, even in the case of a non-transmissive liquid crystal display, it can be used for a guest-host liquid crystal display, electronic paper, or the like.

(Second Embodiment)
A thin film transistor device according to a second embodiment of the present invention is shown in FIGS. FIG. 7 is a plan layout view showing one pixel region of the thin film transistor array, and FIG. 8 is a sectional view taken along line BB ′.
The thin film transistor device 60 of the present embodiment is different from the thin film transistor device 50 shown in the first embodiment in the cross-sectional structure. The planar arrangement is the same as that of the thin film transistor device shown in the first embodiment.
As shown in FIG. 8, in the thin film transistor device 60 of this embodiment, the gate electrode 2 and the capacitor lower electrode 10 are formed on the same surface on the insulating substrate 1, and the top is covered with the gate insulating film 3. A semiconductor layer 6 covers the entire surface of the gate insulating film 3. Further, the source electrode 4 and the drain electrode 5 are formed on the semiconductor layer 6 in contact with the semiconductor layer 6, and the upper portion thereof is covered with the interlayer insulating layer 7, and the pixel electrode 8 is formed thereon. The pixel electrode 8 is connected to the source electrode 4 by a via hole 9.
That is, it differs from the thin film transistor device of the first embodiment in that the semiconductor layer 6 is on the substrate side of the source electrode 4 and the drain electrode 5 or on the opposite side of the substrate.
Since the material used and the shape of each pattern are the same as those in the first embodiment, description thereof is omitted.

Next, a method for manufacturing the thin film transistor device of this embodiment will be described with reference to cross-sectional process diagrams of FIGS. The difference from the method of manufacturing the thin film transistor device according to the first embodiment is the order in which the semiconductor layers 6 are formed. Also, some other methods are adopted for forming each layer.
That is, a 125 μm-thick polyethylene naphthalate (PEN) is prepared as the insulating substrate 1, and after sputtering Al film, a part of the rectangular side with rounded corners is cut out and used by photolithography and etching. Gate electrode 2 and circular capacitor lower electrode 10 are fabricated (see FIG. 9A). It is appropriate that the thickness is about 100 nm, the outer shape of the gate electrode 2 is 460 μm, the inner shape is about 340 μm, and the diameter of the capacitor lower electrode 10 is about 200 μm. At this time, the gate wiring 2 ′ and the capacitor wiring 10 ′ are also prepared at the same time.

Next, SiO ₂ to be the gate insulating film 3 is formed by sputtering, and InGaZnO ₄ to be the semiconductor layer 6 is formed thereon (see FIG. 9B). Appropriate thicknesses of about 500 nm and 200 nm are appropriate.

  Next, the source electrode 4 and the drain electrode 5 are formed by screen printing (see FIG. 9C). The thickness is about 10 μm, the source electrode 4 is a quadrangle with an outer shape of about 350 μm (the corner is an arc shape with a radius of about 50 μm), and the drain electrode 5 is a part of a square with an outer shape of 500 μm and an inner shape of about 450 μm. C-shaped (the inner peripheral corner is an arc having a diameter of about 100 μm). At this time, the drain wiring 5 'is also formed at the same time.

Further, an interlayer insulating film 7 is formed by applying and baking an epoxy resin or the like (see FIG. 9D). The thickness is about 100 μm.
Next, a via hole 9 having a diameter of 50 μm is formed in the interlayer insulating film 7 by a UV-YAG laser (see FIG. 10E), and the Ag paste is embedded by a doctor blade, followed by firing (see FIG. 10F). . Here, it is preferable to make the surface lightly flattened.
Finally, for example, Al or ITO is vapor-deposited as the pixel electrode 8 and patterned into a square of about 490 μm square by photolithography / etching (see FIG. 10G).
In this way, the thin film transistor device 60 of the second embodiment is obtained.

  FIG. 11 is a diagram showing a planar configuration of the thin film transistor array 80 of the present invention. A thin film transistor array 80 according to the present invention includes a plurality of thin film transistor devices 50 according to the present invention arranged in a matrix on an insulating substrate, and the plurality of thin film transistor devices 50 are connected to a gate wiring 2 ′, a drain wiring 5 ′, and a capacitor wiring. 10 'electrically connected.

  FIG. 12 is a cross-sectional configuration diagram showing an electrophoretic display 91 which is another example of the thin film transistor display of the present invention. In the electrophoretic display 91 of the present invention, a thin film transistor array 80 equipped with the thin film transistor device 50 of the first embodiment and a counter substrate 82 including the transparent capsule 13 and the counter electrode 14 including the electrophoretic capsule 16 are attached. It is a combination.

FIG. 13 is a sectional view showing a guest-host liquid crystal display 90 which is a kind of thin film transistor display of the present invention. In the guest-host liquid crystal display 90 of the present invention, a thin-film transistor array 80 including the thin-film transistor device 60 according to the second embodiment and a counter substrate 81 including the transparent substrate 13 and the counter electrode 14 are substantially rectangular in plan view. And a guest-host liquid crystal layer 15 is sealed in a region surrounded by the sealing material (not shown).
Since the guest-host liquid crystal display 90 of the present invention uses the thin film transistor device of the present invention, there is an advantage that an image is stable and a thin and light-weight one is provided at low cost.

Example 1
A thin film transistor array including the thin film transistor device according to the first embodiment having the structure shown in FIGS. 1 and 2 was prepared according to the process charts shown in FIGS.
C-shaped gate electrode 2 in which polyethylene naphthalate (PEN) having a thickness of 125 μm is prepared as insulating substrate 1, Al is sputter-deposited, and a part of a rectangular side with rounded corners is cut off by photolithography and etching; A circular capacitor lower electrode 10 was produced (see FIG. 3A). The thickness was 100 nm, the outer diameter of the gate was 460 μm, the inner diameter was 390 μm, and the diameter of the capacitor lower electrode was 200 μm. A gate wiring 2 ′ and a capacitor wiring 10 ′ were also produced at the same time. A large number of these gate electrodes 2 and circular capacitor lower electrodes 10 are formed in a matrix on the insulating substrate 1, and the gate wiring 2 ′ and the capacitor wiring 10 ′ are formed so as to connect them.

Next, a polyvinyl phenol solution was spin-coated and baked to form the gate insulating film 3 (see FIG. 3B). The thickness was 1 μm.
Next, the source electrode 4 and the drain electrode 5 were formed by screen printing (see FIG. 3C). The thickness was 10 μm, the source electrode 4 was a quadrangle with an outer shape of 400 μm (the corner is a circular arc with a radius of 50 μm), and the drain electrode 5 was a part of a square side with an outer shape of 500 μm and an inner shape of 450 μm (the inner diameter was an arc with a radius of 75 μm). The channel length is 25 μm and the channel width is 1590 μm. The drain wiring 5 ′ was also formed at the same time.

And the polythiophene solution was apply | coated with the dispenser in the gap | interval of the source electrode 4 and the drain electrode 5, and it was set as the semiconductor layer 6 by baking (refer FIG.3 (d)).
Furthermore, the interlayer insulation film 7 was formed by apply | coating and baking an epoxy resin (refer FIG.4 (e)). The thickness was about 100 μm.
Next, a via hole 9 having a diameter of 50 μm is formed in the interlayer insulating film 7 by a UV-YAG laser (see FIG. 4F), and the Ag paste is embedded by a doctor blade, followed by firing (see FIG. 4G). . Here, the surface was lightly shaved and flattened.
Finally, ITO was vapor-deposited as the pixel electrode 8 and patterned into a square of about 490 μm square by photolithography and etching (see FIG. 4H).
In this way, a thin film transistor array having a planar structure shown in FIG. In this thin film transistor array, the channel length is the same as that of the comparative example described later and the channel width can be made ten times that of the conventional one, so that the on-current is 10 times as large as 1 μA (the variation is 0.5 to 2 μA). Further, since the gate electrode 2 almost covers the source electrode 4, the off-current can be suppressed to 50 pA or less.

  An electrophoretic display having the structure shown in FIG. 12 was produced using the produced thin film transistor array 80 and confirmed to operate.

(Example 2)
A thin film transistor array including the thin film transistor device according to the second embodiment having the structure shown in FIGS. 7 and 8 was produced according to the process charts shown in FIGS. 9A to 10G.
A 125-μm thick polyethylene naphthalate (PEN) is prepared as an insulating substrate 1, and after sputtering Al, a C-shaped gate electrode 2 in which a part of a square with rounded corners is cut off by photolithography and etching. A circular capacitor lower electrode 10 was produced (see FIG. 9A). The thickness was 100 nm, the gate electrode 2 had an outer shape of 460 μm, an inner shape of 340 μm, and the capacitor lower electrode 10 had a diameter of 200 μm. A gate wiring 2 ′ and a capacitor wiring 10 ′ were also produced at the same time. A large number of these gate electrodes 2 and circular capacitor lower electrodes 10 are formed in a matrix on the insulating substrate 1, and the gate wiring 2 ′ and the capacitor wiring 10 ′ are formed so as to connect them.

Next, SiO ₂ to be the gate insulating film 3 and InGaZnO ₄ to be the semiconductor layer 6 were formed by sputtering (see FIG. 9B). The thicknesses were 500 nm and 200 nm, respectively.

  Next, the source electrode 4 and the drain electrode 5 were formed by screen printing using an Ag conductive paste (see FIG. 9C). The thickness was 10 μm, the source electrode 4 was a square having an outer shape of 350 μm (the corner was an arc having a radius of 50 μm), and the drain electrode 5 was a part of a square side having an outer shape of 500 μm and an inner shape of 450 μm (the corner was an arc having a radius of 100 μm). The drain wiring 5 'was also formed at the same time. The channel length was 50 μm and the channel width was 1470 μm.

Compared to Comparative Example 2 described later, the channel length was doubled and the channel width was 10 times that of the conventional one.
The on-current was 5 times 15 μA (variation was 10 to 20 μA). Further, the off-current can be suppressed to 2.5 nA or less because the gate electrode 2 substantially covers the source electrode 4 and the channel length can be doubled.

  Subsequently, an interlayer insulating film 7, a via hole 9, and a pixel electrode 8 are formed by the same process as in the first embodiment (see FIGS. 9D to 10G), and the thin film transistor device shown in FIGS. A thin film transistor array 80 having a planar structure shown in FIG. Using the produced thin film transistor array, using a counter substrate using a PET film as a transparent substrate and ITO as a counter electrode, a guest-host liquid crystal display having the structure shown in FIG. 13 was obtained, and as a result, a stable and clear image was displayed. I was able to confirm.

(Comparative Example 1)
As the insulating substrate 1, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and after sputtering Al, a rectangular gate electrode 2 and a circular capacitor lower electrode 10 were formed by photolithography and etching. The thickness was 100 nm, the gate width was 50 μm, the length was 250 μm, and the size of the capacitor lower electrode 10 was 200 μm × 150 μm. A gate wiring 2 ′ and a capacitor wiring 10 ′ were also produced at the same time. A large number of these gate electrodes 2 and capacitor lower electrodes 10 are formed in a matrix on the insulating substrate 1, and the gate wiring 2 ′ and the capacitor wiring 10 ′ are formed so as to connect them.

Next, a polyvinyl phenol solution was spin-coated and baked to form the gate insulating film 3. The thickness was 1 μm.
Next, the source electrode 4 and the drain electrode 5 were formed by screen printing. The thickness was 10 μm, the channel length between the source electrode 4 and the drain electrode 5 was 25 μm, and the channel width was 150 μm. The drain wiring 5 ′ was also formed at the same time.
And the polythiophene solution was apply | coated with the dispenser in the gap | interval of the source electrode 4 and the drain electrode 5, and it was set as the semiconductor layer 6 by baking, and the thin-film transistor was formed.

  The on-current (drain voltage = drain voltage at −40V) of the thin film transistor obtained is 100 nA (variation is 50 nA to 200 nA), and the off-current (drain voltage = −40V, gate current = 0V). 100 pA.

(Comparative Example 2)
As the insulating substrate 1, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and after sputtering Al, a rectangular gate electrode 2 and a circular capacitor lower electrode 10 were formed by photolithography and etching. The thickness was 100 nm, the gate width was 50 μm, the length was 250 μm, and the overlapping area of the capacitor lower electrode 10 was 30000 μm ² . A gate wiring 2 ′ and a capacitor wiring 10 ′ were also produced at the same time. A large number of these gate electrodes 2 and capacitor lower electrodes 10 are formed in a matrix on the insulating substrate 1, and the gate wiring 2 ′ and the capacitor wiring 10 ′ are formed so as to connect them.

Next, SiO ₂ to be the gate insulating film 3 and InGaZnO ₄ to be the semiconductor layer 6 were formed by sputtering. The thicknesses were 500 nm and 200 nm, respectively. The semiconductor layer 6 was patterned by photolithography and wet etching.
Next, the source electrode 4 and the drain electrode 5 were formed by screen printing. The thickness was 10 μm, the channel length between the source electrode 4 and the drain electrode 5 was 25 μm, and the channel width was 150 μm. The drain wiring 5 ′ was also formed at the same time.

  The obtained thin film transistor has an on-current (drain voltage = drain current at a gate voltage = 5 V) of about 3 μA (variation is 1.5 μA to 6 μA), off-current (drain voltage = 5 V, drain current at a gate voltage = 0 V). Was about 10 nA.

It is a figure which shows the plane arrangement | positioning of the thin-film transistor apparatus concerning the 1st Embodiment of this invention. It is a figure which shows the cross-sectional structure along line A-A 'of FIG. FIG. 3 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 1. FIG. 4 is a sectional process diagram subsequent to FIG. 3; It is a figure explaining an example of the shape after screen printing. It is a figure explaining the other example of the shape after screen printing. It is a figure which shows the plane arrangement | positioning of the thin-film transistor apparatus concerning the 2nd Embodiment of this invention. FIG. 8 is a diagram showing a cross-sectional structure along line B-B ′ in FIG. 7. FIG. 8 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 7. FIG. 10 is a sectional process diagram subsequent to FIG. 9; It is a figure explaining the planar structure of the thin-film transistor array of this invention. It is a figure explaining the cross-section of an example of the thin-film transistor display of this invention. It is a figure explaining the cross-section of the other thin-film transistor display of this invention. It is a figure explaining an example of the plane arrangement of the conventional thin-film transistor. FIG. 15 is a cross-sectional view taken along line D-D ′ of FIG. 14. It is a figure explaining other plane arrangement of the conventional thin-film transistor.

Explanation of symbols

1 .... Insulating substrate, 2 .... Gate electrode, 2 '... Gate wiring, 3 .... Gate insulating film, 4 .... Source Electrode, 5... Drain electrode, 5 '... Drain wiring, 6 ... Semiconductor layer, 7 ... Interlayer insulating film, 8 ...・ Pixel electrode, 9 ・ ・ ・ ・ ・ ・ Via hole, 10 ・ ・ ・ ・ ・ ・ Capacitor lower electrode, 10 ′ ・ ・ ・ ・ ・ ・ Capacitor wiring, 13 ・ ・ ・ ・ ・ ・ Counter substrate, 14 ・ ・ ・ ・..Counter electrode, 15 ... Guest host liquid crystal, 16 ... Electrophoresis capsule, 50, 60, ... Thin film transistor device, 51 ... Thin film transistor, 52・ ・ ・ ・ ・ ・ Capacitor, 80 ・ ・ ・ ・ ・ ・ Thin film transistor array, 90 ・ ・ ・ ・ ・ ・ Guest host liquid crystal display , 91 ...... electrophoretic display

Claims (10)

  A gate electrode and a capacitor lower electrode formed on the insulating substrate, and a source electrode and a drain electrode are disposed in contact with the gate insulating film through the gate insulating film formed thereon, and the source A semiconductor layer is disposed so as to fill a gap between the electrode and the drain electrode, and further, a pixel electrode is disposed through an interlayer insulating film formed thereon, and the pixel electrode is formed by a via hole in the interlayer insulating film. A thin film transistor device in which an electrode and the source electrode are connected, wherein the source electrode is an isolated island pattern in plan view, the gate electrode is between the source electrode and the drain electrode, and the source electrode is The drain electrode has a C shape substantially surrounding the gate electrode, and the capacitor is formed inside the source electrode. A thin film transistor device, characterized in that it comprises a lower electrode.   2. The thin film transistor device according to claim 1, wherein the source electrode also serves as a capacitor upper electrode.   2. The planar arrangement is characterized in that the source electrode is a quadrangular shape with rounded corners, and the gate electrode and the drain electrode have a C-shape with one side of a quadrilateral having a uniform width. Alternatively, the thin film transistor device according to claim 2.   4. The thin film transistor device according to claim 1, wherein the semiconductor layer is made of an oxide semiconductor or an organic semiconductor.   A plurality of thin film transistor devices according to any one of claims 1 to 4 are arranged in a matrix on an insulating substrate, and the plurality of thin film transistor devices includes gate wiring, source / drain wiring, and capacitor wiring. A thin film transistor array, wherein the thin film transistor array is electrically connected to each other.   6. A thin film transistor display using the thin film transistor array according to claim 5.   A gate electrode made of a conductive film and a capacitor lower electrode are formed on an insulating substrate, a gate insulating film is formed thereon, and then a source electrode and a drain electrode made of a conductive film are formed on the gate insulating film, and the gate A semiconductor layer is formed on a part of the insulating film so as to be in contact with the source electrode and the drain electrode (the semiconductor layer and the source / drain electrode may be formed in any order first), and the source electrode including the semiconductor layer, After forming an interlayer insulating film on the drain electrode and the gate insulating film, a via hole is formed at a predetermined position of the interlayer insulating film, a conductor layer is formed in the via hole, and further on the interlayer insulating film including the via hole The method for manufacturing a thin film transistor device according to claim 1, further comprising: a step of forming a pixel electrode.   8. The method of manufacturing a thin film transistor device according to claim 7, wherein the step of forming the semiconductor layer includes at least a printing step.   9. The method of manufacturing a thin film transistor device according to claim 7, wherein the step of forming the source electrode, the drain electrode, and the capacitor lower electrode includes at least a printing step.   The method for manufacturing a thin film transistor device according to claim 7, wherein the step of forming a conductor layer in the via hole includes at least a printing step.

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