JP2019070817A - Display device - Google Patents

Abstract

To provide an organic EL display device capable of reducing a leak current when an oxide semiconductor transistor is off.SOLUTION: There is provided a display device in which a pixel circuit is formed in a matrix. The pixel circuit comprises at least a light-emitting element which emits light according to current, a first transistor which applies a driving voltage to the light-emitting element, a capacitive element which applies a prescribed voltage to a gate terminal of the first transistor at least during one frame period, and a second transistor which writes an image signal in the capacitive element on the basis of a selection signal. The first and second transistors are formed of an oxide semiconductor. The second transistor comprises two gate electrodes formed side by side so as to overlap an active layer region of the same transistor. The same selection signal is input to the two gate electrodes.SELECTED DRAWING: Figure 13

Description

  The present invention relates to a display device, and more particularly to an active matrix display device in which an EL (Electro Luminescence) element is used as a display pixel and a TFT for driving the EL element is provided for each pixel.

  In the conventional active matrix organic EL display (OLED), an LTPS-TFT (low-temperature polysilicon TFT) using low-temperature polysilicon for the active layer is used as a driving transistor.

  However, in the active matrix organic EL display device, the ratio of the cost of the LTPS-TFT for driving the organic EL element to the whole is high, and in particular, the LTPS-TFT has a problem that the cost required for manufacturing is large.

  For this purpose, the use of a-Si TFT (amorphous silicon TFT) has been considered, but a-Si has low mobility and the threshold voltage Vt of the TFT is easily shifted (variation), so organic EL of organic EL display device It is difficult to use an a-Si TFT for driving the device.

  As a method of solving this problem, as shown in Patent Document 2 and Patent Document 3, a TFT using an oxide semiconductor has been studied.

  Further, Patent Document 1 discloses an organic EL display device using an oxide semiconductor TFT.

JP, 2006-186319, A Unexamined-Japanese-Patent No. 2006-165532 Japanese Patent Application Publication No. 2007-150157

  In a conventional organic EL display device, a drive transistor for driving an organic EL element, a capacitor for storing a charge for holding a voltage level of a gate electrode of the drive transistor at a predetermined level for one frame period, and a video signal to the capacitor And a switching transistor for writing at least each pixel. With this configuration, a current corresponding to the charge amount is written to the capacitor via the switching transistor every one frame period, and the driving transistor causes a current to flow, and the organic EL element emits light.

  On the other hand, as shown in Patent Documents 1 to 3, when a transistor is formed of an amorphous oxide semiconductor, as shown in the gate voltage-drain current characteristics of FIG. Although it decreases, the decrease in current gradually becomes gradual because electrons with low mobility remain around 0 V.

  Therefore, when a conventional amorphous oxide semiconductor is used as a switching transistor for writing a video signal to a capacitor, the amount of charge stored in the capacitor decreases with the passage of time. That is, a leak occurs between the source and the drain, the charge of the capacitor can not be maintained for one frame period, and the light emission with the same light amount can not be maintained for one frame period.

  An object of the present invention is to provide a display device in which the off-state leakage current of an oxide semiconductor transistor is reduced.

  Another object of the present invention is to provide a display device capable of image display without display unevenness with a simple pixel circuit.

  In order to solve the above problems, the invention according to claim 1 comprises a light emitting element which emits light according to a current, a first transistor which applies a drive voltage to the light emitting element, and at least one frame period of the first transistor. A display device in which a pixel circuit including at least a capacitive element for applying a predetermined voltage to a gate terminal and a second transistor for writing an image signal to the capacitive element based on a selection signal is arranged in a matrix. The first and second transistors are formed of an oxide semiconductor, and the second transistor includes two gate electrodes formed in parallel so as to overlap the active layer region of the same transistor, and the two gate electrodes are formed on the two gate electrodes. This is a display device to which the same selection signal is input.

  According to a second aspect of the present invention, in the display device according to the first aspect, the first and second transistors are N-type oxide semiconductors.

  According to a third aspect of the present invention, in the display device according to the first or second aspect, a part of one of the two gate electrodes overlaps a source electrode. The other gate electrode is formed so as to overlap with the drain electrode.

  In order to solve the above problems, the invention according to claim 4 is the display device according to any one of claims 1 to 3, wherein the first and second transistors are formed of an InGaZnOx-based oxide semiconductor. It is.

  In order to solve the above problems, the invention according to claim 5 is the display device according to any one of claims 1 to 4, in which the gate insulating film of the first and second transistors is formed of a silicon oxide film. It is

  In order to solve the above problems, the invention according to claim 6 is the display device according to claim 5, wherein the silicon oxide film is a film which has been annealed.

  In order to solve the above problems, the invention according to claim 7 is the display device according to any one of claims 1 to 4, in which the gate insulating film of the first and second transistors is formed of a SiN film. It is.

  In order to solve the above problems, the invention according to claim 8 is the display device according to any one of claims 1 to 7, wherein the light emitting element comprises an EL element.

  In order to solve the above problems, the invention according to claim 9 is the display device according to any one of claims 1 to 8, wherein the display device is a top emission type.

  In order to solve the above problems, the invention according to claim 10 is the display device according to any one of claims 1 to 8, wherein the second transistor is driven by a selection signal of 0 V or more.

  In the display device of the present invention, two gate electrodes are formed in parallel in the same semiconductor region of the second transistor, and the same selection signal is input to the two gate electrodes. By stopping the carriers from the source electrode at the first gate electrode and lowering the carrier density between the gate electrodes, an effect more than doubling the resistance of the transistor can be obtained.

  As a result, even when the second transistor which is an oxide semiconductor is used for a pixel circuit of a display device, leakage current when the second transistor is off can be reduced.

  Further, since a leak current at the time of off of the second transistor can be reduced, a silicon oxide film which can further stabilize the threshold voltage can be used as the gate insulating film. As a result, it is possible to perform image display without display unevenness with a simple pixel circuit.

  Other effects of the present invention will be apparent from the entire description of the specification.

It is sectional drawing for demonstrating schematic structure of the amorphous oxide semiconductor transistor in the organic electroluminescence display which is a display apparatus of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is a circuit diagram for demonstrating schematic structure of the pixel circuit of the organic electroluminescence display of embodiment of this invention. It is a figure for demonstrating the operation | movement of the pixel circuit of the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a perspective view for demonstrating schematic structure of the organic electroluminescence display which is a display apparatus of embodiment of this invention. It is sectional drawing in the AA of FIG. It is a figure for demonstrating the operation | movement of the pixel circuit of the organic electroluminescence display of other embodiment of this invention. It is a figure for demonstrating the gate voltage-drain current characteristic at the time of forming a transistor with the conventional amorphous oxide semiconductor.

  Hereinafter, examples of embodiments to which the present invention is applied will be described using the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description will be omitted.

(Embodiment 1)
<Whole composition>
FIG. 19 is a perspective view for explaining a schematic configuration of an organic EL display device which is a display device according to an embodiment of the present invention, and FIG. 20 is a cross-sectional view taken along line AA of FIG.

  As shown in FIG. 19, the organic EL display device of the present embodiment is constituted of a TFT substrate (first substrate) 19-1 on which an OLED layer is formed and a sealing glass (second substrate) 19-2. There is. The TFT substrate 19-1 and the sealing glass 19-2 are fixed by a sealing sealing material 19-3, and the structure in which the space between the TFT substrate 19-1 and the sealing glass 19-2 is held in vacuum It has become.

  Also, an OLED (organic light emitting diode, organic electroluminescent element, light emitting layer) that emits R (red), G (green), and B (blue) that become pixels in a region surrounded by the sealing sealing material 19-3 Are arranged in a matrix in the x and y directions in the drawing to form a pixel area 19-4.

  Furthermore, an electrode line formed on the TFT substrate 19-1 and connected to each pixel extends beyond the sealing sealing material 19-3 to the outside of the pixel region 19-4. A terminal portion 19-5 is formed at an end portion of the electrode line, and a control signal is externally input to a pixel formed on the TFT substrate 19-1.

  Further, in the present embodiment, a control signal input from the outside includes a video signal corresponding to the light emission amount of each pixel, a gate signal which designates writing of the video signal to each pixel and which becomes one power supply at the time of light emission. And a power supply for supplying a 6V power supply voltage. Therefore, in the organic EL display device according to the present embodiment, the video signal line for inputting the video signal, the gate signal line for inputting the gate signal, and the power supply line for supplying power exceed the sealing sealing material 19-3 and are external It is the composition that is pulled out. The detailed configuration of the pixel circuit (circuit for one pixel cell) of the present embodiment will be described later.

  When a signal line for designating writing of a video signal to each pixel is formed separately as in the conventional pixel circuit and a power supply line for supplying one power, electrode lines and terminals corresponding to each are separately formed. By forming the portion 19-5, the present invention is applicable.

  As shown in FIG. 20, in the organic EL display device of this embodiment, pixels are formed in the region between the TFT substrate 19-1 and the sealing glass 19-2. In addition, since the light emitting material used for the light emitting layer has a very weak property to humidity, in the present embodiment, the known transparent desiccant 20-5 is formed on the inner side of the sealing glass 19-2, ie, on the pixel formation side. The structure is

  Further, the cathode electrode 20-2 of the light emitting layer (OLED) and the pixel separation film 20-1 are formed on the upper surface side (pixel formation side) of the TFT substrate 19-1, and the cathode electrode 20-2 is formed. A light emitting layer (OLED, light emitting portion) 20-3 and an anode electrode 20-4 formed of a known transparent electrode material are formed in the upper layer of the pixel separation film 20-1. As described later, in the organic EL display device of the present invention, since the oxide semiconductor FET which is an n-type semiconductor is used, each pixel has a top anode type. Although it is possible to configure the pixel of the present invention in combination with the top cathode type light emitting layer (OLED), in this case, it is necessary to increase the driving voltage of the peripheral circuits by several V than the top anode type. There is.

  Further, the distance between the TFT substrate 19-1 and the sealing glass 19-2 is determined by the thickness of the transparent desiccant 20-5, and in the present embodiment, a part of the transparent desiccant 20-5 is an anode. It is configured to be in contact with the electrode 20-4. The entire surface of the transparent desiccant 20-5 may be in contact with the anode electrode 20-4.

  Furthermore, since the organic EL display device of the present embodiment is a so-called top emission type display device, each light of RGB emitted by the OLED layer 20-3 of each pixel is transparent to the anode electrode 20-4. The light is emitted in the direction of the arrow 20-6 through the desiccant 20-5 and the sealing glass 19-2. The present invention is also applicable to a so-called bottom emission type organic EL display device.

  In this embodiment, the sealing and sealing material 19-3 is configured to use a known epoxy resin, and the transparent desiccant 20-5 is configured to use an aluminum alkoxide of a known high molecular alcohol. In addition, sealing sealing material 19-3 and the transparent desiccant 20-5 are not limited to the said material, Other materials may be sufficient.

<Configuration of pixel circuit>
FIG. 11 is a circuit diagram for explaining a schematic configuration of a pixel circuit of the organic EL display device of the present invention, and FIG. 12 is a diagram for explaining an operation of the pixel circuit of the organic EL display device of the present invention. Note that the configuration of the pixel circuit is not limited to this, and can also be applied to a pixel circuit having a circuit or the like that compensates for variations in transistors in each pixel circuit. The pixel circuit shown in FIG. 11 is a pixel circuit for 2 × 2 four pixels.

  As shown in FIG. 11, the pixel circuit of the present invention comprises a light emitting layer (OLED) which is a diode D, and a power supply line (common electrode line for supplying a power supply voltage of 6 V which is one power supply voltage to the light emitting layer (OLED). And the first transistor T1 that controls the current flowing through the diode D, that is, the light emission amount of the light emitting layer (OLED), the gate signal line VSS that also functions as the other power supply line, and the drain-source terminal of the first transistor T1. And a second transistor T2 for writing a video signal of at least one frame in the capacitor C, and a video signal line DATA for supplying a video signal to the second transistor T2. There is.

  The configuration of the pixel circuit of the present embodiment shown in FIG. 11 will be described in detail below.

  A power supply voltage of 6 V is applied to the anode side of the diode D via the power supply line V1. The cathode side of the diode D is connected to the gate signal line VSS via the first transistor T1, and the current corresponding to the voltage applied to the gate terminal of the first transistor T1 causes the diode D to The flow is such that the light emission amount of the light emitting element is controlled.

  Further, a capacitor C is formed between the gate and source of the first transistor T1, and the drain terminal of the second transistor T2 is connected to one end of the capacitor C, that is, the gate terminal of the first transistor T1. The structure is On the other hand, the source terminal of the second transistor T2 is connected to the video signal line DATA for supplying the video signal, and the video signal is written to the capacitor C. At this time, since one end of the capacitor C is connected to the gate terminal of the first transistor T1, the voltage corresponding to the video signal written to the capacitor C is at least one frame period to the gate of the first transistor T1. It will be applied. The details of the video signal writing operation will be described later.

  Furthermore, the gate terminal of the second transistor T2 is configured to be connected to the gate signal line VSS, and the video signal line DATA of the video signal line DATA connected to the source terminal according to the write signal applied to the gate signal line VSS. A video signal is written to the capacitor C.

  Next, based on FIG. 12, the operation in the pixel circuit of the present embodiment will be described in detail. However, in the following description, only the operation of the upper left pixel circuit in FIG. 11 will be described. Further, the voltage waveform shown in FIG. 12 shows the voltage waveform applied to the gate signal line VSS and the video signal line DATA connected to the pixel circuit at the upper left in FIG.

  In the period t1 to t2, a voltage of 0 V is applied to the gate terminal of the second transistor T2, so the second transistor T2 is in the off state. Therefore, the charge stored in the write operation one frame before is held in the capacitor C, and a voltage corresponding to the charge of the capacitor C is applied to the gate terminal of the first transistor T1. Therefore, the first transistor T1 applies a current corresponding to the charge of the capacitor C to the diode D, and the diode D continuously emits light with a light emission amount corresponding to the current. At this time, in the organic EL display device of the present embodiment, the second gate electrode is formed of an amorphous oxide semiconductor by forming two gate electrodes in parallel in the same active layer of the second transistor T2. Since the leak current between the source and the drain of the transistor T2 is significantly reduced, the charge written to the capacitor C can be held for one frame period.

  In the period t2 to t3, the write voltage V2 is applied to the gate terminal of the second transistor T2, and the second transistor T2 is turned on. For this reason, the video signal Vd1 supplied to the video signal line DATA in the corresponding period is applied (written) to the capacitor C via the second transistor T2. Therefore, the video signal Vd1 is applied to the gate terminal of the first transistor T1, and the first transistor T1 passes a current according to the applied voltage Vd1 to the diode D, and the diode D continues to emit light according to the current. It emits light.

  In the period t3 to t4, since the voltage of 0 V is applied to the gate terminal of the second transistor T2 again, the second transistor T2 is turned off. The applied voltage Vd1 stored in the write operation in the period t2 to t3 is held by the capacitor C, and the applied voltage Vd1 is applied to the gate terminal of the first transistor T1. Therefore, the first transistor T1 applies a current corresponding to the applied voltage Vd1 written to the capacitor C to the diode D, and the diode D continuously emits light with a light emission amount corresponding to the current.

  In the period after t4, the same operation as in the period t3 to t4 is performed until the next writing period, and the pixel circuit continues to emit light with a light emission amount corresponding to the applied voltage Vd1. Further, the same light emission operation is performed in the other pixel circuits, so that desired image display can be performed.

  Furthermore, in the organic EL display device of the present embodiment, since the first transistor T1 is also formed of an amorphous oxide semiconductor, the diode D can stably emit light.

<Structure of transistor>
FIG. 1 is a cross-sectional view for explaining a schematic configuration of an amorphous oxide semiconductor transistor in the organic EL display device of the present embodiment.

  As shown in FIG. 1, in the transistor of this embodiment, a barrier layer 2 of aluminum oxide is formed on the surface of a glass substrate 1, and an InGaZnOx film 3 to be an active layer of an oxide semiconductor is formed on the barrier layer 2. The structure is By adopting such a configuration, entry of impurities from the glass substrate 1 to the InGaZnOx film 3 causing the shift of the threshold voltage Vth of the transistor or the like is prevented.

  In the upper layer of the InGaZnOx film 3, the SD wiring 4 of the Mo film to be the source or drain of the amorphous oxide semiconductor transistor is separately formed to sandwich the channel portion to be the active layer. The SD wiring 4 made of this Mo film has a shape with rounded corners.

  A gate insulating film 5 made of a silicon oxide film (SiOx film, silicon oxide film) is formed on the SD wiring 4 and the film thickness of the channel portion is formed to be about 50 nm. Further, in the present embodiment, the SiOx film annealed at a high temperature is used as the gate insulating film 5 in order to prevent the shift of the threshold voltage which is a drawback when the SiOx film is used for the gate insulating film 5. .

  In the upper layer of the gate insulating film 5 in the channel portion, a gate wiring 6 having a three-layer structure of Mo / Al / Mo is formed. At this time, in the present embodiment, as a configuration for preventing the disconnection of the gate wiring 6, the gate wiring 6 is formed with a thickness twice or more the level difference of the base layer. Further, in the present embodiment, in the contact hole portion of the gate insulating film 5 provided on the upper side of the wiring to be the drain electrode in the SD wiring 4, the same layer as the gate wiring 6 and the same thin film as the gate wiring material A thin film layer made of a material is formed. The thin film layer is electrically connected to the wiring on the side to be the drain electrode in the SD wiring 4.

  In the upper layer of the gate wiring 6, the function of a planarizing film for planarizing the unevenness on the front surface of the glass substrate 1 accompanying the formation of the transistor and the wiring layer not shown, and the function as a protective film of the transistor and the wiring layer not shown An insulating film 7 made of a photosensitive polyimide resin is formed.

  An electrode layer 8 of a light emitting layer (OLED, diode) formed of an ITO / Ag / ITO laminated film is formed on the insulating film 7, and a pixel separation film 9 of photosensitive polyimide is formed on the electrode layer 8. It is done.

  This embodiment is a TFT substrate having a configuration in which the amorphous oxide semiconductor transistor having such a configuration is used for driving the light emitting layer.

<Method of manufacturing transistor>
FIGS. 2 to 10 are process diagrams for explaining the manufacturing method of the first and second transistors in the organic EL display device of the present embodiment, and the manufacturing method will be described in order of steps based on FIGS. 2 to 10 below. Do. In addition, since formation of the thin film including formation of the electrode in each process is possible by the well-known photolithographic technique, detailed description is abbreviate | omitted.

Step 1 (Figure 2)
First, an aluminum oxide film is formed on the surface of a glass substrate 1 as a barrier layer 2 by sputtering, and then an InGaZnOx film 3 to be an active layer of an oxide semiconductor is formed by sputtering. An Mo film to be an SD wiring (abbreviated as 4) is continuously formed. The film thickness at this time is about 70 nm for the aluminum oxide film, about 60 nm for the InGaZnOx film 3, and about 180 nm for the Mo film.

Step 2 (Figure 3)
Next, a pattern (SD pattern) for forming a source or drain wiring (SD wiring) 4 by molding a Mo film, and a pattern for forming a channel portion to be an active layer in the InGaZnOx film 3 are made of photoresist 10. Form. However, this pattern is formed by exposure using a photomask made like a half mirror so that the channel portion is formed thin. In the pattern of the photoresist 10, the resist film thickness of the SD portion is 1.4 μm, and the channel portion is 0.4 μm.

Step 3. (Figure 4)
Next, the Mo film (both sides in the drawing) to be the SD wiring 4 and the InGaZnOx film 3 (both sides in the drawing) are etched by wet etching using the photoresist 10 formed in the step 2. At this time, the Mo film is wet etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Further, the InGaZnOx film 3 is wet etched using boric acid. Thereafter, the photoresist 10 is removed by plasma ashing to a thickness of about 0.6 .mu.m to expose the Mo film in the channel portion and to narrow the width of the photoresist 10 in the SD wiring portion in the figure. Thereafter, the Mo film is wet-etched again using a mixed acid of phosphoric acid, acetic acid, and nitric acid to remove the Mo film in the channel portion and remove both sides in the drawing of the Mo film, thereby removing the Mo film from the InGaZnOx film 3 Reduce the width of the pattern in the figure.

  With such a shape, it is possible to eliminate the portion where the SD wire 4 rides over the InGaZnOx film 3 (oxide semiconductor layer), and disconnection of the SD wire 4 due to a step can be avoided. Further, by forming the SD wire 4 smaller than the InGaZnOx film 3 (oxide semiconductor layer), it is possible to easily cover the laminated portion (portion of the SD wire 4) with a gate insulating film described later.

  Furthermore, in the present embodiment, in order to further facilitate the cover by the gate insulating film, first, ashing is performed after the peeling of the photoresist 10, thereby oxidizing the corner portion of the SD wire 4 formed of the Mo film. Thereafter, by washing with water, the corner of the SD wire 4 is rounded.

Step 4 (Figure 5)
Next, a gate insulating film 5 is formed, and a contact hole 11 is formed in the gate insulating film 5 by photolithography. The gate insulating film 5 is formed by decomposing TEOS (4-ethyloxysilane) gas and oxygen by plasma CVD to form a SiOx film. The contact holes 11 are formed by wet etching, and buffered hydrofluoric acid is used as an etchant. Thus, the gate insulating film 5 having a thickness of about 50 nm is formed. In addition, the inclined region 12 a is formed at the peripheral edge (upper end of the peripheral edge) of the formation region 12 of the gate wiring. In the formation of the inclined region 12 a, when a gate wiring is formed in a later step, both end portions of the gate wiring and the end portion of the SD wiring overlap with each other via the gate insulating film 5. This is to smooth the formation of the channel region between the source and the gate.

  However, since deep defect levels in the SiOx film formed by the plasma CVD method can be eliminated by high temperature annealing, also in this embodiment, annealing is performed at 400 ° C. or higher, preferably 450 ° C. to 550 ° C. , To reduce to practically no problem. In the deep defect state in the gate insulating film, electrons collected at the interface between the gate insulating film 5 and the InGaZnOx film 3 (oxide semiconductor layer) enter the fixed charge when the transistor is turned on. It causes the threshold voltage of the transistor to shift.

Step 5. (Figure 6)
Next, the gate wiring 6 is formed. At this time, the gate wiring 6 is formed so that the both ends of the gate wiring 6 and the end of the SD wiring 4 overlap via the gate insulating film 5. The gate wiring 6 of this embodiment has a three-layer structure of Mo / Al / Mo, and in order to prevent disconnection due to a step, the total film thickness of Mo: 50 nm, Al: 400 nm, Mo: 50 nm is 500 nm. In the present embodiment, since the step of the base is 240 nm, the thickness of the gate wiring 6 is about twice that to prevent disconnection. Therefore, the thickness of the gate wiring 6 is not limited to 500 nm. For example, in the case where the film thickness of the InGaZnOx film 3 (oxide semiconductor layer) is 40 nm and the film thickness of the SD wiring 4 is 120 nm, the gate Even if the film thickness of the wiring layer 6 is about 350 nm, disconnection can be prevented. Also, in order to make the depth of the contact hole 11 shallow and to make it easy to open, the gate wiring material 6a in the contact hole portion is left.
Step 6. (Figure 7)
Next, an insulating film 7 is formed to insulate the wiring of the transistor and the electrode of the light emitting layer (OLED, diode). The insulating film 7 is formed by applying photosensitive polyimide on the upper layer by a known spin coating method or the like, and then performing exposure development. After the formation of the insulating film 7, a contact hole 13 for electrically connecting the electrode of the light emitting layer (OLED, diode) and the SD wiring 4 is formed on the gate insulating material 6a by known photolithography. Note that by using the coating type insulating film 7, unevenness on the surface of the substrate accompanying the formation of the transistor and the wiring can be made smooth, so that it is possible to obtain an effect of eliminating corner portions that cause light scattering in particular. . The film thickness of this polyimide, that is, the film thickness of the insulating layer 7 is about 1.5 μm.

Step 7 (Figure 8)
Next, an ITO / Ag / ITO laminated film to be the electrode 8 of the light emitting layer (OLED, diode) is formed. The ITO / Ag / ITO laminated film is formed by continuously sputtering ITO, Ag, and ITO in order, and then forming the film into a predetermined pattern by known photolithography. In addition, although it is possible to perform etching of ITO with oxalic acid and etching of Ag with a mixed acid of phosphoric acid, acetic acid, and nitric acid, it is not limited to this. In addition, the film thickness of each of the ITO layer is about 50 nm, the Ag layer is about 150 nm, and the ITO layer is about 30 nm from the lower side (the glass substrate 1 side).

Step 8. (Figure 9)
Next, the pixel separation film 9 is formed. The pixel separation film 9 is formed by applying photosensitive polyimide by a known spin coating method or the like, exposing and developing it, and then forming an opening on the electrode 8.

  Through the above steps 1 to 8, the transistor array substrate for active driving the light emitting layer (OLED, diode) is completed.

  However, in the organic EL display device of the present embodiment, the configuration of the gate electrode is different between the first transistor and the second transistor. Hereinafter, a method of manufacturing the second transistor will be described.

  As shown in FIG. 10, the second transistor has a configuration in which two gate wirings 14a and 14b are formed in parallel between SD wirings 4 formed apart from each other, that is, in the same active layer region.

  Such gate wiring is formed by etching each of the Mo layer, etching the Al layer, and etching the Mo layer in forming the gate wiring having a three-layer structure of Mo / Al / Mo in step 5 described above. By forming the two gate wirings 14a and 14b, the subsequent steps are the same as the above-described method of manufacturing the first transistor.

  At this time, in the present embodiment, the gate wiring 6 of the first transistor shown in FIG. 9 is divided into two into the source side and the drain side, so that one end of the gate wiring 14a is the source wiring. The other gate wiring 14b has a structure in which the end thereof overlaps with the end of the drain wiring.

  With such a structure, in the oxide semiconductor, the effect more than doubling the resistance of the transistor can be obtained, and the leakage current between the source and the drain can be significantly reduced. That is, since two transistors are connected in series, the resistance is effectively doubled, but in the oxide transistor, the mobility decreases as the number of carriers decreases, and the carrier leaks from the source. Thus, the carrier concentration in the channel portion to be originally depleted is increased, and the mobility is also increased, thereby increasing the leak current. Therefore, in the present embodiment, the carriers from the source are stopped at the first gate by continuously providing the gates (two gate wirings are formed in parallel), and the carrier density between the gate electrodes is lowered. Thus, the effect of doubling the resistance of the transistor can be obtained, and the leakage current between the source and the drain can be significantly reduced. Furthermore, in the present embodiment, the respective end portions of the two gate wirings 14a and 14b are configured to overlap with any of the end portions of the source wiring or the drain wiring, so that the oxide semiconductor The effect is also obtained that the increase in the ON resistance of the two transistors can be minimized.

<Method of manufacturing pixel circuit>
13 to 18 are plan views for explaining the method of manufacturing the pixel circuit in the organic EL display device of the present embodiment. Hereinafter, the manufacturing method will be described in order based on FIG. 13 to FIG. In addition, since formation of the thin film including formation of the electrode in each process is possible by the well-known photolithographic technique, detailed description is abbreviate | omitted.

Step 1 (Figure 13)
First, after an oxide semiconductor layer (InGaZnOx layer) for forming an active layer of an oxide semiconductor is formed on the upper surface (TFT element formation) side of a glass substrate (not shown) having a barrier layer formed on the substrate surface, SD An electrode layer pattern to be a wiring layer and a signal line (video signal wiring layer) is formed. In FIG. 13, an SD wiring layer pattern 13-1 serving as an SD electrode of the first transistor and a pixel are provided in a region between two adjacent signal line patterns 13-3 for applying a write voltage to each pixel capacitor-. An electrode layer pattern is formed which is an electrode pattern 13-2 of one of the capacitors and an SD electrode pattern of the second transistor.

  As apparent from FIG. 13, the oxide semiconductor layer pattern 13-5 and the SD wiring layer pattern 13-1 almost overlap each other, and the SD wiring layer pattern 13-1 is an oxide semiconductor layer pattern 13-. Since it does not ride on 5 or fall off, the SD wiring layer pattern 13-1 does not break at the step of the oxide semiconductor layer pattern 13-5. Further, in a portion where the gate wiring layer pattern described later passes over the SD wiring layer pattern 13-1, the unevenness 13-4 is provided in the SD wiring layer pattern. By forming the asperities 13-4 in this manner, it is possible to make the crossing line into a curved shape, and to avoid the phenomenon that the etching liquid infiltrates between the resist and the gate wiring material to cause disconnection when etching the gate wiring.

Step 2 (Figure 14)
Next, the gate insulating film pattern 14-2 is formed on the upper surface of the glass substrate (not shown). At a place where the gate wiring layer pattern to be described later and the SD wiring layer pattern 13-1 are electrically connected, and where the SD wiring layer pattern 13-1 and the electrode of the light emitting layer (OLED, diode) are electrically connected Form a contact hole 14-1.

Step 3. (Figure 15)
Next, gate wiring patterns and signal line patterns are formed. In this step, the gate electrode pattern 15-1 of the first transistor T1, the gate electrode pattern 15-4 of the second transistor T2, and the other electrode pattern 15-2 of the pixel capacitor C are formed. Furthermore, a wiring pattern 15-3 is formed, which supplies power to the light emitting layer (OLED, diode) and sends an open / close signal (gate signal) to the second transistor (write transistor). In particular, in the present embodiment, double gate electrode patterns 15-5, that is, two gate electrode patterns 15-5 arranged side by side are formed as the gate electrode patterns 15-5 of the second transistor T2.

  In the formation of the capacitor, the electrode pattern 13-2 in the same layer as the SD wiring layer and the electrode pattern 15-2 in the same layer as the gate wiring layer are formed so as to overlap via the gate insulating film pattern 14-2. . In the present embodiment, the pattern on the gate wiring layer side (electrode pattern 15-2 in the same layer as the gate wiring layer) is referred to as the pattern on the SD wiring layer side (electrode pattern 13-2 in the same layer as SD wiring layer). By forming the pattern on the gate wiring layer side smaller than the pattern on the SD wiring layer side and not protruding from the pattern on the SD wiring layer side, a short circuit is caused by a step on the outer peripheral portion of the SD wiring pattern. You are avoiding getting up.

  Furthermore, in the present embodiment, the contact hole portion 14-1 is made higher by forming the contact hole portion 14-1 of the gate insulating film pattern 14-2 with the gate electrode pattern 15-4 remaining. The coating thickness of the photosensitive polyimide in the contact hole portion provided in the photosensitive polyimide layer in the process described later is reduced, and the contact hole is surely opened.

Step 4 (Figure 16)
Next, a photosensitive polyimide layer pattern 16-2 is formed to smooth irregularities on the surface of the glass substrate (not shown). After the formation of the photosensitive polyimide layer pattern 16-2, the contact hole pattern 16-1 for electrically connecting the electrode of the light emitting layer (OLED, diode) and the SD wiring layer pattern 13-1 to the gate electrode pattern 15 is formed. Form in -4 part.

Step 5. (Figure 17)
Next, the electrode pattern 17-1 of the light emitting layer (OLED, diode) is formed in the region between the two adjacent signal line patterns 13-3. The light emitting layer (OLED, diode) electrode pattern 17-1 is electrically connected to the SD wiring layer pattern 13-1 through the contact hole 16-1 provided in the photosensitive polyimide layer pattern 16-2.

Step 6. (Figure 18)
Next, a photosensitive polyimide layer is formed on the surface of a glass substrate (not shown), and then an opening 18-1 is formed above the light emitting layer (OLED, diode) electrode pattern 17-1 to form a pixel separation film pattern. . However, when forming the opening 18-1, the opening 18-1 is formed so that the peripheral portion of the light emitting layer (OLED, diode) electrode pattern 17-1 and the contact hole 16-1 are covered with the photosensitive polyimide layer. By forming it, the light emitting layer (OLED, diode) electrode pattern (cathode) 17-1 and the anode are not short-circuited.

  As described above, the transistor array substrate is manufactured.

  Next, a procedure for forming a light emitting layer (OLED, diode) on the transistor array substrate will be described.

  First, the first substance of electron transportability and the second substance are co-deposited on the top of the opening 18-1 of the light emitting layer (OLED, diode) electrode pattern (cathode) 17-1 provided on the transistor array substrate. To form an electron injection layer.

  Next, a first substance is deposited over the electron injection layer to form an electron transport layer. The film thickness of the electron transport layer differs depending on each emission color, and is 130 nm for red, 100 nm for green, and 70 nm for blue.

  Next, a light emitting layer is formed on the electron injection layer. At this time, the film thickness is 60 nm when forming the red light emitting layer, the film thickness is 60 nm when forming the green light emitting layer, and the film thickness is 60 nm when forming the blue light emitting layer. .

  Next, a hole transport layer is formed of a third substance in the upper layer of the light emitting layer.

  Next, a hole injection layer is formed on the hole transport layer. The film thickness of the hole injection layer is 10 nm.

  Next, an anode electrode having a film thickness of 30 nm is formed on the hole injection layer by sputtering of IZO, whereby an organic EL device is configured. The organic EL device emits light by applying a negative voltage to the cathode electrode and a positive voltage to the upper anode electrode.

  The first substance is not particularly limited as long as it exhibits electron transportability and can easily be a charge transfer complex by co-evaporation with an alkali metal. For example, tris (8-quinolinolato) aluminum, tris (4- (4) Metal complexes such as methyl-8-quinolinolato) aluminum, bis (2-methyl-8-quinolinolato) -4-phenylphenolate-aluminum, bis [2- [2-hydroxyphenyl] benzoxazolate] zinc, and 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole, 1,3-bis [5- (p-tert-butylphenyl) -1,3,4- Oxadiazol-2-yl] benzene etc. can be used.

  The second substance is not particularly limited as long as it is a material exhibiting an electron donating property to the electron transporting substance, and examples thereof include: alkali metals such as lithium and cesium; alkaline earth metals such as magnesium and calcium; Further, a material which exhibits an electron donating property can be used, which is selected from metals such as rare earth metals, or oxides, halides and carbonates thereof.

  The third substance is a substance exhibiting hole transportability, and examples thereof include tetraarylbenzidine compounds (triphenyldiamine: TPD), aromatic tertiary amines, hydrazone derivatives, carbazole derivatives, triazole derivatives, imidazole derivatives, Oxadiazole derivatives having an amino group, polythiophene derivatives, copper phthalocyanine derivatives and the like can be used.

In addition, as a material used for the hole injection layer, an inorganic material such as MoO ₃ , WO ₃ or V ₂ O ₅ can be used. By using such a substance as the hole injection layer, it is possible to obtain an effect that deterioration of the organic material can be avoided even if the anode electrode IZO is sputtered.

  In addition, as a light emitting material used for the light emitting layer, a host material capable of transporting electrons and holes is added with a dopant that emits fluorescence or phosphorescence due to recombination thereof, and can be formed as a third layer by co-evaporation The host is not particularly limited as long as it is a substance, for example, tris (8-quinolinolato) aluminum, bis (8-quinolinolato) magnesium, bis (benzo {f} -8-quinolinolato) zinc, bis (2-methyl-8) -Quinolinolato) aluminum oxide, tris (8-quinolinolato) indium, tris (5-methyl-8-quinolinolato) aluminum, 8-quinolinolatolithium, tris (5-chloro-8-quinolinolato) gallium, bis (5-chloro) -8-quinolinolato) calcium 5,7-dichloro-8-quinolinolato Ruminium, Tris (5,7-dibromo-8-hydroxyquinolinolato) aluminum, complexes such as poly [zinc (II) -bis (8-hydroxy-5-quinolinyl) methane], anthracene derivatives, carbazole derivatives, etc. Can be used.

  As the dopant, a substance that emits light by capturing electrons and holes in the host and recombining, for example, red for pyran derivative, green for coumarin derivative, and blue for anthracene derivative can be used. Further alternatively, a substance which emits phosphorescence such as an iridium complex or a pyridinate derivative can also be used.

  The uppermost layer, that is, the anode electrode uses ITO or IZO, which is a transparent conductive film, to extract light.

  Since the light emitting layer is weak to moisture, it is necessary to seal by sealing dry nitrogen or the like. Alternatively, it is also possible to place a desiccant inside as in the present embodiment, in consideration of moisture entering from the outside. Further, it may be sealed with frit glass or the like so that moisture does not enter at all. In addition, in the top emission type organic EL display device as in this embodiment, the sealing glass is transparent, and light is emitted through the sealing glass.

  Further, in the organic EL display device according to the present embodiment, the silicon oxide film subjected to the annealing process is used as the gate insulating film of the amorphous oxide semiconductor forming the first and second transistors, but the invention is limited thereto. For example, a SiN film formed by plasma CVD may be used as a gate insulating film.

  In addition, when the first and second transistors are formed of an amorphous oxide semiconductor using a silicon oxide film as the gate insulating film, the SiN film is formed outside the gate insulating film, that is, in the upper layer when using the SiN film as a passivation film. There is a need to.

  As described above, in the organic EL display device according to the present embodiment, as shown in FIG. 10, when forming the second transistor which is a switching transistor, two gate electrodes 14a in the same semiconductor region, that is, in the same channel portion. , 14b are formed side by side. At this time, since the same selection signal (gate signal) is input to two gate electrodes as shown in FIG. 15, carriers from the source electrode are stopped by the first gate electrode 13b, and the carrier density between the gate electrodes is determined. The effect of more than doubling the resistance of the transistor can be obtained by lowering. As a result, even when the second transistor which is an oxide semiconductor is used for the pixel circuit of the organic EL display device, the leak current when the second transistor is off can be reduced.

  Further, since a leak current at the time of off of the second transistor can be reduced, a silicon oxide film which can further stabilize the threshold voltage can be used as the gate insulating film. As a result, even in the organic EL display device, it is possible to perform image display without display unevenness with a simple pixel circuit.

  In the organic EL display device according to the embodiment of the present invention, the gate electrode of the second transistor is formed of two gate electrodes arranged in parallel, but the gate electrode of the second transistor is the gate of the first transistor In the case where one electrode is formed as in the case of the electrode, as shown in FIG. 21, the gate voltage of the second transistor in the off state may be made negative to advance the channel depletion.

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... barrier layer, 3 ... InGaZnOx film | membrane 4 ... SD wiring, 5 ... gate insulating film, 6 ... gate wiring 6a ... gate wiring material, 7 ... Insulating film, 8 ... electrode of light emitting layer 9 ... pixel separation film, 10 ... photoresist, 11 ... contact hole 12 ... formation region of gate wiring, 12a ... inclined region 13, contact holes 14a, 14b: gate wiring, 13-1: SD wiring layer pattern 13-2: electrode pattern of pixel capacitor, 13-3: signal line pattern 13-4 ... Irregularities of wiring pattern, 13-5 ... Oxide semiconductor layer pattern 14-1 ... Contact hole, 14-2 ... Gate insulating film pattern 15-1 ... Gate electrode pattern, 15- 2 ・ ・ ・ Pixel component Electrode pattern 15-3 ... wiring pattern, 15-4 ... gate electrode pattern 15-5 ... gate electrode pattern, 16-1 ... contact hole pattern 16-2 ... photosensitive polyimide Layer pattern, 17-1: Electrode pattern of light emitting layer 18-1: Opening, 19-1: TFT substrate, 19-2: Sealing glass 19-3: Sealing seal Material 19-4: pixel area 19-5: terminal portion 20-1: pixel separation film 20-2: cathode electrode 20-3: OLED layer 20-4 Anode electrode 20-5 Transparent desiccant T1 First transistor T2 Second transistor C Capacitor D Diode V1 power line (common electrode Line), DATA ... video signal line VSS ... Over door signal line

Claims (10)

A light emitting element that emits light according to the current;
A first transistor for applying a drive voltage to the light emitting element;
A capacitive element for applying a predetermined voltage to the gate terminal of the first transistor for at least one frame period;
A display device in which pixel circuits including at least a second transistor for writing an image signal to the capacitive element based on a selection signal are arranged in a matrix.
The first and second transistors are formed of an oxide semiconductor,
A display characterized in that the second transistor includes two gate electrodes formed in parallel so as to overlap the active layer region of the same transistor, and the same selection signal is input to the two gate electrodes. apparatus. In the display device according to claim 1,
The display device, wherein the first and second transistors are N-type oxide semiconductors. In the display device according to claim 1 or 2,
Of the two gate electrodes,
A part of one gate electrode is formed to overlap the source electrode,
A display device characterized in that a part of the other gate electrode is formed to overlap with the drain electrode. The display device according to any one of claims 1 to 3.
The display device, wherein the first and second transistors are formed of an InGaZnOx-based oxide semiconductor. The display device according to any one of claims 1 to 4.
In the display device, the gate insulating film of the first and second transistors is formed of a silicon oxide film. In the display device according to claim 5,
The display device, wherein the silicon oxide film is an annealed film. The display device according to any one of claims 1 to 4.
In the display device, the gate insulating film of the first and second transistors is formed of a SiN film. The display device according to any one of claims 1 to 7.
The display device, wherein the light emitting element comprises an EL element. The display device according to any one of claims 1 to 8.
A display device characterized in that the display device is a top emission type. The display device according to any one of claims 1 to 8.
The display device according to claim 1, wherein the second transistor is driven by a selection signal of 0 V or more.

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