JP4887646B2 - Thin film transistor device and its manufacturing method, thin film transistor array and thin film transistor display - Google Patents

Thin film transistor device and its manufacturing method, thin film transistor array and thin film transistor display Download PDF

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JP4887646B2
JP4887646B2 JP2005102397A JP2005102397A JP4887646B2 JP 4887646 B2 JP4887646 B2 JP 4887646B2 JP 2005102397 A JP2005102397 A JP 2005102397A JP 2005102397 A JP2005102397 A JP 2005102397A JP 4887646 B2 JP4887646 B2 JP 4887646B2
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electrode
thin film
film transistor
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JP2006286772A (en
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隆一 中村
修 喜納
透 大久保
亮平 松原
守 石崎
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凸版印刷株式会社
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  The present invention relates to a thin film transistor device used for an image display device or the like and a display using the same.

Based on transistor and integrated circuit technology based on semiconductor itself, amorphous silicon (a-Si) and polysilicon (p-Si) thin film transistors (TFTs) are manufactured on a glass substrate. Applied.
In these transistors, the semiconductor layer in the operation region is also formed by photoetching after a silicon film is formed by the CVD method or PVD method, so that the process is complicated and the manufacturing cost is inevitable.
An example of a conventional TFT display device, shown in FIGS. 15 and 16. FIG. 15 is a plan view, and FIG. 16 is a cross-sectional view taken along line DD ′. The outline of the manufacturing method of this display device will be described. First, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1 by metal film formation, photolithography, and etching. Next, the SiNx insulating layer 3 and the semiconductor layer 6 made of amorphous silicon (a-Si) are formed by plasma CVD. A thin n + doping layer 6 'is formed on the top of amorphous silicon (a-Si). Then, the semiconductor layer 6 made of a-Si is patterned into an island shape by photolithography. Subsequently, an ITO (Indium Oxide) film is formed as the pixel electrode 8 and patterned into a predetermined shape by photolithography / etching. Further, a metal film of the source electrode 4 and the drain electrode 5 is formed, patterned by photolithography and etching, and the n + -Si layer in the channel portion is etched.
Thus, the current semiconductor manufacturing process makes full use of a vacuum process and a large number of photo processes, and the apparatus becomes large, so that the manufacturing cost is high.

In recent years, attention has been paid to IC cards, RFID tags, and the like. For these, semiconductor devices are used. Semiconductor devices are becoming more and more multifunctional year by year, but conversely, they are becoming thinner and lighter, and in order to realize them, integration in a limited space and thinning of elements are required.
If the substrate used in the semiconductor device is thinned to reduce the thickness, the element is easily broken. For example, IC cards are stored and carried in card holders and wallets, etc., but they are often bent and twisted by external force in pockets and bags, and are strongly demanded to be flexible and resistant to breakage. It has been. In addition, since it is necessary to perform wiring by wire bonding or the like, there is a problem that the reliability is remarkably lowered, for example, the element itself or wiring is broken by bending or twisting.
Recently, TFTs using oxide semiconductors and organic semiconductors have appeared, and the formation temperature of the semiconductor layer can be lowered from room temperature to about 200 ° C. Therefore, it is possible to use a plastic substrate, and a lightweight and flexible display has been achieved. It is expected to be obtained at a low cost (for example, see Patent Document 1).

In addition, in the conventional semiconductor device, there is a problem that electric charges leak even when the TFT is in an off state. In addition, charge may leak inside the capacitance, but leakage from the TFT is generally about one digit larger. When this leak is severe, a phenomenon called flicker occurs in which the brightness of an image changes at the same cycle as the frame frequency.
By the way, in the TFT having the top gate structure, the leak current is generated at the portion where the edge portion of the semiconductor layer of the TFT intersects with the gate electrode. As a cause of this, the gate electrode causes a short circuit between the source electrode and the drain electrode due to poor insulation of the gate electrode at this edge portion. Alternatively, the periphery of the semiconductor layer may not have a crystal structure due to damage caused by etching or ion doping.

In order to obtain a TFT with a small leakage current, a liquid crystal display including a TFT in which a source electrode and a gate electrode are arranged in a circular shape has been proposed (for example, see Patent Document 2). As shown in FIG. 17 , in the thin film transistor of this liquid crystal display, a gate electrode 502 is disposed so as to surround the source electrode 501, and a drain electrode 503 is disposed outside the gate electrode 502 so as to substantially surround the gate electrode 502. Have a structure. In the figure, reference numeral 504 denotes a semiconductor layer. In other words, electrodes having a substantially similar outer shape of the TFT are arranged concentrically on the semiconductor layer. A gate electrode and an electrode having a shape lacking a part of the ring are arranged so as to surround the outside of the circular electrode. The electrode having a shape lacking a part of the ring is arranged in a layer different from the wiring metal constituting the gate electrode, and the two electrodes are composed of the same wiring metal. As a result, since the edge portion of the semiconductor layer does not exist on the line connecting the source electrode and the drain electrode, the drain electrode and the source electrode are not short-circuited by the gate electrode. It is said that can be reduced. This phenomenon is peculiar to a TFT having a top gate structure when it has a patterned semiconductor layer.

As a technique that eliminates the need for semiconductor patterning, there is a structure in which an operation layer is provided around a source (or drain), a drain (or source) around the source (or drain), and a shielding electrode around the source (or drain) (see, for example, Patent Document 3). . However, when silicon is used as a semiconductor as in Patent Document 2 and Patent Document 3, ion implantation and etching for forming a contact layer are necessary, and even if semiconductor patterning is unnecessary, the corresponding process is as follows. It remained and was still complex. Further, the shielding electrode complicates the structure.
Republished patent WO 98-29261 Japanese Patent Laid-Open No. 08-160469 JP 08-139336 A

The present invention has been made in view of such a state of the art, and an object of the present invention is to provide a thin film transistor device at a low cost by reducing the number of photolithography processes.
Further, although the technique disclosed in Patent Document 2 reduces the leakage current generated at the edge portion crossing the semiconductor layer, the capacitor for stabilizing the image uses the overlapping of wiring and electrodes, and is sufficient. There is a drawback that the function cannot be performed.
It is an object of the present invention to provide a thin film transistor device including a capacitor with little leakage current and effective for stabilizing an image.
It is another object of the present invention to provide a thin film transistor array using the thin film transistor device as described above, thereby providing a light and thin thin film transistor display having a stable image.

In order to solve the above-described problems, the present invention has a gate electrode and a capacitor lower electrode formed on an insulating substrate, and a semiconductor layer is disposed via the gate insulating film formed thereon, the semiconductor A thin film transistor device having a source electrode, a drain electrode and a capacitor upper electrode in contact with a layer, and further having a pixel electrode through an interlayer insulating film formed thereon, wherein the source The electrode has an isolated island pattern, the drain electrode is disposed so as to surround the source electrode, the gate electrode is disposed at a position filling a gap between the source electrode and the drain electrode, and the interlayer insulation is provided. the via hole in the film are connected between the pixel electrode and the source electrode and between the pixel electrode and the capacitor upper electrode, on the capacitor Electrode is an isolated island pattern, and the capacitor lower electrode is formed so as to include large and the capacitor upper electrode than the capacitor upper electrode, becomes the semiconductor layer is formed on the one entire surface of the substrate A thin film transistor device was obtained.
The reason why the semiconductor layer has to be patterned into an island shape is that if the semiconductor layer is not patterned into an island shape, the semiconductor layer formed on the entire surface is connected to another electrode through a portion that is not controlled by the gate. This is because a leak current flows through the. For example, if the semiconductor layer is connected between the source electrode and another electrode except for the portion where the gate electrode exists, a leakage current flows and the potential of the source electrode changes. This causes display deterioration of the display.
On the other hand, by using the thin film transistor device having the structure of the present invention, the leakage current between the source and the drain can be reduced without patterning the semiconductor layer, and the process can be simplified. This is because the gate can completely control the current flowing into the source. Note that the leakage current to be reduced here is a leakage current between the source and the drain due to the connection of the semiconductor at a portion other than on the gate electrode, and is different from the gate leakage in Patent Document 2.
In addition, a capacitor for stabilizing the image is effectively arranged. Therefore, an extremely stable image can be obtained when the image display device is used.
The current flowing into the capacitor upper electrode can be shut out by the capacitor lower electrode.
An inexpensive printing method can be used, and the etching process can be reduced.

In the thin film transistor device of the present invention, it is preferable that the source electrode and the drain electrode are arranged so as to mesh with each other in a comb shape.
The source electrode has a plurality of source-side comb-like portions extending in parallel with being spaced apart from each other, and the drain electrode is separated from the source-side comb-like portion between the adjacent source-side comb-like portions. And a drain-side comb-like portion that extends in parallel with the source-side comb-like portion.
Further, in the plan view arrangement, it is preferable that the drain electrode and the source electrode are arranged at positions separated from the capacitor electrode.
This is necessary to make the source electrode an isolated island pattern.
In the plan view arrangement, the source electrode may be circular, the drain electrode may be a uniform ring shape, and the centers thereof may coincide .

In the thin film transistor device of the present invention, the semiconductor layer is disposed on the gate insulating film, and the source electrode, the drain electrode, and the capacitor upper electrode are disposed on the semiconductor layer. Can

A thin film transistor array according to the present invention includes a plurality of thin film transistor devices according to the present invention arranged in a matrix on an insulating substrate, and the plurality of thin film transistor devices are electrically connected by gate wiring, drain wiring, and capacitor wiring. It is.
In the thin film transistor display of the present invention, the thin film transistor array and the counter substrate are bonded together by a sealing material having a substantially rectangular frame shape in plan view, and a liquid crystal layer is sealed in a region surrounded by the sealing material. is there.
Since the liquid crystal display of the present invention uses the thin film transistor device of the present invention, there is an advantage that an image is stable, and a thin and lightweight display is provided at low cost.

Method of manufacturing a thin film transistor device of the present invention, on an insulating substrate, a gate electrode and a lower capacitor electrode made of a conductive film, forming a gate insulating film thereon, and then the semiconductor layer on the gate insulating film formed, forms the shape of the source electrode, the drain electrode, the capacitor upper electrode thereon, after forming an interlayer insulating film on the its, via holes are formed at predetermined positions of the interlayer insulating film, a conductor in the via hole And a manufacturing method including at least a step of forming a pixel electrode on the interlayer insulating film including the via hole.
In this manufacturing method, the step of forming the source electrode, the drain electrode, and the capacitor upper electrode may include at least a printing step.
Further, the step of forming the conductor layer in the via hole can include at least a printing step.
According to such a manufacturing method, a thin film transistor device including an effective capacitor with little leakage current can be reliably manufactured.
In particular, if a printing method is employed, conductors can be formed only in necessary portions, so that the manufacturing process is greatly reduced, and a large amount can be manufactured at low cost.

By connecting the pixel electrode and the source electrode, and the pixel electrode and the capacitor upper electrode via holes, the TFT portion and the capacitor portion can be designed independently. Further, the off-current can be reduced by surrounding the source electrode with an isolated island pattern and surrounding it with the gate electrode, and surrounding the capacitor upper electrode with the capacitor lower electrode. Since the source electrode is circular, the drain electrode is a uniform-width ring, and the centers coincide with each other, the channel length can be kept uniform, so that stable operation with uniform characteristics and stable leakage current can be ensured.
Moreover, according to the manufacturing method of the present invention, it is possible to provide a thin and light thin film transistor display in a large amount at a low cost by using an inexpensive material.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings used below, the scale is not accurately drawn for easy understanding.
(First embodiment)
A thin film transistor device according to a first embodiment of the present invention is shown in FIGS. FIG. 1 is a plan view showing one pixel region of a thin film transistor array, and FIG. 2 is a cross-sectional view taken along line AA ′.
As shown in FIG. 1, the thin film transistor device 50 according to the first embodiment includes an isolated island-like circular source electrode 4 in the center of the pixel electrode 8, and an annular drain electrode 5 surrounding the source electrode 4. Has been placed. A via hole 9 is provided in the center of the source electrode 4. A gate electrode 2 is formed so as to fill a gap between the source electrode 4 and the drain electrode 5, and a thin film transistor 51 is formed. The source electrode 4 and the gate electrode 2 are connected to the source / drain wiring 5 ′ and the gate wiring 2 ′, respectively.
A capacitor 52 is formed in a portion of the pixel electrode 8 adjacent to the thin film transistor 51. The capacitor 52 has a capacitor upper electrode 11 and a via hole 12 in the center. The capacitor upper electrode 11 is connected to the capacitor wiring 10 ′.
The drain wiring 5 ′, the gate wiring 2 ′ and the capacitor wiring 10 ′ are extended so as to connect a plurality of pixel regions.

  As shown in FIG. 2, in the thin film transistor device 50 according to the first embodiment, the gate electrode 2 and the capacitor lower electrode 10 are formed on the same surface on the insulating substrate 1, and the gate electrode 2 and the capacitor lower electrode 10 are covered with the gate insulating film 3. ing. Further, a semiconductor layer 6 is covered thereon, and a source electrode 4, a drain electrode 5 and a capacitor upper electrode 11 are formed on the same surface. Furthermore, it is covered with an interlayer insulating layer 7, and a pixel electrode 8 is formed thereon. The pixel electrode 8 is connected to the source electrode 4 by a via hole 9 and is connected to the capacitor upper electrode 11 by a via hole 12.

In the thin film transistor device according to the first embodiment, the drain electrode and the source electrode are arranged at positions separated from the capacitor electrode in a plan view arrangement. Therefore, there is an advantage that the transistor thin film 51 portion and the capacitor 52 portion can be designed independently.
In addition, the influence of peripheral electrodes and wiring can be eliminated as much as possible.
Further, in a plan view arrangement, the source electrode is circular, the drain electrode is in a uniform ring shape, and their centers coincide with each other so that the drain electrode surrounds the source electrode. That is, the gate electrode has a shape including the space between the source and drain electrodes.

In the thin film transistor device according to the first embodiment, the semiconductor layer 6 is formed on the entire surface of the substrate. Even if the semiconductor layer 6 is formed on the entire surface of the substrate, the current that flows into the source electrode 4 can be cut off by controlling the potential of the gate electrode 2, so that the source / drain electrodes are kept in an off state. Thus, the same function as that formed by patterning the semiconductor layer can be exhibited.
An advantage of forming the semiconductor layer on the entire surface of the substrate is that an etching step for patterning the electrode can be omitted. This, along with the adoption of the printing method, facilitates process simplification and can greatly contribute to cost reduction.
Here, the gate electrode 2 may have an island shape including not only the gap between the source electrode 4 and the drain electrode 5 but also the source electrode 4, but in order to reduce the parasitic capacitance between the source electrode 4 and the drain electrode 5. Further, it is more desirable that the closed loop substantially corresponds to the gap between the source electrode 4 and the drain electrode 5.

Furthermore, in the thin film transistor device according to the first embodiment, in the planar arrangement, the capacitor is arranged as an isolated pattern at another position adjacent to the transistor, and the capacitor lower electrode is larger than the capacitor upper electrode, and the capacitor It is formed so as to include the upper electrode. For this reason, if the potential of the capacitor lower electrode 10 is set to a potential at which the TFT is turned off, a current that flows into the capacitor upper electrode 11 via the semiconductor layer 6 is blocked by the potential of the capacitor lower electrode 10. The potential of the pixel electrode when the TFT is off can be kept normal.
For this reason, the capacitor is not affected by other electrodes and wirings, and a necessary large capacity can be secured, so that high performance as a capacitor can be exhibited.

  Further, by using screen printing as a process for forming the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, it is not necessary to use photolithography for these patterning. However, depending on the pattern shape, the distance (channel length) between the source electrode 4 and the drain electrode 5 may not be kept constant. For example, in the case of forming a quadrangle as shown in FIG. 5A, rounding of the corners or thickening of the line occurs in the printing process, resulting in a shape as shown in FIG. 5B. Occurs. Therefore, as a result of intensive studies to form the distance (channel length) between the source electrode 4 and the drain electrode 5 with high accuracy, the source electrode 4 is circular and the drain electrode 5 is a uniform ring shape as shown in FIG. In the case where the centers are made coincident with each other, it has been found that the channel length can be kept uniform because the shape as shown in FIG.

  In the thin film transistor device of the present invention, as the insulating substrate, depending on the material of the semiconductor and conductor used, in addition to quartz and glass, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI) ), Polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon and the like can be used. These plastic substrates have the advantage that they can be used as an insulating substrate in the form of a thin film.

The gate electrode, the capacitor lower electrode, the source electrode, the drain electrode, the capacitor upper electrode, and the gate wiring, source wiring, and capacitor wiring that connect them have good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, etc. A metal film or a transparent electrode film such as ITO can be used. These conductive films are formed using a CVD method or a PVD method.
Alternatively, a conductive paste such as an Ag paste or Ni paste can be used. It is desirable to form by printing Ag paste or Ni paste and then firing.
By forming the source electrode, drain electrode, capacitor upper electrode, or the gate wiring, source wiring, and capacitor wiring connecting them using a printing method, film formation and patterning can be performed in a single process, thus simplifying the process. This makes it possible to greatly reduce capital investment.
Further, when screen printing is used as the printing method, the source electrode, drain electrode or capacitor upper electrode can be formed thick, so that when forming a hole for a via hole, the conditions for squeezing that reach the electrode and do not penetrate are wide. There are advantages.

As the gate insulating layer and the interlayer insulating film, inorganic substances such as SiO 2 , Al 2 O 3 , and SiN, and organic substances such as polyvinyl phenol, epoxy, and polyimide can be used. Usually, a film of an inorganic material can be formed using a CVD method or a PVD method, and an organic material can be formed using a spin coating method or a printing method.

As a semiconductor constituting the semiconductor layer, an oxide semiconductor such as InGaZnO-based, InZnO-based, ZnGaO-based, InGaO-based, In 2 O 3 , ZnO, SnO 2 , or a mixture thereof, polythiophene derivative, polyphenylene vinylene derivative, poly Organic semiconductors such as thienylene vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, oligothiophene derivatives, and the like can be used.

The oxide semiconductor layer can be obtained by metal organic chemical vapor deposition, film formation by sputtering or laser ablation, but can also be obtained by baking after applying a raw material.
In the case of using an organic semiconductor film, it can be obtained not only by vapor deposition but also by applying and baking raw materials.
The use of an oxide semiconductor or an organic semiconductor has an advantage that a plastic film can be used as an insulating substrate because the temperature required for forming a semiconductor layer is lowered to room temperature or 200 ° C. or lower.

It is preferable to use a UV-YAG laser beam for forming a hole for a via hole formed in the interlayer insulating film. If a UV-YAG laser beam is used, it is possible to accurately form a minute via hole.
In the via hole, Ag paste or Ni paste can be printed and then pushed in with a doctor blade.
As the pixel electrode, an Al or Ag thin film or an ITO film is preferably used.

  Next, a method for manufacturing the thin film transistor device of the present embodiment will be described with reference to cross-sectional process diagrams of FIGS. For example, a polyethylene naphthalate (PEN) having a thickness of 125 μm is prepared as the insulating substrate 1. After Al is sputtered on the entire surface, a ring-shaped gate electrode 2 and a rectangular capacitor lower electrode 10 are formed at predetermined positions by photolithography and etching. (See FIG. 3A). For example, the thickness of the Al film is 100 nm, the outer diameter of the gate electrode 2 is 160 μm, the inner diameter is 80 μm, and the size of the capacitor lower electrode can be about 225 μm × 375 μm, but the size can be appropriately changed according to the purpose of use. is there. At this time, the gate wiring and the capacitor wiring are also formed at the same time.

Next, SiO 2 or the like to be the gate insulating film 3 and an InGaZnO 4 film to be the semiconductor layer 6 are formed by sputtering (see FIG. 3B). Appropriate thicknesses of about 500 nm and 200 nm are appropriate.

Next, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 are formed by screen printing using Ag paste (see FIG. 3C). The thickness is about 10 μm, the source electrode 4 is a circle having a diameter of 100 μm, the drain electrode 5 is a ring shape having an outer diameter of 200 μm and an inner diameter of about 140 μm, and the capacitor upper electrode 11 is a rectangle of about 200 μm × 350 μm. At this time, the drain wiring is also formed at the same time.
Further, an interlayer insulating film 7 is formed by applying and baking an epoxy resin (see FIG. 3D). The thickness is about 100 μm.

  Next, via holes 9 and 12 having a diameter of about 50 μm are formed in the interlayer insulating film 7 by a UV-YAG laser (FIG. 4E), Ag paste is embedded by a doctor blade, and then fired (FIG. 4F). ). Here, it is preferable to make the surface lightly flattened.

Finally, for example, Al or ITO is vapor-deposited as the pixel electrode 8 and patterned into a square of about 490 μm square by photolithography / etching (FIG. 4G).
In this way, the thin film transistor device of the first embodiment is obtained.

By using such a thin film transistor device, an image display element such as a liquid crystal display can be manufactured. For example, an oxide semiconductor is used for the semiconductor layer 6, a transparent electrode such as ITO is used for the gate electrode 2, the source electrode 4, the drain electrode 5, the capacitor lower electrode 10, and the capacitor upper electrode 11, and SiO 2 is used for the gate insulating layer 3. 7 can also be used to produce a liquid crystal display with a large aperture ratio by using a transparent epoxy resin or polyimide resin. Further, by using an Ag paste for the source electrode 4 and the drain electrode 5, even in the case of a non-transmissive liquid crystal display, it can be used for a guest-host liquid crystal display or the like.

(Second Embodiment)
A thin film transistor device according to a second embodiment of the present invention is shown in FIGS. FIG. 7 is a plan layout view showing one pixel region of the thin film transistor array, and FIG. 8 is a sectional view taken along line BB ′.
The thin film transistor device 60 of the present embodiment is different from the thin film transistor device 50 shown in the first embodiment in the cross-sectional structure. The planar arrangement is the same as that of the thin film transistor device shown in the first embodiment, and the thin film transistor 61 and the capacitor 62 are separately provided adjacent to each other.
As shown in FIG. 8, in the thin film transistor device 60 of this embodiment, the gate electrode 2 and the capacitor lower electrode 10 are formed on the same surface on the insulating substrate 1, and the top is covered with the gate insulating film 3. A source electrode 4, a drain electrode 5 and a capacitor upper electrode 11 are formed on and in contact with the gate insulating film 3, and the entire upper surface thereof is covered with a semiconductor layer 6. Further, the upper surface of the semiconductor layer 6 is covered with an interlayer insulating layer 7, and a pixel electrode 8 is formed thereon. The pixel electrode 8 is connected to the source electrode 4 by a via hole 9 and is connected to the capacitor upper electrode 11 by a via hole 12.
In other words, the semiconductor layer 6 is different from the thin film transistor device of the first embodiment in that the semiconductor layer 6 is on the substrate side of the source electrode 4, the drain electrode 5 and the capacitor upper electrode 11 or on the opposite side of the substrate.
Since the material used and the shape of each pattern are the same as those in the first embodiment, description thereof is omitted.

Next, a method for manufacturing the thin film transistor device of this embodiment will be described with reference to cross-sectional process diagrams of FIGS. The difference from the method of manufacturing the thin film transistor device according to the first embodiment is the order in which the semiconductor layers 6 are formed. Also, some other methods are adopted for forming each layer.
That is, for example, a polyethylene naphthalate (PEN) having a thickness of 125 μm is prepared as the insulating substrate 1, Al is sputtered on the entire surface, and then a ring-shaped gate electrode 2 and a rectangular capacitor lower portion are formed at predetermined positions by photolithography and etching. The electrode 10 is formed (see FIG. 9A). For example, the thickness of the Al film is 100 nm, the outer diameter of the gate electrode 2 is 160 μm, the inner diameter is 80 μm, and the size of the capacitor lower electrode can be about 225 μm × 375 μm. is there. At this time, the gate wiring and the capacitor wiring are also formed at the same time.

Next, a polyvinyl phenol solution to be the gate insulating film 3 is applied by spin coating and baked (see FIG. 9B). A thickness of about 1 μm is suitable.
Next, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 are formed by screen printing and firing (see FIG. 9C). Ag paste or Ni paste can be used for each electrode. The source electrode 4 has a circular shape with a diameter of about 100 μm, the drain electrode 5 has a ring shape with an outer diameter of 200 μm and an inner diameter of about 140 μm, and the capacitor upper electrode 11 has a rectangular shape with a size of about 200 μm × 350 μm. At this time, the drain wiring is also formed at the same time.

Next, a polythiophene solution is applied by spin coating, and the semiconductor layer 6 is formed over the entire surface by baking (FIG. 4D).
Further, an interlayer insulating film 7 is formed by applying and baking an epoxy resin (see FIG. 10E). The thickness is about 100 μm.
Next, via holes 9 and 12 having a diameter of 50 μm are formed in the interlayer insulating film 7 and the semiconductor layer 6 by the UV-YAG laser (see FIG. 10F), and the Ag paste is buried by a doctor blade, followed by firing (see FIG. 10). 10 (g)). Here, it is preferable to make the surface lightly flattened.

Finally, for example, Al or ITO is vapor-deposited as the pixel electrode 8 and patterned into a square of about 490 μm square by photolithography / etching (see FIG. 10H).
In this way, the thin film transistor device 60 of the second embodiment is obtained.

(Third embodiment)
A thin film transistor device according to a third embodiment of the present invention is shown in FIGS. FIG. 11 is a plan layout view showing one pixel region of the thin film transistor array, and FIG. 12 is a cross-sectional view taken along line CC ′.
The thin film transistor device 70 of this embodiment is different from the thin film transistor device 50 shown in the previous first embodiment or the thin film transistor device 60 shown in the second embodiment in its planar arrangement structure. The cross-sectional structure is the same as that of the thin film transistor device 60 shown in the second embodiment.

As shown in FIG. 11, in the thin film transistor device 70 of this embodiment, the source electrode 4 and the drain electrode 5 are arranged in a comb shape at the center of the pixel electrode 8 and fill the gap between the source electrode 4 and the drain electrode 5. Thus, the gate electrode 2 is formed, and the thin film transistor 51 is formed. A via hole 9 is provided in the center of the source electrode 4. The source electrode 4 and the gate electrode 2 are connected to the drain wiring 5 ′ and the gate wiring 2 ′, respectively.
A capacitor 52 is formed in a portion of the pixel electrode 8 adjacent to the thin film transistor 51. The capacitor 52 has a capacitor upper electrode 11 and a via hole 12 in the center. The capacitor upper electrode 11 is connected to the capacitor wiring 10 ′.
The drain wiring 5 ′, the gate wiring 2 ′ and the capacitor wiring 10 ′ are extended so as to connect a plurality of pixel regions.

The sectional structure shown in FIG. 12 is the same as that of the second embodiment shown in FIG.
Moreover, since the manufacturing method can use the manufacturing process of the first embodiment or the second embodiment, only the shape of each pattern is different, the description is omitted.

By configuring the planar arrangement of the thin film transistor device in this manner, a portion where the source electrode and the drain electrode are opposed to each other can be increased, so that a high-performance thin film transistor can be obtained.
Further, in a plan view arrangement, the capacitor is arranged as an isolated pattern at another position adjacent to the transistor, and the capacitor lower electrode is larger than the capacitor upper electrode and includes the capacitor upper electrode. . For this reason, if the potential of the capacitor lower electrode 10 is set to a potential at which the TFT is turned off, a current that flows into the capacitor upper electrode 11 via the semiconductor layer 6 is blocked by the potential of the capacitor lower electrode 10. The potential of the pixel electrode when the TFT is off can be kept normal.
For this reason, the capacitor is not affected by other electrodes and wirings, and a necessary large capacity can be secured, so that high performance as a capacitor can be exhibited.

FIG. 13 is a diagram showing an example of a planar configuration of the thin film transistor array 80 of the present invention. A thin film transistor array 80 according to the present invention includes a plurality of thin film transistor devices 50 according to the first embodiment of the present invention arranged in a matrix on an insulating substrate. -It is electrically connected by the drain wiring 5 'and the capacitor wiring 10'. The arrangement is the same even if the thin film transistor device 50 of the first embodiment replaces the thin film transistor device 60 of the second embodiment.
FIG. 14 is a sectional view showing a liquid crystal display 90 which is a kind of thin film transistor display of the present invention. In the liquid crystal display 90 of the present invention, the thin film transistor array 80, the transparent substrate 13, and the counter substrate 81 including the counter electrode 14 are bonded together by a sealing material (not shown) having a substantially rectangular frame shape in plan view. The liquid crystal layer 15 is sealed in the enclosed region.
Since the liquid crystal display 90 of the present invention uses the thin film transistor device of the present invention, there is an advantage that an image is stable, and a thin and lightweight display is provided at low cost.

Example 1
The thin film transistor device according to the first embodiment having the structure shown in FIGS. 1 and 2 was prepared according to the process diagrams shown in FIGS.
Polyethylene naphthalate (PEN) with a thickness of 125 μm was prepared as the substrate 1, and after sputtering Al, a ring-shaped gate electrode 2 and a rectangular capacitor lower electrode 10 were fabricated by photolithography and etching (FIG. 3A). reference). The thickness was 100 nm, the outer diameter of the gate electrode 2 was 160 μm, the inner diameter was 80 μm, and the size of the capacitor lower electrode 10 was 225 μm × 375 μm. A gate wiring 2 ′ and a capacitor wiring 10 ′ were also produced at the same time.

Next, SiO 2 of the gate insulating film 3 and InGaZnO 4 of the semiconductor layer 6 were formed by sputtering (see FIG. 3B). The thicknesses were 500 nm and 200 nm, respectively.
Here, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 were formed by screen printing (see FIG. 3C). The thickness was 10 μm, the source electrode 4 was a circle having a diameter of 100 μm, the drain electrode 5 was a ring shape having an outer diameter of 200 μm and an inner diameter of 140 μm, and the capacitor upper electrode 11 was a rectangle of 200 μm × 350 μm. The source / drain wiring 5 ′ was also formed at the same time.

Further, an epoxy resin was formed as an interlayer insulating film 7 by coating and baking (see FIG. 3D). The thickness was 100 μm.
Next, a hole having a diameter of 50 μm was formed in the interlayer insulating film 7 by a UV-YAG laser (see FIG. 4E), and Ag paste was embedded and fired by a doctor blade (see FIG. 4F). Here, the surface was lightly shaved and flattened.
Finally, Al was vapor-deposited as the pixel electrode 8 and patterned into a 490 μm square by photolithography etching (see FIG. 4G).

  Using the thin film transistor array using the thin film transistor device thus produced, a guest-host liquid crystal panel having the structure shown in FIG. 14 was produced and confirmed to operate. Since this thin film transistor device exhibits n-channel characteristics, a negative potential is applied to the capacitor wiring to suppress inflow of current.

(Example 2)
A thin film transistor device according to the second embodiment having the structure shown in FIGS. 7 and 8 was produced according to the process charts shown in FIGS.
A 125 μm-thick polyethylene naphthalate (PEN) was prepared as the substrate 1, and after sputtering Al, a ring-shaped gate electrode 2 and a rectangular capacitor lower electrode 10 were fabricated by photolithography and etching (FIG. 9A). )reference). The thickness was 100 nm, the outer diameter of the gate electrode 2 was 160 μm, the inner diameter was 80 μm, and the size of the capacitor lower electrode 10 was 225 μm × 375 μm. A gate wiring 2 ′ and a capacitor wiring 10 ′ were also produced at the same time.

Next, a polyvinylphenol solution was spin-coated and baked to form the gate insulating film 3 (see FIG. 9B). The thickness was 1 μm.
Here, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 were formed by screen printing (see FIG. 9C). The thickness was 10 μm, the source electrode 4 was a circle having a diameter of 100 μm, the drain electrode 5 was a ring shape having an outer diameter of 200 μm and an inner diameter of 140 μm, and the capacitor upper electrode 11 was a rectangle of 200 μm × 350 μm. The source / drain wiring 5 ′ was also formed at the same time.
And the polythiophene solution was apply | coated by spin coating, and it was set as the semiconductor layer 6 by baking (refer FIG.9 (d)).

Furthermore, an epoxy was formed as the interlayer insulating film 7 by coating and baking (see FIG. 10E). The thickness was 100 μm.
Next, a hole having a diameter of 50 μm was formed in the interlayer insulating film 7 by a UV-YAG laser, and an Ag paste was embedded by a doctor blade and baked (see FIGS. 10F and 10G). Here, the surface was lightly shaved and flattened.
Finally, Al was deposited as the pixel electrode 8 and patterned into a 490 μm square by photolithography etching (see FIG. 10H).

Since this thin film transistor device exhibits p-channel characteristics, a positive potential was applied to the capacitor wiring to suppress current inflow.

It is a figure which shows the plane arrangement | positioning of the thin-film transistor apparatus concerning the 1st Embodiment of this invention. It is a figure which shows the cross-sectional structure along line A-A 'of FIG. FIG. 3 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 1. FIG. 4 is a sectional process diagram subsequent to FIG. 3; It is a figure explaining an example of the shape after screen printing. It is a figure explaining the other example of the shape after screen printing. It is a figure which shows the plane arrangement | positioning of the thin-film transistor apparatus concerning the 2nd Embodiment of this invention. FIG. 8 is a diagram showing a cross-sectional structure along line B-B ′ in FIG. 7. FIG. 8 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 7. FIG. 10 is a sectional process diagram subsequent to FIG. 9; It is a figure which shows the planar arrangement | positioning of the thin-film transistor apparatus concerning the 3rd Embodiment of this invention. It is a figure which shows the cross-sectional structure along line C-C 'of FIG. It is a figure explaining the planar structure of the thin-film transistor array of this invention. It is a figure explaining the cross-section of an example of the thin-film transistor display of this invention. It is a figure explaining an example of the plane arrangement of the conventional thin-film transistor. FIG. 16 is a cross-sectional view taken along line D-D ′ of FIG. 15. It is a figure explaining other plane arrangement of the conventional thin-film transistor.

Explanation of symbols

1 .... Insulating substrate, 2 .... Gate electrode, 2 '... Gate wiring, 3 .... Gate insulating film, 4 .... Source Electrode, 5... Drain electrode, 5 '... Source / drain wiring, 6 ... Semiconductor layer, 6' ... Doping layer, 7 ... ... Interlayer insulation film, 8 ... Pixel electrode, 9, 12, ... Via hole, 10 ... Lower capacitor electrode, 10 '... Capacitor wiring, 11... Capacitor upper electrode, 13... Transparent substrate, 14 .. Counter electrode, 15. Thin film transistor arrangement 51... Thin film transistor 52... Capacitor 80. ... Counter substrate 90... Thin film transistor display 501... Source electrode 502... Gate electrode 503. .... Semiconductor layer

Claims (11)

  1. A gate electrode and a capacitor lower electrode formed on an insulating substrate, and a semiconductor layer is disposed via a gate insulating film formed thereon, and a source electrode and a drain electrode are in contact with the semiconductor layer And a capacitor upper electrode, and further having a pixel electrode through an interlayer insulating film formed thereon,
    In a plan view arrangement, the source electrode has an isolated island pattern, the drain electrode is arranged so as to surround the source electrode, and the gate electrode is arranged at a position filling the gap between the source electrode and the drain electrode. Being
    And between the pixel electrode and the source electrode and between the pixel electrode and the capacitor upper electrode by the via hole in the interlayer insulating film ,
    The capacitor upper electrode is an isolated island pattern, and the capacitor lower electrode is formed to be larger than the capacitor upper electrode and include the capacitor upper electrode,
    A thin film transistor device, wherein the semiconductor layer is formed over the entire surface of the substrate .
  2. The thin film transistor device according to claim 1, wherein the source electrode and the drain electrode are arranged so as to mesh with each other in a comb shape .
  3. The source electrode has a plurality of source-side comb-like portions extending in parallel while being separated from each other,
    The drain electrode includes a drain-side comb-like portion that is disposed between the source-side comb-like portions and is spaced apart from the source-side comb-like portion and extends in parallel with the source-side comb-like portion. The thin film transistor device according to claim 1 .
  4. 4. The thin film transistor device according to claim 1 , wherein the drain electrode and the source electrode are arranged at positions separated from the capacitor electrode in a planar view. 5.
  5. 2. The thin film transistor device according to claim 1 , wherein the source electrode is circular, the drain electrode is a uniform ring shape, and the centers thereof coincide with each other in a planar view.
  6. The semiconductor layer is disposed on the gate insulating film;
    6. The thin film transistor device according to claim 1 , wherein the source electrode, the drain electrode, and the capacitor upper electrode are disposed on the semiconductor layer . 7.
  7.   A plurality of thin film transistor devices according to any one of claims 1 to 6 are arranged in a matrix on an insulating substrate, and the plurality of thin film transistor devices are electrically connected by gate wiring, drain wiring, and capacitor wiring. A thin film transistor array characterized by being connected to each other.
  8.   The thin film transistor array according to claim 7 and a counter substrate are bonded together by a sealing material having a substantially rectangular frame shape in plan view, and a liquid crystal layer is sealed in a region surrounded by the sealing material. Thin film transistor display.
  9. On an insulating substrate, a gate electrode and a lower capacitor electrode made of a conductive film, forming a gate insulating film thereon, then forming a semiconductor layer on the gate insulating film, a source electrode thereon, a drain electrode, forms the shape of the capacitor upper electrode, after forming an interlayer insulating film on the its via hole is formed at a predetermined position of the interlayer insulating film, forming a conductive layer in said via hole, further comprising a via hole The method of manufacturing a thin film transistor device according to claim 6 , further comprising: forming a pixel electrode on the interlayer insulating film.
  10.   10. The method of manufacturing a thin film transistor device according to claim 9, wherein the step of forming the source electrode, the drain electrode, and the capacitor upper electrode includes at least a printing step.
  11.   The method for manufacturing a thin film transistor device according to claim 9 or 10, wherein the step of forming a conductor layer in the via hole includes at least a printing step.
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