TWI750098B - 具有導電聚合物襯墊的半導體元件結構及其製備方法 - Google Patents

具有導電聚合物襯墊的半導體元件結構及其製備方法 Download PDF

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TWI750098B
TWI750098B TW110120663A TW110120663A TWI750098B TW I750098 B TWI750098 B TW I750098B TW 110120663 A TW110120663 A TW 110120663A TW 110120663 A TW110120663 A TW 110120663A TW I750098 B TWI750098 B TW I750098B
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conductive
metal layer
conductive polymer
energy
dielectric layer
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TW110120663A
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TW202209616A (zh
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薛宇涵
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南亞科技股份有限公司
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Abstract

本揭露提供一種具有導電聚合物襯墊的半導體元件結構及該半導體元件結構的製備方法。該半導體元件結構具有一第一金屬層以與一第二金屬層，該第一金屬層設置在一半導體基底，該第二金屬層設置在該第一金屬層上。該半導體元件結構還具有一導電結構，設置在該第一金屬層與該第二金屬層之間。該導電結構包括一第一導電通孔與一第一導電聚合物襯墊，該第一導電聚合物襯墊包圍該第一導電通孔。

Description

具有導電聚合物襯墊的半導體元件結構及其製備方法
本申請案主張2020年8月27日申請之美國正式申請案第17/004,889號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件結構及其製備方法。特別是有關於一種具有導電聚合物襯墊之半導體元件結構及其製備方法。
對於許多現代應用，半導體元件是不可或缺的。隨著電子科技的進步，半導體元件的尺寸變得越來越小，於此同時提供較佳的功能以及包括較大的積體電路數量。由於半導體元件的規格小型化，實現不同功能的半導體元件之不同型態與尺寸規模，係整合(integrated)並封裝(packaged)在一單一模組中。再者，許多製造步驟執行於各式不同型態之半導體裝置的整合(integration)。
在一半導體元件中，一內連接結構係用於電性連接在一積體電路之不同層或是相同層中的多個導電元件。然而，隨著半導體元件的按比例縮小，相鄰導電元件之間的間隔係逐漸縮小，其係可縮減內連接結構的製程裕度(process window)。因此，在半導體元件中製造內連接結構則越來越困難。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露的一實施例提供一種半導體元件結構。該半導體元件結構具有一第一金屬層以與一第二金屬層，該第一金屬層設置在一半導體基底，該第二金屬層設置在該第一金屬層上。該半導體元件結構還具有一導電結構，設置在該第一金屬層與該第二金屬層之間。該導電結構包括一第一導電通孔與一第一導電聚合物襯墊，該第一導電聚合物襯墊包圍該第一導電通孔。
在一些實施例中，該第一導電聚合物襯墊包括石墨烯或共軛聚合物。在一些實施例中，該第一導電通孔及該第一導電聚合物襯墊與該第一金屬層的一頂表面直接接觸。在一些實施例中，該半導體元件結構更包括一第一介電層，設置在該第一金屬層與該第二金屬層之間，其中該第一導電聚合物襯墊被該第一介電層包圍，且該第一介電層與該第一金屬層的一頂表面直接接觸。在一些實施例中，該導電結構還包括一第二導電通孔與包圍該第二導電通孔的一第二導電聚合物襯墊，其中該第二導電通孔接合在該第一導電通孔上，該第二導電聚合物襯墊接合在該第一導電通孔聚合物襯墊上，且其中該第二導電聚合物襯墊包括石墨烯或共軛聚合物。
在一些實施例中，該第二導電通孔與該第二導電聚合物襯墊直接接觸該第二金屬層的一底表面，其中該第二元件結構更包括一第二介電層，設置在該第一金屬層與該第二金屬層之間，其中該第二導電聚合物襯墊被該第二介電層包圍，且該第二介電層與該第二金屬層的該底表面直接接觸。在一些實施例中，該半導體元件結構更包括一能量可去除結構，設置在該第一金屬層與該第二金屬層之間且與該導電結構分離，其中一氣隙結構被該能量可去除結構包圍。
本揭露的另一實施例提供一種半導體元件結構。該半導體元件結構包括設置在一半導體基底上的一第一金屬層與設置在該第一金屬層上的一導電結構。該導電結構包括一第一導電通孔，一第二導電通孔，設置在該第一導電通孔上，一第一導電聚合物襯墊，設置在該第一導電通孔的側壁上以及一第二導電聚合物襯墊，設置在該第二導電通孔的側壁上。該第一導電聚合物襯墊與該第二導電聚合物襯墊包括石墨烯或共軛聚合物。該半導體元件結構還包括設置在該導電結構上的一第二金屬層。
在一些實施例中，該第一導電聚合物襯墊與該第二導電聚合物襯墊包括聚(3,4-乙撐二氧噻吩)(PEDOT)或聚苯胺(PANI)。在一些實施例中，該第一導電通孔的側壁與該第二導電通孔的側壁實質上對齊。在一些實施例中，該半導體元件結構還包括第一介電層以及設置在該第一金屬層與該第二金屬層之間的一第二介電層，其中該第一導電聚合物襯墊被該第一介電層包圍，而該第二導電聚合物襯墊被該第二介電層包圍。
在一些實施例中，被第二介電層包圍半導體元件結構更包括一能量可去除結構貫穿該第一介電層與該第二介電層係接觸該第一金屬層與該第二金屬層，其中該能量可去除結構與該導電結構分離。在一些實施例中，該氣隙結構藉由該能量可去除結構與該第一金屬層及該第二金屬層分離。
本揭露的又一實施例提供一種半導體元件結構的製備方法，包括：形成一第一半導體晶粒與形成一第二半導體晶粒。該第一半導體晶粒包括一第一金屬層；該第一金屬層上的一第一導電通孔；以及包圍該第一導電通孔的一第一導電聚合物襯墊。該第二半導體晶粒包括一第二金屬層；該第二金屬層上的一第二導電通孔；以及包圍該第二導電通孔的一第二導電聚合物襯墊。該製備方法還包括：藉由將該第二半導體晶粒接合到該第一半導體晶粒形成電連接該第一金屬層與該第二金屬層的一導電結構。該導電結構由該第一導電通孔，該第一導電聚合物襯墊，該第二導電通孔與該第二導電聚合物襯墊形成。該第一導電通孔與該第二導電通孔接合，且該第一導電聚合物襯墊與該第二導電聚合物襯墊接合。
在一些實施例中，該第一半導體晶粒的形成包括在該第一半導體基底上形成該第一金屬層，以及形成覆蓋該第一金屬層的一第一介電層。該第一半導體晶粒的形成還包括蝕刻該第一介電層以形成曝露該第一金屬層的一部分的一第一開口，以及在該第一開口中形成一第一導電通孔與一第一導電聚合物襯墊以接觸該第一金屬層的該。在一些實施例中，該第一導電聚合物襯墊的形成包括在該第一開口的一底表面與側壁上方沉積一第一導電聚合物材料，以及在該第一開口的該底表面上去除該第一導電聚合物材料的一部分，其中該第一導電聚合物材料的剩餘部分形成一第一導電聚合物襯墊。在一些實施例中，該第一導電聚合物材料包括石墨烯、聚(3,4-乙撐二氧噻吩)(PEDOT)或聚苯胺(PANI)。
在一些實施例中，該第一半導體晶粒的形成還包括蝕刻該第一介電層形成一第二開口，該第二開口係在該第一導電通孔形成之後曝露的該第一金屬層的另外部分，且使用一能量可去除材料填充該第一開口。在一些實施例中，該第二半導體晶粒還包括一第二能量可去除材料，且在該第二半導體晶粒接合到該第一半導體晶粒之後，該第二能量可去除材料與該第一能量可去除材料接合。在一些實施例中，該製備方法還包括在形成該導電結構之後進行一熱處理製程係將該第一能量可去除材料與該第二能量可去除材料轉變為一能量可去除結構，其中一氣隙結構被該能量可去除結構包圍，且該導電結構被該氣隙結構包圍。
本揭露實施例提供之半導體元件結構具有包圍導電通孔的導電聚合物襯墊，且導電通孔做為互連結構。例如，導電通孔設置在第一金屬層上，且導電通孔做為將第一金屬層電連接到形成在導電通孔上的第二金屬層。導電聚合物襯墊被配置以降低半導體元件結構的電阻，減輕積體電路在線路上的電阻電容延遲（RC-Delay）效應。因此，可提高半導體元件結構的操作速度，這顯著提高了整體元件的效能。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包括特定特徵、結構或是特性，然而並非每一實施例必須包括該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
應當理解，以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可相依於製程條件及/或裝置的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可按不同比例任意繪製各種特徵。在附圖中，為簡化起見，可省略一些層/特徵。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1例示本揭露一些實施例之半導體元件結構300a的剖視示意圖。依據一些實施例，如圖1所示，半導體元件結構300a包括一第一半導體晶粒100a與接合在第一半導體晶粒100a上的一第二導體晶粒200a。
在第一半導體晶粒100a中，一介電層103設置在第一半導體基底101上，且一第一金屬層119設置在介電層103中。在一些實施例中，第一金屬層119藉由一阻擋層117與介電層103分離。此外，一介電層121設置在介電層103、阻擋層117與第一金屬層119上。在一些實施例中，一第一導電通孔139設置在介電層103中，且第一導電通孔139藉由第一導電聚合物襯墊135與介電層121分離。
在一些實施例中，第一導電通孔139被第一導電聚合物襯墊135包圍，且第一導電聚合物襯墊135被介電層121包圍。具體地，第一導電聚合物襯墊135設置在第一導電通孔139的一側壁139S上。在一些實施例中，第一導電通孔139及第一導電聚合物襯墊135與第一金屬層119的一頂表面119T直接接觸。
在第二半導體晶粒200a中，一第二導電通孔239接合到第一半導體晶粒100a的第一導電通孔139，且第二導電聚合物襯墊235接合到第一半導體晶粒100a的第一導電聚合物襯墊135。在一些實施例中，第二導電通孔239被第二導電聚合物襯墊235包圍，且第二導電聚合物襯墊235被一介電層221包圍，介電層221接合到第一半導體晶粒100a的介電層121。具體地，第二導電聚合物襯墊235設置在第二導電通孔239的一側壁239S上。
第二半導體晶粒200a還包括設置在介電層221、第二導電通孔239與第二導電聚合物襯墊235上的一第二金屬層219。在一些實施例中，第二導電通孔239與第二導電聚合物襯墊235與第二金屬層219的一底表面219B直接接觸。此外，第二金屬層219設置在一介電層203中，且第二半導體基底201設置在介電層203上。在一些實施例中，第二金屬層219藉由一阻擋層217與介電層203分離。
應當理解，第一半導體晶粒100a的第一導電通孔139與第一導電聚合物襯墊135，以及第二半導體晶粒200a的第二導電通孔239與第二導電聚合物襯墊235形成一導電結構339。在一些實施例中，導電結構339電連接第一半導體晶粒100a的第一金屬層119與第二半導體晶粒200a的第二金屬層219。之後將詳細描述導電結構339。
圖2例示本揭露一些實施例之半導體元件結構300b的剖視示意圖，其係半導體元件結構300a的一替代實施例。由於一致性及清楚的原因，出現在圖1及圖2中的相似元件將具有相同的標記。
類似於半導體元件結構300a，半導體元件結構300b包括一第一半導體晶粒100b與接合在第一半導體晶粒100b上的一第二半導體晶粒200b。不同之處在於半導體元件結構300b包括一能量可去除結構353與能量可去除結構353中包圍的一氣隙結構G。
儘管在圖2的剖視圖中示出能量可去除結構353的六個部分，然而能量可去除結構353的六個部分可在不同的剖視圖中彼此連接。與能量可去除結構353類似，氣隙結構G的六個部分也可在不同的剖視圖中彼此連接。此外，能量可去除結構353與氣隙結構353的部分數量可依據半導體元件結構300b的設計需求進行調整。
在一些實施例中，能量可去除結構353與氣隙結構G設置在第一金屬層119與第二金屬層219之間。此外，能量可去除結構353的下部設置在第一半導體晶粒100b的介電層121中，而能量可去除結構353的上部設置在第二半導體晶粒200b的介電層221中。在一些實施例中，能量可去除結構353與第一金屬層119的該頂表面119T及第二金屬層219的該底表面219B直接接觸。換句話說，氣隙結構G藉由能量可去除結構353與第一金屬層119及第二金屬層219分開。
如上所述，在一些實施例中，氣隙結構G的六個部分彼此連接。因此，導電結構339被氣隙結構G包圍。另外，依據一些實施例，導電結構339與能量可去除結構353分離。之後將詳細描述能量可去除結構353。
圖3例示本揭露一些實施例之半導體元件結構300a之製備方法10的流程示意圖。製備方法10包括步驟S11、S13、S15與S17。步驟S11到S17結合以下附圖詳細說明。
圖4到圖15為依據本揭露一些實施例形成半導體元件結構300a的中間階段的剖視圖。具體來說，圖4至15為依據一些實施例製備第一半導體晶粒100a的順序製程流程的剖視圖。對應的步驟係繪示在如圖3所示之方法10中的步驟S11。
如圖4所示，提供一第一半導體基底101。第一半導體基底101係可一積體電路(IC)晶片的一部分，其包括各種被動與主動微電子元件，例如電阻器、電容器、電感器、二極體、p型場效應電晶體(pFET)、n型場效應電晶體(nFET)、金屬氧化物半導體場效應電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極結型電晶體(BJT)、橫向擴散MOS(LDMOS)電晶體、高壓電晶體、高頻電晶體、鰭式場效應電晶體(FinFET)、其他適合的IC元件或其的組合的元件。
取決於IC製造階段，第一半導體基底101可包括被配置為形成IC特徵(例如，摻雜區、隔離特徵、閘極特徵、源極/汲極特徵、互連特徵、其他特徵或其特徵的組合)的各種材料層(例如，介電層、半導體層及/或導電層)。為清楚起見，簡化第一半導體基底101。應當理解，在第一半導體基底101中可增加額外的特徵，且在其他實施例中可替換、修改或消除下面描述的一些特徵。
仍參考圖4，依據一些實施例，介電層103形成在第一半導體基底101上。在一些實施例中，介電層103由氧化矽、氮化矽、氮氧化矽或其他適用的介電材料製成。此外，介電層103可藉由一化學氣相沉積(CVD)製程、一物理氣相沉積(PVD)製程、一原子層沉積(ALD)製程、一旋塗製程或其他適用的製程形成。
接下來，依據一些實施例，如圖5所示，在介電層103上形成一圖案化的遮罩105。在一些實施例中，以圖案化遮罩105為遮罩蝕刻介電層103，係在介電層103中形成一開口110。開口110可藉由一溼蝕刻製程、一乾蝕刻製程或其組合製程形成。雖然在本實施例中，在形成開口110之後，圖案化遮罩105保留在介電層103上，但可在形成開口110後去除圖案化遮罩105。
接著，依據一些實施例，如圖6所示，形成一阻擋材料113係共形地覆蓋開口110的側壁與底表面，以及圖案化遮罩105的頂表面與側壁(如果在形成開口110之後去除圖案化遮罩105，則可形成阻擋材料113以覆蓋介電層103的頂表面)。在一些實施例中，阻擋材料113由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、鈷鎢(CoW)、其他適用材料或其組合材料製成。此外，阻擋材料113可藉由一CVD製程、一PVD製程、一ALD製程、一金屬有機化學氣相沉積(MOCVD)製程、一濺射製程、一電鍍製程或其他適用的製程形成。
在形成阻擋材料113之後，依據圖7一些實施例所示，在阻擋材料113上共形地形成一第一金屬材料115，且開口110的剩餘部分由第一金屬材料115填充。在一些實施例中，第一金屬材料115由鎢(W)、鋁(Al)、銅(Cu)、鈦(Ti)、鉭(Ta)、其組組合或其他適用的金屬材料製成。此外，第一金屬材料115可藉由一CVD製程、一PVD製程、一ALD製程、一MOCVD製程、一濺射製程、一電鍍製程或其他適用的製程形成。
隨後，依據一些實施例，如圖8所示，對第一金屬材料115與阻擋材料113進行一平坦化製程，係在開口110(見圖5)中形成第一金屬層119與阻擋層117。該平坦化製程可包括一化學機械平坦化(CMP)製程，其去除圖案化遮罩105以及在介電層103上的阻擋材料113與第一金屬材料115的多餘部分。
在一些實施例，阻擋層117覆蓋第一金屬層119的側壁與底表面。在一些實施例中，第一金屬層119的頂表面、阻擋層117的頂表面與介電層103的頂表面彼此實質上共面。在本揭露中，用語“實質上”係指優選至少90%、更優選95%、甚至更優選98%，最優選99%。
接著，依據一些實施例，如圖9所示，在介電層103上形成一介電層121。在一些實施例中，阻擋層117與第一金屬層119被介電層121覆蓋。形成介電層121的部分材料及製程與形成介電層103的材料及製程類似或相同，在此不再重覆。
接著，依據一些實施例，如圖2所示，在介電層121上形成一圖案化遮罩123。在一些實施例中，以圖案化遮罩123為遮罩蝕刻介電層121，以形成貫穿介電層121的一開口130。換句話說，開口130曝露出第一金屬層119的部分頂表面119T。開口130可藉由一溼蝕刻製程、一乾蝕刻製程或其組合製程形成。在形成開口130之後，可去除圖案化遮罩123。
依據一些實施例，如圖11所示，在形成開口130之後，形成一第一導電聚合物材料133以覆蓋開口130的側壁130S與底表面130B以及介電層121的頂表面。在一些實施例中，第一金屬層119的該頂表面119T被開口130曝露的該部分被第一導電聚合物材料133覆蓋。
在一些實施例中，第一導電聚合物材料133包括石墨烯或共軛聚合物，例如聚(3,4-乙烯二氧噻吩)(PEDOT)或聚苯胺(PANI)。在一些實施例中，第一導電聚合物材料133藉由一CVD製程、一PVD製程、一ALD製程、一旋塗製程或其他適合的製程形成。
接著，對第一導電聚合物材料133進行一非等向性蝕刻製程，以垂直方向去除各處等量的第一導電聚合物材料133，而在開口130的側壁130S上留下第一導電聚合物襯墊135，如圖所示在圖。圖12依據一些實施例。在一些實施例中，該蝕刻製程係一乾蝕刻製程。依據一些實施例，在該蝕刻製程之後，介電層121的該頂表面被曝露，且第一金屬層119的頂表面119T被部分地曝露。
依據一些實施例，如圖13所示，在形成第一導電聚合物襯墊135之後，在介電層121上形成一第一導電材料137，且開口130的剩餘部分由第一導電材料137填充。成第一導電材料137的部分材料及製程與形成第一金屬材料115的材料及製程類似或相同，在此不再詳述。在一些實施例中，第一導電聚合物襯墊135被一第一導電材料137覆蓋。
依據一些實施例，如圖14所示，然後，對第一導電材料137進行一平坦化製程係在開口130(見圖12)中形成一第一導電通孔139。該平坦化製程可包括一CMP製程，其去除介電層121上方的第一導電材料137的多餘部分。在該平坦化製程之後，第一導電通孔139的頂表面、第一導電聚合物襯墊135的頂表面與介電層121的頂表面彼此共面，從而獲得第一半導體晶粒100a。在一些實施例中，第一導電通孔139與第一導電聚合物襯墊135設置在第一金屬層119上且與第一金屬層119直接接觸，並且第一導電通孔139被第一導電聚合物襯墊135包圍。
圖15為依據本揭露一些實施例形成半導體元件結構300a的中間階段的剖視圖。具體地，圖15為依據一些實施例的第二半導體晶粒200a的剖視圖。對應的步驟係繪示在如圖3所示之方法10中的步驟S13。
形成第二半導體晶粒201、介電層203、阻擋層217、第二金屬層219、介電層221、第二導電聚合物襯墊235及第二導電通孔239的一些材料與製程類似於，或者分別與形成第一半導體晶粒101、介電層103、阻擋層117、第一金屬層119、介電層121、第一導電聚合物襯墊135及第一導電通孔139的部分相同，在此不再詳述。在形成第二導電通孔239之後，獲得一第二半導體晶粒200a。在一些實施例中，第二導電通孔239及第二導電聚合物襯墊235設置在第二金屬層219上且與第二金屬層219直接接觸，並且第二導電通孔239被第二導電聚合物襯墊235包圍。
接下來，依據一些實施例，如圖1所示，將第二半導體晶粒200a倒置並接合在第一半導體晶粒100a上，並且使介電層221面向介電層121。對應的步驟係繪示在如圖3所示之方法10中的步驟S15。在接合製程之後，獲得一半導體元件結構300a。
在一些實施例中，第二導電通孔239接合在第一導電通孔139上，且第二導電聚合物襯墊235接合在第一導電聚合物襯墊135上。在一些實施例中，第一導電通孔139、第二導電通孔239、第一導電聚合物襯墊135與第二導電聚合物襯墊235形成導電結構339，與第一半導體晶粒100a的第一金屬層119與第二半導體晶粒電連接。在一些實施例中，第一半導體基底101中的電氣元件(未示出)藉由第一金屬層119、導電結構339與第二金屬層219電連接到第二半導體基底201中的電氣元件(未示出)。
圖16至17為依據本揭露一些實施例形成半導體元件結構300b的中間階段的剖視圖。具體來說，圖16至17為依據本揭露一些實施例的製備該第一半導體晶粒100b的順序製程流程的剖視圖。
依據一些實施例，如圖16所示，在形成第一導電通孔139之後(即在圖14的步驟之後)，在介電層121上形成一圖案化遮罩141。在一些實施例中，以圖案化遮罩141為遮罩蝕刻介電層121，係在介電層121中形成一開口結構150。雖然在圖16的剖視圖中示出開口結構150的六個部分，開口結構150的六個部分可在不同的剖視圖中彼此連接。開口結構150可藉由一溼蝕刻製程、一乾蝕刻製程或其組合製程形成。在形成開口結構150之後，可去除圖案化遮罩141。
接著，如圖17所示，依據一些實施例，在開口結構150中形成一第一能量可去除材料153。在一些實施例中，第一能量可去除材料153形成在第一金屬層119與介電層103上。在一些實施例中，第一能量可去除材料153包括一可熱分解材料。在一些其他實施例中，第一能量可去除材料153包括一光子可分解材料、一電子束可分解材料或其他可應用的能量可分解材料。
具體地，在一些實施例中，第一能量可去除材料153包括一基礎材料與一旦曝露於能量源(例如，熱)就實質上被去除的一可分解的致孔劑材料。在一些實施例中，該基礎材料包括：一氫倍半矽氧烷(HSQ)、甲基倍半矽氧烷(MSQ)、多孔聚芳基醚(PAE)、多孔SiLK或多孔氧化矽(SiO2)，且該可分解的致孔劑材料包括一致孔劑有機化合物，係可在隨後的製程中為最初由該第一能量可去除材料所佔據的空間提供孔隙。
第一能量可去除材料153可藉由一沉積製程與一平坦化製程形成。該沉積製程可包括一CVD製程、一PVD製程、一ALD製程、一旋塗製程或其他適合的製程。該平坦化製程係可一CMP製程。在開口結構150被第一能量可去除材料153填充後，即得到修改後的第一半導體晶粒100b。
圖18至圖20為依據本揭露一些實施例形成半導體元件結構300b的中間階段的剖視圖。具體來說，圖18至20為依據本揭露一些實施例的製備該第一半導體晶粒100b的順序製程流程的剖視圖。
參考圖18，依據一些實施例，在形成第二導電通孔239之後(即，在圖15的步驟之後)，在介電層221上形成一圖案化遮罩241。在一些實施例中，以圖案化遮罩241為遮罩蝕刻介電層221，係在介電層221中形成開口結構250。雖然在圖18的剖視圖中開口結構250的六個部分，開口結構250的六個部分可在不同的剖視圖中彼此連接。開口結構250可藉由一溼蝕刻製程、一乾蝕刻製程或其組合製程形成。在形成開口結構250之後，可去除圖案化遮罩241。
接著，依據一些實施例，如圖19所示，在開口結構250中形成一第二能量可去除材料253。在一些實施例中，第二能量可去除材料253形成在第二金屬層219與介電層203上。形成第二能量可去除材料253的部分材料及製程與形成第一能量可去除材料153的材料及製程類似或相同，在此不再詳述。在開口結構250被第二能量可去除材料253填充後，得到一第二半導體晶粒200b。
然後，如圖20所示，依據一些實施例，將修改後的第二半導體晶粒200b倒置並接合在修改後的第一半導體晶粒100b上，使介電層221面向介電層121。在一些實施例中，第二能量可去除材料253接合在第一能量可去除材料153上。類似於半導體元件結構300a，第一導電通孔139、第二導電通孔239、第一導電聚合物襯墊135與第二導電聚合物襯墊235形成一導電結構339電連接修改後的第一半導體晶粒100b的第一金屬層119與第二半導體晶粒200b的第二金屬層219。
隨後，依據一些實施例，如圖20所示，對圖20的結構進行一熱處理製程，將接合的第一能量可去除材料153與第二能量可去除材料253轉變為一能量可去除結構353與一氣隙結構G。對應的步驟係繪示在如圖3所示之方法10中的步驟S17。在一些實施例中，氣隙結構G被能量可去除結構353包圍。
更具體地，在一些實施例中，該熱處理製程係去除第一能量可去除材料153與第二能量可去除材料253的該可分解的致孔劑材料以產生孔隙，且第一能量可去除材料153與第二能量可去除材料253的該基礎材料堆積在第一能量可去除材料153與第二能量可去除材料253所佔空間的邊緣。依據一些實施例，在去除可分解的致孔劑材料後，孔隙被空氣填充，從而在第一能量可去除材料153與第二能量可去除材料253(即能量可去除結構353)的剩餘部分內部獲得氣隙結構G。
在一些實施例中，能量可去除結構353與氣隙結構G形成在第一半導體晶粒100b的第一金屬層119與第二半導體晶粒200b的第二金屬層219之間。在一些實施例中，氣隙結構G藉由一能量可去除結構353與第一金屬層119及第二金屬層219分開。在一些實施例中，能量可去除結構353與第一金屬層119及第二金屬層219直接接觸。在該熱處理製程之後，得到一半導體元件結構300b。
本揭露提供了半導體元件結構300a與300b的實施例。為了降低電阻，半導體元件結構300a與300b包括分別具有包圍導電通孔139、239的導電聚合物襯墊135、235。由於導電聚合物襯墊135、235包括低電阻導電材料，例如石墨烯或共軛聚合物(例如PEDOT、PANI等)，因此可減少電阻電容(RC)延遲。因此，可提高半導體元件結構300a、300b的操作速度，且顯著地提高整體元件效能。
本揭露的一實施例提供一種半導體元件結構。該半導體元件結構具有一第一金屬層以與一第二金屬層，該第一金屬層設置在一半導體基底，該第二金屬層設置在該第一金屬層上。該半導體元件結構還具有一導電結構，設置在該第一金屬層與該第二金屬層之間。該導電結構包括一第一導電通孔與一第一導電聚合物襯墊，該第一導電聚合物襯墊包圍該第一導電通孔。
本揭露的另一實施例提供一種半導體元件結構。該半導體元件結構包括設置在一半導體基底上的一第一金屬層與設置在該第一金屬層上的一導電結構。該導電結構包括一第一導電通孔；設置在該第一導電通孔上的一第二導電通孔；設置在該第一導電通孔的側壁上的一第一導電聚合物襯墊；以及設置在該第二導電通孔的側壁上的一第二導電聚合物襯墊。該第一導電聚合物襯墊與該第二導電聚合物襯墊包括石墨烯或共軛聚合物。該半導體元件結構還包括設置在該導電結構上的一第二金屬層。
本揭露的又一實施例提供一種半導體元件結構的製備方法。該製備方法包括形成一第一半導體晶粒與形成一第二半導體晶粒。該第一半導體晶粒包括一第一金屬層、該第一金屬層上的一第一導電通孔與包圍該第一導電通孔的一第一導電聚合物襯墊。該第二半導體晶粒包括一第二金屬層、該第二金屬層上的一第二導電通孔與包圍該第二導電通孔的一第二導電聚合物襯墊。該製備方法還包括藉由將該第二半導體晶粒接合到該第一半導體晶粒形成電連接該第一金屬層與該第二金屬層的一導電結構。該導電結構由該第一導電通孔、該第一導電聚合物襯墊、該第二導電通孔與該第二導電聚合物襯墊形成。該第一導電通孔與該第二導電通孔接合，且該第一導電聚合物襯墊與該第二導電聚合物襯墊接合。
本揭露的實施例具有一些有利特徵。藉由形成包圍導電通孔的導電聚合物襯墊，可降低導電通孔的電阻，減輕積體電路在線路上的電阻電容延遲（RC-Delay）效應。因此，半導體元件結構的運作速度係以提升，從而顯著地提升整體半導體元件效能。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包括於本申請案之申請專利範圍內。
10:製備方法
100a:第一半導體晶粒
100b:第一半導體晶粒
101:基底
103:介電層
105:圖案化遮罩
110:開口
113:阻擋材料
115:第一金屬材料
117:阻擋層
119:第一金屬層
119T:頂表面
121:介電層
130:開口
130B:底表面
130S:側壁
133:第一導電聚合物材料
135:第一導電聚合物襯墊
137:第一導電材料
139:第一導電通孔
139S:側壁
141:圖案化遮罩
150:開口結構
153:第一能量可去除材料
200a:第二半導體晶粒
200b:第二半導體晶粒
201:基底
203:介電層
217:阻擋層
219:第二金屬層
219B:底表面
221:介電層
235:第二導電聚合物襯墊
239:第二導電通孔
239S:側壁
241:圖案化遮罩
250:開口結構
253:第二能量可去除材料
300a:半導體元件結構
300b:半導體元件結構
339:導電結構
353:能量可去除結構
G:氣隙結構
S11:步驟
S13:步驟
S15:步驟
S17:步驟
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1例示本揭露一些實施例之半導體元件結構的剖視示意圖。 圖2例示本揭露一些實施例之半導體元件結構的剖視示意圖。 圖3例示本揭露一些實施例之半導體元件結構之製備方法的流程示意圖。 圖4例示本揭露一些實施例在形成一第一半導體晶粒期間在一第一半導體基底上形成一介電層的中間階段的剖視示意圖。 圖5例示本揭露一些實施例在形成該第一半導體晶粒期間蝕刻該介電層的中間階段的剖視示意圖。 圖6例示本揭露一些實施例在形成該第一半導體晶粒期間形成一阻擋材料的中間階段的剖視示意圖。 圖7例示本揭露一些實施例在形成該第一半導體晶粒期間形成一第一金屬材料的中間階段的剖視示意圖。 圖8例示本揭露一些實施例在形成該第一半導體晶粒期間值平坦化該第一金屬材料以形成一第一金屬層的中間階段的剖視示意圖。 圖9例示本揭露一些實施例在形成一第一半導體晶粒期間形成一介電層以覆蓋該第一金屬層的中間階段的剖視示意圖。 圖10例示本揭露一些實施例在形成該第一半導體晶粒期間蝕刻該介電層以曝露該第一金屬層的一部分的中間階段的剖視示意圖。 圖11例示本揭露一些實施例在形成該第一半導體晶粒期間形成一第一導電聚合物材料的中間階段的剖視示意圖。 圖12例示本揭露一些實施例在形成該第一半導體晶粒期間值部分蝕刻該第一導電聚合物材料以形成一第一導電聚合物襯墊的中間階段的剖視示意圖。 圖13例示本揭露一些實施例在形成該第一半導體晶粒期間形成一第一導電材料的中間階段的剖視示意圖。 圖14例示本揭露一些實施例在形成該第一半導體晶粒期間值平坦化該第一導電材料以形成一第一導電通孔的中間階段的剖視示意圖。 圖15例示本揭露一些實施例之第二半導體晶粒的剖視示意圖。 圖16例示本揭露一些實施例在形成一第一半導體晶粒期間蝕刻該介電層以形成曝露該第一金屬層的一開口的中間階段的剖視示意圖。 圖17例示本揭露一些實施例在形成該第一半導體晶粒期間藉由一第一能量可去除材料填充該開口的中間階段的剖視示意圖。 圖18例示本揭露一些實施例在形成一第二半導體晶粒期間蝕刻該介電層以形成曝露該第二金屬層的一開口的中間階段的剖視示意圖。 圖19例示本揭露一些實施例在形成該第二半導體晶粒期間藉由一第二能量可去除材料填充該開口的中間階段的剖視示意圖。 圖20例示本揭露一些實施例在形成該第一半導體晶粒期間接合該第二半導體晶粒到該第一半導體晶粒的中間階段的剖視示意圖。
100b:第一半導體晶粒
101:基底
103:介電層
117:阻擋層
119:第一金屬層
121:介電層
135:第一導電聚合物襯墊
139:第一導電通孔
139S:側壁
200b:第二半導體晶粒
201:基底
203:介電層
217:阻擋層
219:第二金屬層
219B:底表面
221:介電層
235:第二導電聚合物襯墊
239:第二導電通孔
239S:側壁
300b:半導體元件結構
339:導電結構
353:能量可去除結構
G:氣隙結構

Claims (17)

  1. 一種半導體元件結構，包括：一第一金屬層，設置在一半導體基底上；一第二金屬層，設置在該第一金屬層上；以及一導電結構，設置在該第一金屬層與該第二金屬層之間，其中該導電結構包括一第一導電通孔與一第一導電聚合物襯墊，該第一導電聚合物襯墊包圍該第一導電通孔；其中該第一導電聚合物襯墊與該第二導電聚合物襯墊包括聚(3,4-乙撐二氧噻吩)(PEDOT)或聚苯胺(PANI)。
  2. 如請求項1所述的半導體元件結構，其中該第一導電通孔與該第一導電聚合物襯墊直接接觸該第一金屬層的一頂表面。
  3. 如請求項1所述的半導體元件結構，還包括：一第一介電層，設置在該第一金屬層與該第二金屬層之間，其中該第一導電聚合物襯墊被該第一介電層包圍，且該第一介電層與該第一金屬層的該頂表面直接接觸。
  4. 如請求項1所述的半導體元件結構，其中該導電結構還包括一第二導電通孔及包圍該第二導電通孔的一第二導電聚合物襯墊，其中該第二導電通孔接合在該第一導電通孔上，該第二導電聚合物襯墊接合在該第一導電聚合物襯墊上，且其中該第二導電聚合物襯墊包括石墨烯或共軛聚合物。
  5. 如請求項4所述的半導體元件結構，其中該第二導電通孔與第二導電聚合物襯墊直接接觸該第二金屬層的一底表面，且其中該半導體元件結構還包括：一第二介電層，設置在該第一金屬層與該第二金屬層之間，其中該第二導電聚合物襯墊被該第二介電層包圍，且該第二介電層直接接觸該第二金屬層的該底表面。
  6. 如請求項1所述的半導體元件結構，還包括：一能量可去除結構，設置在該第一金屬層與該第二金屬層之間且與該導電結構分離，其中一氣隙結構被該能量可去除結構包圍。
  7. 一種半導體元件結構，包括：一第一金屬層，設置在一半導體基底上；一導電結構，設置在該第一金屬層上，其中該導電結構包括：一第一導電通孔；一第二導電通孔，設置在該第一導電通孔上；一第一導電聚合物襯墊，設置在該第一導電通孔側壁上；以及一第二導電聚合物襯墊，設置在該第二導電通孔的側壁上；其中該第一導電聚合物襯墊與該第二導電聚合物襯墊包括石墨烯或共軛聚合物；以及一第二金屬層，設置在導電結構上；其中該第一導電聚合物襯墊與該第二導電聚合物襯墊包括聚(3,4-乙撐二氧 噻吩)(PEDOT)或聚苯胺(PANI)。
  8. 如請求項7所述的半導體元件結構，其中該第一導電通孔的側壁與該第二導電通孔的側壁實質上對齊。
  9. 如請求項7所述的半導體元件結構，還包括：一第一介電層與一第二介電層，設置在該第一金屬層與該第二金屬層之間，其中該第一介電層包圍該第一導電聚合物襯墊，該第二介電層包圍該第二導電聚合物襯墊。
  10. 如請求項9所述的半導體元件結構，還包括：一能量可去除結構貫穿該第一介電層與該第二介電層係接觸該第一金屬層與該第二金屬層，其中該能量可去除結構與該導電結構分離。
  11. 如請求項10所述的半導體元件結構，其中一氣隙結構藉由該能量可去除結構與該第一金屬層與及第二金屬層分離。
  12. 一種半導體元件結構的製備方法，包括：形成一第一半導體晶粒，其中該第一半導體晶粒包括一第一金屬層、該第一金屬層上的一第一導電通孔以及包圍該第一導電通孔的一第一導電聚合物襯墊；形成一第二半導體晶粒，其中該第二半導體晶粒包括一第二金屬層、該第二金屬層上的一第二導電通孔以及包圍該第二導電通孔的一第二 導電聚合物襯墊；以及藉由將該第二半導體晶粒接合到該第一半導體晶粒形成電連接該第一金屬層與該第二金屬層的一導電結構，其中該導電結構由該第一導電通孔、該第一導電聚合物襯墊、該第二導電通孔及該第二導電聚合物襯墊形成；該第一導電通孔與該第二導電通孔接合，以及該第一導電聚合物襯墊與第二導電聚合物襯墊接合；其中該第一導電聚合物襯墊與該第二導電聚合物襯墊包括聚(3,4-乙撐二氧噻吩)(PEDOT)或聚苯胺(PANI)。
  13. 如請求項12所述的製備方法，其中該第一半導體晶粒的形成包括：在一第一半導體基底上形成該第一金屬層；形成覆蓋該第一金屬層的一第一介電層；蝕刻該第一介電層形成一第一開口係曝露該第一金屬層的一部分；以及在該第一開口中形成一第一導電通孔與一第一導電聚合物襯墊以接觸第一金屬層的該部分。
  14. 如請求項13所述的製備方法，其中該第一導電聚合物襯墊的形成包括：在該第一開口的一底表面與側壁上沉積一第一導電聚合物材料；以及去除該第一開口的該底表面上的該第一導電聚合物材料的一部分，其中該第一導電聚合物材料的剩餘部分形成該第一導電聚合物襯墊。
  15. 如請求項13所述的製備方法，其中該第一半導體晶粒的形成還包括：在形成該第一導電通孔後，蝕刻該第一介電層係形成曝露該第一金屬層的另部分的一第二開口；以及使用一第一能量可去除材料填充該第二開口。
  16. 如請求項15所述的製備方法，其中該第二半導體晶粒還包括一第二能量可去除材料，在該第二半導體晶粒接合該第一半導體晶粒之後，該第二能量可去除材料與該第一能量可去除材料接合。
  17. 如請求項16所述的製備方法，還包括：形成該導電結構後，執行一熱處理製程係將該第一能量可去除材料與該第二能量可去除材料轉變為一能量可去除結構，其中一氣隙結構被該能量可去除結構包圍，而該導電結構被該能量可去除結構包圍。
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