TWI749803B - 高電壓電晶體結構與其製作方法 - Google Patents

高電壓電晶體結構與其製作方法 Download PDF

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TWI749803B
TWI749803B TW109135067A TW109135067A TWI749803B TW I749803 B TWI749803 B TW I749803B TW 109135067 A TW109135067 A TW 109135067A TW 109135067 A TW109135067 A TW 109135067A TW I749803 B TWI749803 B TW I749803B
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gate electrode
polysilicon
input
polysilicon gate
layer
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TW109135067A
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TW202118005A (zh
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林孟漢
黃文鐸
才永軒
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台灣積體電路製造股份有限公司
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Abstract

本公開描述了一種用於形成(i)具有多晶矽閘極電極和氧化矽閘極介電質整合的輸入/輸出(I/O)鰭式場效應電晶體以及(ii)具有金屬閘極電極和高介電常數閘極介電質的非輸入/輸出場效應電晶體的方法。此方法包括在半導體基板的第一區域上沉積氧化矽層以及在半導體基板的第二區域上沉積高介電常數介電層；在氧化矽和高介電常數介電層上沉積多晶矽層；圖案化多晶矽層，以在氧化矽層上形成第一多晶矽閘極電極結構，並在高介電常數介電層上形成第二多晶矽閘極電極結構，其中第一多晶矽閘極電極結構比第二多晶矽閘極電極結構寬並且比氧化矽層窄。此方法還包括用金屬閘極電極結構代替第二多晶矽閘極電極結構。

Description

高電壓電晶體結構與其製作方法
本公開是關於一種電晶體結構與其製作方法。
隨著半導體技術的進步，對更高的儲存容量、更快的處理系統、更高的性能以及更低的成本的需求不斷地增加。為了滿足這些需求，半導體工業持續地使半導體裝置(例如，金屬氧化物半導體場效應電晶體(metal oxide semiconductor field effect transistors,MOSFETs)，包括平面金屬氧化物半導體場效應電晶體和鰭式場效應電晶體(fin field effect transistors,finFETs))的尺寸微縮。這種尺寸微縮增加了半導體製程的複雜性。
根據本公開的部分實施例，一種電晶體結構包括形成在半導體基板的第一區域上的第一電晶體，其中此第一電晶體包括閘極介電質、多晶矽閘極電極和第一間隔物結構，多晶矽閘極電極設置在閘極介電質上，其中閘極介電質比多晶矽閘極電極長。第一間隔物結構鄰接多晶矽閘極 電極的側壁，使得第一間隔物結構的側壁與閘極介電質的側壁對齊。此電晶體結構還包括形成在半導體基板的第二區域上的第二電晶體，其中第二電晶體比第一電晶體窄並且包括高介電常數閘極介電質、金屬閘極電極和第二間隔物結構。金屬閘極電極設置在高介電常數閘極介電質上並與之對齊，以使金屬閘極電極的側壁與高介電常數閘極介電質的側壁對齊。第二間隔物結構鄰接金屬閘極電極和高介電常數閘極介電質的側壁。
根據本公開的部分實施例，一種電晶體結構的製作方法包括在半導體基板的第一區域上沉積氧化矽層；在半導體基板的第二區域上沉積比氧化矽層薄的高介電常數介電層；在氧化矽層和高介電常數介電層上沉積多晶矽層；對多晶矽層進行圖案化，以在氧化矽層上形成第一多晶矽閘極電極結構，並在高介電常數介電層上形成第二多晶矽閘極電極結構，其中第一多晶矽閘極電極結構比第二多晶矽閘極電極結構寬並且比氧化矽層窄。此方法還包括在第一多晶矽閘極電極結構的側壁上形成第一間隔物，以使第一間隔物的外側壁與氧化矽層的側壁對齊；在第二多晶矽閘極電極結構和高介電常數介電層的側壁上形成第二間隔物；用金屬閘極電極結構代替第二多晶矽閘極電極結構。
根據本公開的部分實施例，一種電晶體結構包括形成在半導體基板的第一區域上的第一電晶體，其中此第一電晶體包括氧化矽閘極介電質、多晶矽閘極電極與第一間隔物結構。多晶矽閘極電極設置在氧化矽閘極介電質上， 並且此多晶矽閘極電極的側壁邊緣與氧化矽閘極介電質的側壁邊緣不對齊。第一間隔物結構的內側壁鄰接多晶矽閘極電極的側壁邊緣。此電晶體結構還包括形成在半導體基板的第二區域上的第二電晶體，其中第二電晶體比第一電晶體窄並且包括高介電常數閘極介電質、金屬閘極電極和第二間隔物結構。金屬閘極電極設置在高介電常數閘極介電質上，以使金屬閘極電極的側壁邊緣與高介電常數閘極介電質的側壁邊緣對齊。第二間隔物結構鄰接金屬閘極電極和高介電常數閘極介電質的側壁邊緣。
100:輸入/輸出場效應電晶體結構
105:半導體基板
110:基板隔離區域
115:介電層
120:閘極介電層
125:閘極電極層
125L:長度
125T:厚度
125W:寬度
130:間隔物結構
135:矽化物層
140:源極/汲極區域
145:矽化物層
150:蝕刻停止層
200:輸入/輸出鰭式場效應電晶體結構
205:半導體鰭片
260:間隔物結構
300:方法
305:操作
310:操作
315:操作
320:操作
325:操作
330:操作
335:操作
400:輸入/輸出基板區域
405:非輸入/輸出基板區域
410:高介電常數閘極介電層
500:輸入/輸出場效應電晶體閘極電極結構
500H:高度
500L:長度
505:非輸入/輸出場效應電晶體閘極電極結構
505H:高度
515:氧化物層
520:氮化物層
600:輕摻雜區域
610:重摻雜區域
905:金屬閘極電極
910:非輸入/輸出場效應電晶體
915:輸入/輸出場效應電晶體
AB:切割線
C:中心
E:邊緣
X:軸
Y:軸
Z:軸
當結合附圖閱讀時，根據以下詳細描述可以最好地理解本公開的各方面。應理解，根據行業中的慣例，各種特徵未按比例繪製。實際上，為了清楚起見，各種特徵的尺寸可以任意地增加或減小。
第1圖是根據部分實施例之具有多晶矽閘極電極和氧化矽閘極介電質的輸入/輸出平面場效應電晶體(field effect transistor,FET)結構的等角視圖。
第2圖是根據部分實施例之具有多晶矽閘極電極和氧化矽閘極介電質的兩個輸入/輸出鰭式場效應電晶體結構的等角視圖。
第3圖是流程圖，描述根據部分實施例之在基板的輸入/輸出區域中形成具有多晶矽閘極電極和氧化矽閘極介電質的 輸入/輸出場效應電晶體結構和在基板的非輸入/輸出區域中形成具有金屬閘極電極和高介電常數閘極介電質的非輸入/輸出場效應電晶體結構方法。
第4圖至第10圖是描述根據部分實施例之在基板的輸入/輸出區域中具有多晶矽閘極電極和氧化矽閘極介電質的輸入/輸出場效應電晶體結構以及在基板的非輸入/輸出區域中具有金屬閘極電極和高介電常數閘極介電質的非輸入/輸出場效應電晶體結構之製程的橫截面圖。
第11圖是根據部分實施例之在化學機械平坦化(chemical mechanical polishing,CMP)製程之後用於輸入/輸出場效應電晶體結構的多晶矽閘極電極的等角視圖。
以下公開提供了用於實現所提供主題之不同特徵的不同實施例或示例。以下描述元件和配置的特定示例以簡化本公開。當然，這些僅僅是示例，而無意於進行限制。例如，在下面的描述中，在第二特徵上形成第一特徵可以包括其中第一特徵和第二特徵以直接接觸形成的實施例，並且還包括可以在第一特徵和第二特徵之間形成附加特徵，使得第一特徵和第二特徵不直接接觸的實施例。
此外，本文中可以使用諸如「在…下面」、「在…下方」、「低於」、「在…上面」、「在…上方」等之類 的空間相對術語，以便於描述一個元件或特徵與如圖所示的另一個或多個元件或特徵的關係。除了在圖中描述的方位之外，空間相對術語還意圖涵蓋裝置在使用或操作中的不同方位。裝置可以以其他方式定向(旋轉90度或以其他定向)，並且本文中使用的空間相對描述語可以同樣相應地解釋。
如本文所用，術語「名義上」是指在元件或製程的設計階段中，設定用於元件或製程操作的特性或參數的期望值或目標值以及高於和/或低於期望值的數值範圍。數值範圍通常是由於製程或公差的微小變化所致。
在部分實施例中，術語「大約」和「實質上」可以指示給定數量的值，此給定數量的值在此值的5%之內變化(例如，此值的±1%、±2%、±3%、±4%、±5%)。
如本公開所用，術語「垂直」是指名義上垂直於基板的表面。
積體電路(integrated circuits,IC)可以包括例如輸入/輸出(I/O)場效應電晶體(field effect transistors,FETs)和非輸入/輸出場效應電晶體(non-I/O FETs)之半導體結構的組合。輸入/輸出場效應電晶體可以是形成在積體電路之外圍區域(被稱為「輸入/輸出區域」或「高壓區域」)中例如電路的一部分，而非輸入/輸出裝置可以是形成在積體電路之「核心」區域中的「核心」電路(被稱為邏輯電路或記憶體電路)的一部分。可以將輸入/輸出裝置配置為接收積體電路的輸入/輸 出電壓或電流，並承受比非輸入/輸出裝置更高的電壓或電流。例如，可以將輸入/輸出裝置配置為處理來自外部電源(例如，鋰離子電池)的輸入電壓，輸出大約5伏特(V)的電壓。此外，這些輸入/輸出裝置可以是輸出大約1伏特的配電電壓(其可以隨後分配給非輸入/輸出場效應電晶體)的變壓器電路的一部分。另一方面，非輸入/輸出裝置未配置為直接處理輸入/輸出電壓/電流，並且它們被稱為核心裝置、邏輯裝置和/或記憶體裝置。例如，非輸入/輸出裝置可以包括形成邏輯閘極的場效應電晶體(例如，NAND、NOR、反相器或其組合)。此外，非輸入/輸出裝置可以包括記憶體裝置(例如，靜態隨機存取記憶體(static random-access memory,SRAM)裝置、動態隨機存取記憶體(dynamic random-access memory,DRAM)裝置、其他類型的記憶體裝置或其組合)。
為了提高製造效率，期望在同一個基板上同時形成輸入/輸出和非輸入/輸出場效應電晶體。在多個技術節點中，已在非輸入/輸出場效應電晶體的閘極堆疊製造中使用金屬閘極材料和高介電常數(high-k)介電材料(例如，k值大於3.9)，以改善裝置性能並促進裝置的尺寸微縮。為了使輸入/輸出和非輸入/輸出場效應電晶體之間的製造過程更簡化、更協調和更有效率，金屬閘極和高介電常數介電材料也已用於輸入/輸出場效應電晶體的閘極堆疊。
因為輸入/輸出和非輸入/輸出場效應電晶體被配置為在不同的電壓下運作(例如，分別在大約5伏特和大 約1伏特下)，所以它們的結構可能會因其物理尺寸而異。例如，與非輸入/輸出場效應電晶體的閘極堆疊(其具有較小的尺寸)相比，輸入/輸出場效應電晶體的閘極堆疊可以具有較大的表面積(例如，大於約1平方微米(μm2))並包括較厚的閘極氧化物。由於輸入/輸出場效應電晶體的尺寸較大，如果閘極電極的材料是金屬或含金屬的堆疊，則這些裝置的化學機械平坦化可能會具有挑戰性。例如，如此大的特徵的平面化會導致輸入/輸出場效應電晶體的閘極電極腐蝕或「凹陷(dishing)」。因此，輸入/輸出場效應電晶體的閘極電極的厚度在整個裝置上可能會不均勻，這可能會降低輸入/輸出場效應電晶體的性能和可靠性。
本公開的實施例針對一種用於形成具有金屬閘極電極和高介電常數閘極介電質的非輸入/輸出場效應電晶體並同時形成具有多晶矽閘極電極和氧化矽閘極介電質的輸入/輸出場效應電晶體的方法。在部分實施例中，多晶矽閘極電極為化學機械平坦化凹陷提供恢復力，並因此容許在製程中形成更大的輸入/輸出場效應電晶體(例如，等於或大於約10μm2)。在部分實施例中，本文描述的方法可以應用於平面和非平面電晶體(例如，鰭式場效應電晶體)。
根據部分實施例，第1圖是多晶矽輸入/輸出場效應電晶體結構100的等軸視圖。多晶矽輸入/輸出場效應電晶體結構100形成在基板隔離區域110之間的半導體基板 105上。在部分實施例中，每個基板隔離區域110可以是淺溝槽隔離(shallow trench isolation,STI)區域，其包括諸如二氧化矽(SiO2)或低k介電材料(例如，k值小於大約3.9)的介電材料。基板隔離區域110形成在半導體基板105中，以在半導體基板105的摻雜區域之間提供電隔離。為簡單起見，第1圖中未繪示半導體基板105的摻雜區域。根據部分實施例，半導體基板105可以包括(i)矽，(ii)化合物半導體，例如，砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)和/或銻化銦(InSb)，(iii)合金半導體，包括矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷銦化鋁(AlInAs)、砷鎵化鋁(AlGaAs)、砷銦化鎵(GaInAs)、磷銦化鎵(GaInP)和/或磷砷銦化鎵(GaInAsP)，或(iv)其組合。出於示例的目的，將在本公開中使用晶體矽作為半導體基板105。基於本文的公開內容，可以使用如上所述之其他材料。這些材料皆在本公開的精神和範圍內。
多晶矽輸入/輸出場效應電晶體結構100透過介電層115與相鄰的裝置或結構(在第1圖中未繪示)橫向地隔離。在部分實施例中，介電層115可以是層間介電質(例如，二氧化矽(SiO2)、摻雜的二氧化矽(SiO2)或介電常數等於或小於約3.9(例如，約3.6、約3.3等)的任何其他合適的介電材料)。作為示例而非限制，如第1圖所示，介電層115圍繞多晶矽輸入/輸出場效應電晶體結構100的側表面。
在部分實施例中，多晶矽輸入/輸出場效應電晶體結構100包括閘極堆疊，此閘極堆疊具有形成在半導體基板105上的閘極介電層120和設置在閘極介電層120上的多晶矽閘極電極層125。作為示例而非限制，閘極介電層120可以包括氧化矽(SiO2)，其可以在半導體基板105上(例如，以接觸的方式)熱生長。作為示例而非限制，閘極介電層120的厚度可以在大約20埃(Å)和大約500埃之間，並且可以實質上比非輸入/輸出場效應電晶體的閘極介電層更厚(例如，更厚約2倍至約20倍)。閘極介電層120允許多晶矽輸入/輸出場效應電晶體結構100在高閘極電壓(例如，約5伏特)下操作。在部分實施例中，多晶矽閘極電極層125的厚度125T為約10奈米(nm)至約300nm，寬度125W為約0.1微米(μm)至約100μm，長度125L為約0.05μm至約50μm。根據部分實施例，多晶矽閘極電極層125的表面積(例如，125W×125L)大於約1μm2。在部分實施例中，多晶矽閘極電極層125的表面積在約1μm2至約10μm2之間。在部分實施例中，多晶矽閘極電極層125的表面積大於約10μm2(例如，約20μm2)。
在部分實施例中，即使閘極電極的表面積大於約10μm2，多晶矽輸入/輸出場效應電晶體結構100的多晶矽閘極電極層125也能提供由閘極電極化學機械平坦化製程引起之凹陷的恢復力。換句話說，在閘極化學機械平坦化製程之後，多晶矽輸入/輸出場效應電晶體結構100的厚 度125T在長度125L和寬度125W上可以實質上均勻。根據部分實施例，在閘極化學機械平坦化製程之後，厚度125T在長度125L和寬度125W上的變化可以為約10%或更小。對於約10nm的厚度125T，厚度變化可以為約1nm。參考第11圖，根據部分實施例，(例如，在化學機械平坦化後)多晶矽輸入/輸出場效應電晶體結構100之平坦化的多晶矽閘極電極層125的中心至邊緣的厚度比(center to edge thickness ratio,C/E)在約0.9與約1之間。即，沿x-y平面，多晶矽輸入/輸出場效應電晶體結構100之平坦化的多晶矽閘極電極層125的中心(C)厚度為邊緣(E)厚度的大約90%至大約100%之間。
此外，第1圖所示的多晶矽輸入/輸出場效應電晶體結構100在沿著多晶矽閘極電極層125的寬度125W的側壁上包括間隔物結構130。作為示例而非限制，間隔物結構130可以包括氮化物(例如，氮化矽)，並且可以進一步包括一層或多層以形成間隔物堆疊。
在部分實施例中，多晶矽閘極電極層125包括矽化物部分，其中可以在其上形成接觸結構(第1圖中未繪示)。在部分實施例中，多晶矽閘極電極層125的矽化部分是覆層矽化物層135，其包括矽化鈦、矽化鎳、矽化鈷或可以在多晶矽閘極電極層125上形成或生長之任何合適的矽化物材料。在部分實施例中，對多晶矽閘極電極層125進行摻雜以使其可導電。作為示例而非限制，多晶矽閘極 電極層125的摻雜劑濃度可以在大約1013原子/立方公分(cm3)和大約1019原子/cm3之間，並且摻雜劑種類可以是n型(例如，磷、砷、銻)或p型(例如，硼、銦和鎵)。
另外，多晶矽輸入/輸出場效應電晶體結構100可以包括源極/汲極區域140和矽化物層145。在部分實施例中，蝕刻停止層150設置在基板隔離區域110、半導體基板105、矽化物層145、閘極介電層120和間隔物結構130的側壁表面上，如第1圖所示。
作為示例而非限制，第1圖所示的多晶矽輸入/輸出場效應電晶體結構100是平面場效應電晶體結構。然而，這不是限制性的，並且根據本公開描述之實施例的多晶矽輸入/輸出場效應電晶體結構可以形成在一個或多個半導體鰭片上以形成一個或多個非平面的多晶矽輸入/輸出場效應電晶體結構(例如，多晶矽輸入/輸出鰭式場效應電晶體結構)。例如，第2圖是分別形成在半導體鰭片205上的兩個多晶矽輸入/輸出鰭式場效應電晶體結構200的等角視圖。分別在第1圖和第2圖中繪示的多晶矽輸入/輸出場效應電晶體結構100和多晶矽輸入/輸出鰭式場效應電晶體結構200共享相似的結構元件(例如，閘極介電層120、多晶矽閘極電極層125、間隔物結構130、矽化物層135和蝕刻停止層150)。此外，在多晶矽輸入/輸出場效應電晶體結構100和多晶矽輸入/輸出鰭式場效應電晶體結構200中的多晶矽閘極電極層125的表面積可以實質上相等 (例如，大於約1μm2，在約1μm2和約10μm2之間，或大於約10μm2(例如，約20μm2))。在部分實施例中，閘極介電層120的厚度實質上比非輸入/輸出場效應電晶體和非輸入/輸出鰭式場效應電晶體中各自的閘極介電層厚。
在部分實施例中，第1圖所示的多晶矽輸入/輸出場效應電晶體結構100可以與非輸入/輸出場效應電晶體結構同時地形成在同一個半導體基板上。同樣地，第2圖所示的多晶矽輸入/輸出鰭式場效應電晶體結構200可以與非輸入/輸出鰭式場效應電晶體結構同時地形成在同一個半導體基板上。
第3圖是方法300的流程圖，此方法300描述了形成具有多晶矽閘極電極和氧化矽閘極介電質的平面和非平面多晶矽輸入/輸出場效應電晶體結構以及同時形成具有金屬閘極電極和高介電常數閘極介電質的非輸入/輸出場效應電晶體結構的過程。可以在方法300的各種操作之間執行其他的製造操作，並且僅為了清楚起見可以將其省略。出於示例的目的，使用方法300形成的多晶矽輸入/輸出場效應電晶體結構將在本公開中被描述為平面結構(例如，多晶矽輸入/輸出場效應電晶體結構100)。基於本公開，可以使用方法300來形成非平面輸入/輸出多晶矽場效應電晶體結構(例如，多晶矽輸入/輸出鰭式場效應電晶體結構200，如上所示，其共享類似的結構元件和表面積)。這些非平面輸入/輸出多晶矽場效應電晶體結構(例 如，輸入/輸出多晶矽鰭式場效應電晶體結構)皆在本公開的精神和範圍內。方法300的描述將參考第4圖至第9圖。
參考第3圖和第4圖，方法300由操作305開始，其為在半導體基板的第一區域中形成閘極介電層並且在半導體基板的第二區域中形成高介電常數閘極介電層的過程。在部分實施例中，半導體基板的第一區域對應於積體電路中形成輸入/輸出裝置的區域(例如，半導體基板的輸入/輸出區域)。半導體基板的第二區域對應於積體電路中形成非輸入/輸出裝置的區域(例如，半導體基板的非輸入/輸出區域)。
作為示例而非限制，參考第4圖，閘極介電層120形成在輸入/輸出基板區域400中(其中閘極介電層120對應於操作305的閘極介電層)，而高介電常數閘極介電層410形成在半導體基板105的非輸入/輸出基板區域405中(其中高介電常數閘極介電層410對應於操作305的高介電常數閘極介電層)。由於閘極介電層120用於輸入/輸出場效應電晶體(而不是非輸入/輸出場效應電晶體)，因此閘極介電層120選擇性地形成在半導體基板105的輸入/輸出基板區域400中，如第4圖所示。在部分實施例中，第4圖的輸入/輸出基板區域400是跨越如第1圖所示的切割線AB之半導體基板105的橫截面圖。根據部分實施例，輸入/輸出基板區域400對應於積體電路的輸入/輸出區域，並且非輸入/輸出基板區域405對應於積體電路的非輸入/輸出區域(例如，核心或邏輯區域)。在部分實 施例中，輸入/輸出基板區域400和非輸入/輸出基板區域405不是相鄰的區域(例如，輸入/輸出基板區域400和非輸入/輸出基板區域405是間隔開的)。在輸入/輸出基板區域400中形成閘極介電層120的選擇性製程可以包括首先在輸入/輸出和非輸入/輸出基板區域上形成閘極介電層120，然後圖案化閘極介電層120以從非輸入/輸出基板區域405中去除閘極介電層120。作為示例而非限制，閘極介電層120可以在大約20埃至大約500埃之間的厚度範圍內熱生長或沉積。
作為示例而非限制，高介電常數閘極介電層410的介電常數(k值)大於約3.9(例如，約4.0、約10、約20、約30等)。在部分實施例中，高介電常數閘極介電層410是金屬氧化物層，其毯覆式沉積在輸入/輸出和非輸入/輸出基板區域上，然後被圖案化，從而如第4圖所示從輸入/輸出基板區域400中去除。在部分實施例中，高介電常數閘極介電層410的厚度在約5埃至約20埃的範圍內。在部分實施例中，在非輸入/輸出基板區域405中的高介電常數閘極介電層410和半導體基板105之間形成界面閘極介電層(在第4圖中未繪示)。此界面閘極介電層可以包括例如氧化矽或氮氧化矽。在部分實施例中，高介電常數閘極介電層410和界面閘極介電層在非輸入/輸出基板區域405中形成閘極介電質堆疊。
參考第3圖，方法300繼續操作310，其為在閘極介電層120和高介電常數閘極介電層410上沉積並圖案 化多晶矽閘極電極層以分別形成用於輸入/輸出和非輸入/輸出場效應電晶體的多晶矽閘極電極結構的過程。參考第5圖，可以在半導體基板105上毯覆式沉積在約100埃至約3000埃之間的厚度的多晶矽閘極電極層125，然後對其進行圖案化以在輸入/輸出基板區域400中形成輸入/輸出場效應電晶體閘極電極結構500並同時在非輸入/輸出基板區域405中形成非輸入/輸出場效應電晶體閘極電極結構505。在部分實施例中，使用單次圖案化操作形成輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505。在部分實施例中，在操作310期間，可以藉助於硬遮罩堆疊來執行多晶矽閘極電極層125的圖案化，此硬遮罩堆疊包括底部氧化物層515(例如，氧化矽層)和頂部氮化物層520(例如，氮化矽層)。氧化物層515和氮化物層520可以在前述圖案化製程的蝕刻操作期間保護多晶矽閘極電極層125。
在部分實施例中，形成在輸入/輸出基板區域400中的輸入/輸出場效應電晶體閘極電極結構500的長度大於形成在非輸入/輸出基板區域405中的非輸入/輸出場效應電晶體閘極電極結構505的長度。例如，輸入/輸出場效應電晶體閘極電極結構500的長度500L(例如，閘極長度)在大約0.05μm至大約50μm的範圍內，而非輸入/輸出場效應電晶體閘極電極結構505的長度為(例如，閘極長度)在約5nm至約50nm之間。在部分實施例中，若輸入/輸出場效應電晶體閘極電極結構500的長度500L 小於約50nm，則可能會不利地影響輸入/輸出場效應電晶體的性能。例如，若輸入/輸出場效應電晶體之輸入/輸出場效應電晶體閘極電極結構500的長度小於約0.05μm，則可能會具有高電流密度，然而其漏電流的量卻是不可接受的。另一方面，若輸入/輸出場效應電晶體閘極電極結構500的長度500L大於約50μm，則輸入/輸出場效應電晶體閘極電極結構500會具有減小其他積體電路元件的可用空間的覆蓋區(例如，表面積)。換句話說，在輸入/輸出場效應電晶體閘極電極結構500的尺寸和用於其他積體電路元件的可用空間之間存在折衷。
在部分實施例中，在圖案化之後，輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505在沿y軸的方向上可具有實質上相等的寬度(第5圖中未繪示)，並且在沿z軸的方向上分別具有高度500H和505H。然而，由於閘極介電層120和高介電常數閘極介電層410之間的厚度差異，在隨後之總體的平坦化操作中，高度500H將變得比高度505H矮。
在部分實施例中，在上述之多晶矽閘極電極層125的圖案化製程期間，在輸入/輸出基板區域400中的閘極介電層120保留在半導體基板105上而未被去除。另一方面，高介電常數閘極介電層410與多晶矽閘極電極層125一起被圖案化。因此，輸入/輸出場效應電晶體閘極電極結構500的長度500L比閘極介電層120的長度短，而非輸入/輸出場效應電晶體閘極電極結構505的長度實質上等於高 介電常數閘極介電層410的長度，如第5圖所示。
根據部分實施例，輸入/輸出場效應電晶體閘極電極結構500的表面積或覆蓋區大於約1μm2，在約1μm2和約10μm2之間，或大於約10μm2(例如，約20μm2)。根據部分實施例，化學機械平坦化期間的凹陷和空間可用性(尤其)是用於定義第5圖所示的輸入/輸出場效應電晶體閘極電極結構500的橫向尺寸(例如，長度和寬度)的因素。
在部分實施例中，非輸入/輸出場效應電晶體閘極電極結構505是一種犧牲閘極電極結構，其在後續操作中將被金屬閘極電極堆疊代替。
參考第3圖，方法300繼續操作315，其為在多晶矽閘極電極結構(例如，輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505)的側壁表面上形成間隔物結構的過程。作為示例而非限制，第6圖繪示在輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505的側壁上形成的間隔物結構130。作為示例而非限制，間隔物結構260可以透過毯覆式沉積間隔物材料(例如，氮化矽)接著各向異性蝕刻製程來形成，此各向異性蝕刻製程從第6圖所繪示之結構的所有水平表面(例如，y-x平面)選擇性地去除間隔物材料。
在部分實施例中，一旦在輸入/輸出場效應電晶體閘極電極結構500的側壁表面上形成了間隔物結構130， 則第二蝕刻製程去除在輸入/輸出基板區域400中未被間隔物結構130掩蓋(例如，覆蓋)之部分的閘極介電層120。換句話說，間隔物結構130和輸入/輸出場效應電晶體閘極電極結構500作為蝕刻遮罩，以限定在輸入/輸出基板區域400中的輸入/輸出場效應電晶體的閘極介電層120的長度。因此，如第6圖所示，間隔物結構130不覆蓋輸入/輸出場效應電晶體中的閘極介電層120的側壁表面。相反地，對於非輸入/輸出場效應電晶體，間隔物結構130在高介電常數閘極介電層410的側壁表面上延伸。
在部分實施例中，在形成間隔物結構130的操作315之前，使用輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505作為佈植遮罩，在半導體基板105中透過離子佈植製程形成輕摻雜區域600。之後，在形成間隔物結構130之後，第二離子佈植製程分別在輸入/輸出基板區域400和非輸入/輸出基板區域405中形成重摻雜區域610。在第二離子佈植製程期間，間隔物結構130作為佈植遮罩。因此，輕摻雜區域600實質上與輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505對齊，並且重摻雜區域610實質上與間隔物結構130對齊。在部分實施例中，輕摻雜區域600和重摻雜區域610一起形成輸入/輸出場效應電晶體和非輸入/輸出場效應電晶體的源極/汲極區域。
在部分實施例中，在形成間隔物結構130之後， 重摻雜區域610的頂表面被矽化以在輸入/輸出場效應電晶體和非輸入/輸出場效應電晶體的源極/汲極區域上方形成自我對準矽化物(self-aligned silicide)(salicide)層145。作為示例而非限制，矽化物層145的形成可如下所示。可以在半導體基板105上毯覆式沉積金屬層。在隨後的退火製程期間，在所沉積的金屬與暴露的矽直接接觸的地方(例如，半導體基板105的重摻雜區域610)形成矽化物。在矽化製程中，輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505的頂表面未被矽化，因為兩個結構均被氧化物層515和氮化物層520覆蓋(例如，未暴露)。在矽化製程之後，未反應的金屬例如透過濕式蝕刻製程去除。在部分實施例中，在去除未反應的金屬之後執行第二退火製程以完成矽化製程。作為示例而非限制，矽化物層145可以包括矽化鎳、矽化鈦、矽化鈷、矽化鎢或任何其他合適的金屬矽化物。
參考第3圖，方法300繼續操作320，其為在間隔物結構130、輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505上形成蝕刻停止層的過程。在部分實施例中，可以毯覆式沉積蝕刻停止層以覆蓋(例如，保形地)配置在半導體基板105上或半導體基板105中的所有特徵。例如，如第7圖所示，蝕刻停止層150沉積在輸入/輸出場效應電晶體閘極電極結構500、非輸入/輸出場效應電晶體閘極電極結構505、間隔物結構130、基板隔離區域110和矽化物層145上。 作為示例而非限制，蝕刻停止層150可以是氮化物層(例如，氮化矽層)。
參考第3圖和第8圖，方法300繼續操作325，其為在輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505的側壁表面周圍形成介電層115的過程。作為示例而非限制，可以在半導體基板105上毯覆式沉積介電層115，使得輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505嵌入於介電層115中。隨後的化學機械平坦化製程從輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505的頂表面去除多餘的介電材料。在部分實施例中，化學機械平坦化製程去除蝕刻停止層150、氮化物層520和氧化物層515的一部分，使得在輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505中均暴露出多晶矽閘極電極層125的頂表面，如第8圖所示。在部分實施例中，作為上述化學機械平坦化製程的結果，在輸入/輸出場效應電晶體閘極電極結構500和非輸入/輸出場效應電晶體閘極電極結構505中，多晶矽閘極電極層125的頂表面與介電層115的頂表面實質上共平面。在部分實施例中，在化學機械平坦化製程之後，輸入/輸出場效應電晶體閘極電極結構500的頂表面保持實質上平坦而沒有凹陷。另外，在化學機械平坦化製程之後，由於閘極介電層120和高介電常數閘極介電層410之間的厚度差異， 輸入/輸出場效應電晶體閘極電極結構500變得比非輸入/輸出場效應電晶體閘極電極結構505更矮(例如，500H<505H)。
參考第3圖，方法300繼續進行操作330，其為使用金屬閘極電極結構代替在非輸入/輸出場效應電晶體閘極電極結構505中的閘極電極層125的過程。作為示例而非限制，參考第9圖，選擇性地去除金屬閘極電極層125並用金屬閘極電極905代替，以形成非輸入/輸出場效應電晶體910。在部分實施例中，金屬閘極電極905包括一個或多個金屬或含金屬的層。作為示例而非限制，可以透過使用硬遮罩(例如，氮化物層)掩蓋輸入/輸出基板區域400並透過濕式蝕刻製程、乾式蝕刻製程或它們的組合從非輸入/輸出場效應電晶體閘極電極結構505中去除多晶矽閘極電極層125，來執行選擇性地從非輸入/輸出場效應電晶體閘極電極結構505中去除多晶矽閘極電極層125。在部分實施例中，不透過從非輸入/輸出場效應電晶體閘極電極結構505中去除多晶矽閘極電極層125的蝕刻製程去除高介電常數閘極介電層410。一旦多晶矽閘極電極層125已從非輸入/輸出場效應電晶體閘極電極結構505中選擇性地去除，可以接著沉積金屬閘極電極905。在部分實施例中，來自金屬閘極電極905的材料分別毯覆式地沉積在輸入/輸出基板區域400和非輸入/輸出基板區域405中。化學機械平坦化製程隨後從介電層115的頂表面去除多餘的金屬閘極電極材料以形成非輸入/輸出場效應電晶體910。 在金屬閘極電極材料的化學機械平坦化製程期間，去除輸入/輸出基板區域400上的硬遮罩(在第9圖中未繪示)，並暴露輸入/輸出場效應電晶體閘極電極結構500的多晶矽閘極電極層125(如第9圖所示)。在部分實施例中，在金屬閘極電極化學機械平坦化製程之後，輸入/輸出場效應電晶體閘極電極結構500的頂表面保持實質上平坦而沒有凹陷。在部分實施例中，在上述金屬閘極電極材料的化學機械平坦化製程期間，輸入/輸出場效應電晶體閘極電極結構500的多晶矽閘極電極層125對凹陷具有恢復力。
參考第3圖，方法300結束在操作335，其為在輸入/輸出場效應電晶體閘極電極結構500的頂表面上形成矽化物以形成第9圖所示的多晶矽輸入/輸出場效應電晶體915的過程。在部分實施例中，矽化製程可以類似於上述形成矽化物層145的製程中所描述的矽化製程。在部分實施例中，在矽化製程期間可透過硬遮罩(例如，氮化物層)遮蓋非輸入/輸出基板區域405可以。參考第10圖，可以在輸入/輸出基板區域400和非輸入/輸出基板區域405上方之介電層115上毯覆式沉積金屬層(第10圖中未繪示)。在隨後的退火製程期間，在輸入/輸出場效應電晶體閘極電極結構500之暴露的頂表面上形成矽化物。在矽化製程之後，透過例如濕式蝕刻製程去除未反應的金屬。在部分實施例中，在去除未反應的金屬之後執行第二退火製程以完成矽化製程。因此，在多晶矽閘極電極層125的頂表面形成矽化物層135，並且形成多晶矽輸入/輸出場效 應電晶體915。作為示例而非限制，矽化物層135可以包括矽化鎳、矽化鈦、矽化鈷、矽化鎢或任何其他合適的金屬矽化物。根據部分實施例，在多晶矽閘極電極層125上形成矽化物層135的過程可以與在積體電路的其他區域中形成矽化物層的過程相結合。
在部分實施例中，方法300可用於形成具有多晶矽閘極電極和氧化矽閘極介電質的非平面輸入/輸出場效應電晶體結構(如第2圖所示的輸入/輸出鰭式場效應電晶體結構200)。
本公開的實施例針對整合形成具有多晶矽閘極電極/氧化矽閘極介電質的輸入/輸出場效應電晶體以及形成具有金屬閘極電極/高介電常數閘極介電質的非輸入/輸出場效應電晶體的方法。在部分實施例中，在非輸入/輸出場效應電晶體的金屬閘極電極化學機械平坦化製程期間，輸入/輸出場效應電晶體的多晶矽閘極電極為化學機械平坦化凹陷提供恢復力，並因此允許形成具有更大的覆蓋區(例如，大於約1μm2，在約1μm2和約10μm2之間，或大於約10μm2(例如，約20μm2)的輸入/輸出場效應電晶體的製程。在部分實施例中，本公開描述的方法適用於平面和非平面電晶體結構(例如，鰭式場效應電晶體)。
在部分實施例中，一種電晶體結構包括形成在半導體基板的第一區域上的第一電晶體，其中此第一電晶體包括閘極介電質、多晶矽閘極電極和第一間隔物結構。多晶 矽閘極電極設置在閘極介電質上，其中閘極介電質比閘極電極長。第一間隔物結構鄰接多晶矽閘極電極的側壁，使得間隔物結構的側壁與閘極介電質的側壁對齊。此電晶體結構還包括形成在半導體基板的第二區域上的第二電晶體，其中第二電晶體比第一電晶體窄並且包括高介電常數閘極介電質、金屬閘極電極和第二間隔物結構。金屬閘極電極設置在高介電常數閘極介電質上並與之對齊，以使金屬閘極電極的側壁與高介電常數閘極介電質的側壁對齊。第二間隔物結構鄰接金屬閘極電極和高介電常數閘極介電質的側壁。於一些實施例中，多晶矽閘極電極的表面積在大約10μm2和大約20μm2之間。於一些實施例中，多晶矽閘極電極的中心至邊緣的厚度比為約0.9。於一些實施例中，多晶矽閘極電極的寬度和金屬閘極電極的寬度實質上相等。於一些實施例中，在部分實施例中，一種電晶體結構的製作方法包括在半導體基板的第一區域上沉積氧化矽層；在半導體基板的第二區域上沉積比氧化矽層薄的高介電常數介電層；在氧化矽層和高介電常數介電層上沉積多晶矽層；對多晶矽層進行圖案化，以在氧化矽層上形成第一多晶矽閘極電極結構，並在高介電常數介電層上形成第二多晶矽閘極電極結構，其中第一多晶矽閘極電極結構比第二多晶矽閘極電極結構寬並且比氧化矽層窄。此方法還包括在第一多晶矽閘極電極結構的側壁上形成第一間隔物，以使第一間隔物的外側壁與氧化矽層的側壁對齊；在第二多晶矽閘極電極 結構和高介電常數介電層的側壁上形成第二間隔物；用金屬閘極電極結構代替第二多晶矽閘極電極結構。於一些實施例中，圖案化多晶矽層包含使第一多晶矽閘極電極結構的表面積大於第二多晶矽閘極電極結構的表面積。於一些實施例中，圖案化多晶矽層包含形成具有約10μm2至約20μm2的表面積的第一多晶矽閘極電極結構。於一些實施例中，替換第二多晶矽閘極電極結構包含掩蓋第一多晶矽閘極電極結構。於一些實施例中，替換第二多晶矽閘極電極結構包含將第一多晶矽閘極電極結構暴露於化學機械平坦化製程。於一些實施例中，方法更包含在替換第二多晶矽閘極電極結構之前，在第一多晶矽閘極電極結構和該第二多晶矽閘極電極結構之間沉積介電層並平坦化介電層，使得介電層的頂表面和第一多晶矽閘極電極結構的頂表面及第二多晶矽閘極電極結構的頂表面實質上共平面。於一些實施例中，平坦化介電層包含平坦化介電層以使第一多晶矽閘極電極結構比第二多晶矽閘極電極結構矮，並且第一多晶矽閘極電極結構的中心至邊緣的厚度比在大約0.9和大約1之間。
在部分實施例中，一種電晶體結構包括形成在半導體基板的第一區域上的第一電晶體，其中此第一電晶體包括氧化矽閘極介電質、多晶矽閘極電極和第一間隔物結構。多晶矽閘極電極設置在氧化矽閘極介電質上，並且此多晶矽閘極電極的側壁邊緣與氧化矽閘極介電質的側壁邊緣不對齊。第一間隔物結構的內側壁鄰接多晶矽閘極電極的側 壁邊緣。此電晶體結構還包括形成在半導體基板的第二區域上的第二電晶體，其中第二電晶體比第一電晶體窄並且包括高介電常數閘極介電質、金屬閘極電極和第二間隔物結構。金屬閘極電極設置在高介電常數閘極介電質上，以使金屬閘極電極的側壁邊緣與高介電常數閘極介電質的側壁邊緣對齊。第二間隔物結構鄰接金屬閘極電極和高介電常數閘極介電質的側壁邊緣。於一些實施例中，第一間隔物結構具有與氧化矽閘極介電質的側壁邊緣對齊的複數個外側壁邊緣。於一些實施例中，多晶矽閘極電極的表面積在大約10μm2和大約20μm2之間，並且多晶矽閘極電極的中心至邊緣的厚度比在大約0.9和大約1之間。於一些實施例中，氧化矽閘極介電質比高介電常數閘極介電質厚。於一些實施例中，金屬閘極電極比多晶矽閘極電極高，金屬閘極電極與多晶矽閘極電極之間的高度差等於氧化矽閘極介電質和高介電常數閘極介電質之間的厚度差。
應當理解，本公開中「實施方式」的段落而非「摘要」的段落旨在用於解釋請求項。本公開中，摘要的段落可以闡述本公開的一個或多個實施例(但不是所有可能的實施例)，因此，摘要的段落無意以任何方式限制後述之請求項。
前述公開概述了幾個實施例的特徵，使得本領域技術人員可以更好地理解本公開的各方面。本領域技術人員將理解，他們可以容易地將本公開用作設計或修改其他過程和結構的基礎，以實現與本文介紹之實施例相同的目的 和/或實現相同的益處。本領域技術人員還將理解，這樣的等效構造不脫離本公開的精神和範圍，並且在不脫離本公開的精神和範圍的情況下，它們可以在此進行各種改變、替換和變更。
100:輸入/輸出場效應電晶體結構
105:半導體基板
110:基板隔離區域
115:介電層
120:閘極介電層
125:閘極電極層
125L:長度
125W:寬度
125T:厚度
130:間隔物結構
135:矽化物層
140:源極/汲極區域
145:矽化物層
150:蝕刻停止層
AB:切割線
X:軸
Y:軸
Z:軸

Claims (10)

  1. 一種電晶體結構，包含：一第一電晶體，形成於一半導體基板的一第一區域上，其中該第一電晶體包含：一閘極介電質；一多晶矽閘極電極，設置在該閘極介電質上，該多晶矽閘極電極的一第一長度在0.05μm至50μm的範圍內，其中該閘極介電質比該多晶矽閘極電極長；一第一間隔物結構，鄰接該多晶矽閘極電極的一側壁，使得第一該間隔物結構的一側壁與該閘極介電質的一側壁對齊；以及一金屬矽化物層，設置在該多晶矽閘極電極上；以及一第二電晶體，具有比該第一電晶體短的一第二長度，並且形成在該半導體基板的一第二區域上，其中該第二電晶體包含：一高介電常數閘極介電質；一金屬閘極電極，設置在該高介電常數閘極介電質上並與該高介電常數閘極介電質對齊，以使該金屬閘極電極的一側壁與該高介電常數閘極介電質的一側壁實質上對齊；以及一第二間隔物結構，鄰接該金屬閘極電極的該側壁和該高介電常數閘極介電質的該側壁。
  2. 如請求項1所述之電晶體結構，其中該多晶矽閘極電極的表面積在大約10μm2和大約20μm2之間。
  3. 如請求項1所述之電晶體結構，其中該多晶矽閘極電極的寬度和該金屬閘極電極的寬度實質上相等。
  4. 如請求項1所述之電晶體結構，其中該金屬閘極電極比該多晶矽閘極電極高，且該金屬閘極電極與該多晶矽閘極電極之高度差實質上等於該閘極介電質和該高介電常數閘極介電質之間的厚度差。
  5. 如請求項1所述之電晶體結構，其中該金屬矽化物層和該多晶矽閘極電極具有實質上相等的表面積。
  6. 如請求項1所述之電晶體結構，其中該第一電晶體被配置為在大約5伏特下運作，並且該第二電晶體被配置為在大約1伏特下運作。
  7. 一種電晶體的製作方法，包含：沉積一氧化矽層於一半導體基板的一第一區域上；沉積一高介電常數介電層於該半導體基板的一第二區域上，其中該高介電常數介電層比該氧化矽層薄；沉積一多晶矽層於該氧化矽層和該高介電常數介電層 上；圖案化該多晶矽層，以在該氧化矽層上形成一第一多晶矽閘極電極結構，並在該高介電常數介電層上形成一第二多晶矽閘極電極結構，該第一多晶矽閘極電極結構的一長度在0.05μm至50μm的範圍內，其中該第一多晶矽閘極電極結構的該長度大於該第二多晶矽閘極電極結構的長度，並且該第一多晶矽閘極電極結構比該氧化矽層窄；形成一第一間隔物於該第一多晶矽閘極電極結構的複數個側壁上，以使該第一間隔物的複數個外側壁與該氧化矽層的複數個側壁對齊；形成一第二間隔物於該第二多晶矽閘極電極結構的複數個側壁和該高介電常數介電層的複數個側壁上；使用一金屬閘極電極結構代替該第二多晶矽閘極電極結構；以及形成一金屬矽化物層於該第一多晶矽閘極電極結構上。
  8. 如請求項7所述之方法，更包含：在替換該第二多晶矽閘極電極結構之前，在該第一多晶矽閘極電極結構和該第二多晶矽閘極電極結構之間沉積一介電層並平坦化該介電層，使得該介電層的頂表面和該第一多晶矽閘極電極結構的頂表面及該第二多晶矽閘極電極結構的頂表面實質上共平面。
  9. 如請求項8所述之方法，其中平坦化該介電 層包含平坦化該介電層以使該第一多晶矽閘極電極結構比該第二多晶矽閘極電極結構矮，並且該第一多晶矽閘極電極結構的中心至邊緣的厚度比在大約0.9和大約1之間。
  10. 一種電晶體結構，包含：一第一電晶體，形成於一半導體基板的一第一區域上，其中該第一電晶體包含：一氧化矽閘極介電質；一多晶矽閘極電極，設置在該氧化矽閘極介電質上，該多晶矽閘極電極的一長度在0.05μm至50μm的範圍內，其中該多晶矽閘極電極的複數個側壁邊緣與該氧化矽閘極介質的複數個側壁邊緣不對齊；一第一間隔物結構，具有複數個內側壁鄰接該多晶矽閘極電極的複數個側壁邊緣；以及一金屬矽化物層，設置於該多晶矽閘極電極上；以及一第二電晶體，形成在該半導體基板的一第二區域上，其中該第二電晶體的表面積小於該第一電晶體的表面積，並且包含：一高介電常數閘極介電質；一金屬閘極電極，設置在該高介電常數閘極介電質上，以使該金屬閘極電極的複數個側壁邊緣與該高介電常數閘極介電質的複數個側壁邊緣對齊；以及一第二間隔物結構，鄰接該金屬閘極電極的該些 側壁邊緣和該高介電常數閘極介電質的該些側壁邊緣。
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