TWI747067B - 晶圓級扇出特殊應用積體電路橋接記憶體堆疊 - Google Patents

晶圓級扇出特殊應用積體電路橋接記憶體堆疊 Download PDF

Info

Publication number
TWI747067B
TWI747067B TW108138225A TW108138225A TWI747067B TW I747067 B TWI747067 B TW I747067B TW 108138225 A TW108138225 A TW 108138225A TW 108138225 A TW108138225 A TW 108138225A TW I747067 B TWI747067 B TW I747067B
Authority
TW
Taiwan
Prior art keywords
rdl
interposer
integrated circuit
processor
package assembly
Prior art date
Application number
TW108138225A
Other languages
English (en)
Other versions
TW202042367A (zh
Inventor
楠勳 金
雲星 權
澤圭 姜
Original Assignee
美商谷歌有限責任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商谷歌有限責任公司 filed Critical 美商谷歌有限責任公司
Publication of TW202042367A publication Critical patent/TW202042367A/zh
Application granted granted Critical
Publication of TWI747067B publication Critical patent/TWI747067B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)

Abstract

本發明揭示一種封裝總成及一種產生該封裝總成之方法。該封裝總成包含一重佈層(RDL)、一積體電路(IC)、一或多個記憶體模組及一中介層，該中介層包括來自穿矽通孔(TSV)、穿模通孔(TMV)及電鍍通孔(PTH)之一列表的複數個通孔。在一些實施方案中，該IC經電及機械附接至該RDL之一第一側。在一些實施方案中，該一或多個記憶體模組及該中介層安置於該RDL之一第二側上。該封裝總成亦包含具有一模製材料之一模製物，該模製材料囊封該IC、該一或多個記憶體模組、該中介層及該RDL以形成該封裝總成。在一些實施方案中，該IC經由該IC、該RDL、該等通孔與一外部電路板之間的一系列電連接來導電連接至該外部電路板。

Description

晶圓級扇出特殊應用積體電路橋接記憶體堆疊
隨著行動運算系統之快速發展，管理此等系統之功耗及熱預算變得更具挑戰(歸因於效能改良之需求)。封裝產業正在努力尋找下一代高效能行動積體電路(IC)(諸如ASIC)之一解決方案。
例如，一習知行動ASIC封裝通常具有安置於ASIC封裝內之一記憶體模組。例如，由於封裝大小要求，動態隨機存取記憶體(DRAM)模組通常堆疊於ASIC之頂部上。DRAM配置於ASIC之頂部上從維持一減小封裝大小方面提供一小佔據面積及相較於早期組態之一改良，但其並非無限制。例如，就DRAM堆疊於ASIC之頂部上之組態而言，若要使ASIC達到其效能極限，則其功率輸出會導致過熱，因為其不具有用於冷卻之一暴露表面。因此，需要一創新方法來解決熱功率平衡且不犧牲效能之提高。
至少一態樣係關於一種封裝總成。該封裝總成包含：一重佈層(RDL)；及一處理器，其經電及機械耦合至該RDL之一第一側。該封裝總成亦包含一中介層，其經電及機械耦合至與該第一側對置之該RDL之 一第二側。該封裝總成亦包含一積體電路晶粒，其經電及機械耦合至該RDL之該第二側。該封裝總成亦包含複數個封裝球，其等耦合至與該RDL對置之該中介層之一側以將該封裝總成電及機械耦合至一外部電路板。
在一些實施方案中，該封裝總成亦包含電及機械耦合至該等封裝球之該外部電路板。在一些實施方案中，該處理器經由該RDL、該中介層及該複數個封裝球來電連接至該外部電路板。在一些實施方案中，該中介層包含來自穿矽通孔(TSV)、穿模通孔(TMV)及電鍍通孔(PTH)之一列表的複數個通孔，且至該外部電路板之該電連接係透過該等通孔。在一些實施方案中，該處理器包含一特殊應用積體電路(ASIC)。在一些實施方案中，該積體電路晶粒包含一記憶體模組。
在一些實施方案中，該封裝總成包含一模製材料，其囊封該中介層、該RDL及該處理器之一部分以使該處理器之一表面至少實質上無該模製材料。在一些實施方案中，該積體電路晶粒安置成相鄰於該中介層且不與該中介層重疊。
至少一態樣係關於一種產生一封裝總成之方法。該方法包含：將一處理器耦合至一重佈層(RDL)之一第一側；將一中介層耦合至與該第一側對置之該RDL之一第二側；將一積體電路晶粒耦合至該RDL之該第二側；及將複數個封裝球耦合至與RDL對置之該中介層之一側。
在一些實施方案中，該方法包含：將該處理器至少部分囊封於一模製材料中，使得與該RDL對置之該處理器之一表面至少實質上無模製材料。在一些實施方案中，該方法進一步包含將該中介層及該積體電路晶粒至少部分囊封於一模製材料中。
在該方法之一些實施方案中，該處理器包含一特殊應用積體電路。在該方法之一些實施方案中，該積體電路晶粒包含一記憶體模組。在該方法之一些實施方案中，該RDL提供該積體電路晶粒與該處理器之間的一電連接。
在該方法之一些實施方案中，該RDL、該中介層及該等封裝球提供該處理器與一外部電路板之間的一電連接。
在一些實施方案中，該方法進一步包含經由該等封裝球將該中介層耦合至一外部電路板。
在該方法之一些實施方案中，該積體電路晶粒耦合至該RDL，在橫向上相鄰於該中介層，且不與該中介層重疊。
在一些實施方案中，該方法進一步包含：將額外積體電路晶粒耦合至該RDL之該第二側，使該額外積體電路晶粒橫向上相鄰於該積體電路晶粒或該中介層，且使該額外積體電路晶粒不與該積體電路晶粒或該中介層重疊。
下文將詳細論述此等及其他態樣及實施方案。以上資訊及以下詳細描述包含各種態樣及實施方案之繪示性實例，且提供理解主張態樣及實施方案之性質及特性的一概述及框架。圖式提供各種態樣及實施方案之繪示及一進一步理解，且併入本說明書且構成本說明書之一部分。
100:封裝總成
102:封裝球
110:重佈層(RDL)
112:凸塊接合
120:積體電路(IC)
130:被動電組件/電容器
142:特殊應用積體電路(ASIC)/記憶體模組
144:ASIC/記憶體模組
160:中介層
180:模製物
182:模製物
200A:封裝總成
200B:封裝總成
210a:RDL
210b:RDL
230b:被動電子組件
242a:晶粒
242b:晶粒
244a:晶粒
244b:晶粒
262a:被動組件區域
262b:中介層
264a:中介層
264b:中介層
266a:被動組件區域
300a:封裝總成
300A:階段
300b:封裝總成
300B:階段
300C:階段
300D:階段
300E:階段
300F:階段
300G:階段
300H:階段
302:封裝球
305:載體晶圓
310:RDL
312:凸塊接合
314:凸塊接合
315:釋放層
320a:IC
320b:IC
330:被動電組件
342a:記憶體模組
342b:記憶體模組
344a:記憶體模組
344b:記憶體模組
360a:中介層
360b:中介層
370a:通孔
370b:通孔
380:模製物
382:模製物
390a:外部電路板/基板
390b:外部電路板/基板
400:方法
410:步驟
420:步驟
430:步驟
440:步驟
450:步驟
460:步驟
附圖不意欲按比例繪製。各種圖式中之相同元件符號及名稱指示相同元件。為清楚起見，未在每一圖式中標記每一組件。在圖式中：圖1展示根據一繪示性實施方案之一封裝總成之一實施方 案之一橫截面圖；圖2A展示根據一繪示性實施方案之一封裝總成之一實施方案之一仰視圖；圖2B展示根據一繪示性實施方案之一封裝總成之另一實施方案之一仰視圖；圖3A至圖3H展示用於產生一封裝總成之一程序流程之示意圖；及圖4係根據一繪示性實施方案之產生一封裝總成之一方法之一流程圖。
本發明係關於一封裝總成及用於產生該封裝總成組態之一方法之各種實施方案，該封裝總成具有適合於在不犧牲一積體電路(IC)之功耗及效能的情況下改良熱功率平衡之一組態。
如上文所論述，IC(例如特殊應用積體電路或ASIC)功率及效能之提高要求需要重新審視用於管理此等裝置之溫度的熱管理系統以更好適應此等IC之更高功耗。需要從封裝級設計組態方面改良基於ASIC上DRAM組態之一封裝總成之當前熱管理策略。由於ASIC上DRAM組態不提供ASIC之一暴露表面，所以沒有主動冷卻機制來耗散由以產生更高效能所需之更高功率運行的ASIC產生之更高熱量。
當前既有方法提高一IC之功率及效能，同時適度平衡熱功率。一些方法包含層疊封裝(PoP)組態、層疊封裝-模製嵌入式封裝(PoP-MEP)組態及混合晶粒堆疊(HDS)組態。然而，此等組態趨向於使一中小型封裝中之一給定ASIC具有一較差熱效能。另外，基於此等組態之ASIC 封裝之信號完整性及電源完整性亦似乎較差。諸如積體扇出型層疊封裝(InFO PoP)組態之一組態廣泛用於行動應用，諸如一蜂巢式電話或一平板電腦。正如上述三種組態，InFO PoP亦似乎使一中小型封裝中之一給定ASIC具有一較差熱效能。基於此組態之一行動IC封裝之信號完整性及電源完整性似乎亦較差。
上述四種組態之較差熱效能可能歸因於組態使ASIC安置於封裝總成之底部上且使DRAM堆疊於ASIC之頂部上。且由於ASIC無可用暴露表面來耗散所產生之熱(歸因於DRAM在頂部上)，所以降低功耗且因此降低效能以避免ASIC過熱。
當前可用之一更先進封裝技術係基於面板級封裝(PLP-m)技術，其使用一精細重佈層(RDL)及接合來提高ASIC效能。在此組態中，ASIC及記憶體經並排放置使得ASIC具有一暴露表面區域來散熱。此組態之熱管理更簡單，因為無需壓制ASIC且ASIC因此可經組態以依最大速度及效能運行。然而，歸因於ASIC及記憶體模組橫向並排放置，封裝大小急劇增大。例如，用於傳統組態(諸如PoP、PoP-MEP及HDS)之典型15mm×15mm封裝大小需要因PLP-m而增大至高達(例如)約19mm×13mm之一封裝大小以包含一個DRAM(DRAM大小約5.3mm×3.2mm)且將增長至24mm×13mm以包含兩個DRAM。封裝大小增大係不利的，對於一多封裝(MCP)組態尤其不利，其中一個別封裝大小之幾毫米增大將使MCP組態顯著增大。
本文中所描述之組態提供一種封裝總成，其可產生與PLP-m組態相當之效能及熱管理，同時維持封裝大小接近標準15mm×15mm。所揭示之封裝總成組態無需任何新製程且因此可使用既有製造技術來產 生。
本文中所揭示之一封裝總成之各種實施方案包含一重佈層(RDL)、一積體電路(IC)、一或多個記憶體模組及一中介層。如本文中所描述，根據一些實施方案，該IC經電及機械附接至該RDL之一第一側。在一些實施方案中，該一或多個記憶體模組及該中介層安置於該RDL之一第二側上。在各種實施方案中，該封裝總成亦包含用於囊封該IC、該一或多個記憶體模組、該中介層及該RDL以形成該封裝總成之一模製材料。在一些實施方案中，該模製材料包含一環氧樹脂。
如本文中所描述，在該封裝總成之一些實施方案中，該RDL包含複數個金屬層，其等由介電材料層分離以允許該IC與該封裝總成內之其他電組件之間的一組空間更分散電連接。該RDL具有複數個接觸墊用於接合至耦合至該IC之下側的凸塊接合(例如焊料或金凸塊或球)以藉此將該IC機械及電耦合至該RDL之該第一側。在一些其他實施方案中，可使用焊錫膏或其他適合導電接合而非使用凸塊接合來經由表面安裝技術將該IC耦合至該RDL。在一些實施方案中，該RDL亦包含複數個接觸墊用於接合至耦合至該等記憶體模組及/或該中介層的凸塊接合(例如焊料或金凸塊或球)以藉此將該記憶體及該中介層機械及電耦合至該RDL之該第二側。在一些實施方案中，使用一焊錫膏或其他導電錫膏或膠來將該等記憶體模組及/或該中介層表面安裝至該RDL。在一些實施方案中，該一或多個記憶體模組及該中介層跨該RDL之該第二側佈置，使得該一或多個記憶體模組及該中介層彼此不上下堆疊。
在各種實施方案中，該中介層包含來自(例如(但不限於))穿矽通孔(TSV)、穿模通孔(TMV)及電鍍通孔(PTH)之一列表的複數個通 孔。在一些實施方案中，該等通孔經組態以提供該IC與一外部電路板之間的電連接。在一些實施方案中，該等通孔包含或具有一塗層，其包含(例如)銅、鋁或金之至少一者。
在一些實施方案中，該封裝總成亦包含(例如)呈一球柵陣列(BGA)之複數個焊料球用於提供該封裝總成與一外部電路板(諸如一印刷電路板)之間的機械及電連接。在一些實施方案中，該IC具有實質上無該模製材料之一暴露表面以允許冷卻該IC。
在一些實施方案中，該一或多個記憶體模組包含以下之一者：隨機存取記憶體(RAM)、靜態RAM、動態RAM(DRAM)、同步動態RAM或雙倍資料速率RAM(DDR RAM)(其包含DDR2 RAM及DDR4 RAM)、低功率DDR(LPDDR)、GDDR、DBM(資料增強記憶體)或未來記憶體或ASIC。
下圖及相對於圖之描述提供封裝總成及其產生方法之各種實施方案之額外細節。
圖1展示根據一繪示性實施方案之一封裝總成100之一實施方案之一橫截面圖。封裝總成100包含一重佈層(RDL)110、一積體電路(IC)120、複數個被動電組件130(例如電容器、電阻器、二極體等等)、記憶體模組或另一ASIC 142及144及一中介層160。如圖1中所展示，IC 120安置於RDL 110之頂部上。IC 120安置於RDL 110之一頂側(一第一側)上。IC 120可經由複數個凸塊接合(未展示)或任何適合電連接(諸如一焊錫膏)來導電連接至RDL 110。IC 120可為一處理器，諸如一ASIC、一FGPA、一微處理器、一DSP、一圖形處理單元(GPU)、一張量處理單元(TPU)或將自本文中所揭示之封裝總成之額外散熱特性受益之任何其他類 型之高效能積體電路。儘管圖1中僅展示一單一IC 120在RDL 110之頂側上，但應瞭解，在一些實施方案中，多個IC 120(例如多個處理器核心)可並排排列於一單一封裝總成中之RDL 110之頂側上。
如圖1中所展示，封裝總成100亦包含一模製物180、一模製物182、複數個凸塊接合112及複數個封裝球102。在一些實施方案中，記憶體模組或另一ASIC 142及144及中介層160安置於RDL 110之一底側(一第二側)上。在一些實施方案中，記憶體模組142及144及中介層160可經由複數個凸塊接合112(例如焊料或金凸塊或球)或任何適合電連接(諸如一焊錫膏)來導電連接至RDL 110。在一些實施方案中，封裝總成100包含複數個封裝球102用於提供封裝總成100與一外部電路板(未展示)或另一基板之間的機械及電連接。
在一些實施方案中，RDL 110係一般技術者已知之一典型重佈層，其用於在一封裝總成中之組件之間空間分佈電連接。RDL由一或多個圖案化金屬層形成，該等金屬層由介電層分離以允許跨RDL 110之表面且透過RDL 110路由互連件。在一些實施方案中，RDL 110包含複數個接觸墊或其他適合接觸區域用於電及機械耦合至封裝總成100之各種電子組件。在一些實施方案中，接觸墊塗覆有一或多個黏著層以改良焊料或金球之黏著，該等焊料或金球在重熔時形成至RDL 110之電及機械連接。接觸墊可在RDL 110之兩側上。
如圖1中所展示，在一些實施方案中，封裝總成100亦包含在IC 120附近嵌入於模製物180中以改善電源完整性之複數個被動電組件130，諸如電容器。另外或替代地，被動電組件130可安置於記憶體模組142或144附近。
如圖1中所展示，記憶體模組142及144安置於RDL 110之底側上。在一些實施方案中，記憶體模組142及144經由複數個凸塊接合112之一子集來導電連接至RDL 110之一部分。在一些實施方案中，記憶體模組142及144經由凸塊接合112之子集及RDL 110來導電連接至IC 120。在一些實施方案中，記憶體模組142及144可包含(但不限於)隨機存取記憶體(RAM)、靜態RAM、動態RAM(DRAM)、同步動態RAM及雙倍資料速率RAM(DDR RAM)(其包含DDR2 RAM及DDR4 RAM)、低功率(LPDDR)、GDDR、DBM(資料增強記憶體)或未來記憶體或ASIC。
如圖1中所展示，中介層160安置於RDL 110之底側上。在一些實施方案中，中介層160包含來自(例如(但不限於))穿矽通孔(TSV)、穿模通孔(TMV)及電鍍通孔(PTH)之一列表的複數個通孔。在一些實施方案中，中介層160經由凸塊接合112之一子集來導電連接至RDL 110之一部分。在一些實施方案中，中介層160經由凸塊接合112之子集及RDL 110來導電連接至IC 120。
在一些實施方案中，中介層160中之通孔經組態以提供IC 120與一外部電路板(未展示)(諸如一印刷電路板)之間的電連接。在一些實施方案中，中介層160中之通孔可包含或具有一塗層，其包含(例如)銅、鋁或金之至少一者。
在一些實施方案中，中介層160經由複數個封裝球102來導電連接至外部電路板。封裝球可為焊料球、金球或球或適合於將一封裝總成耦合至一外部電路板之其他可回焊導電材料。在一些實施方案中，IC 120可經由IC 120、RDL 110、複數個凸塊接合112、通孔及複數個封裝球 102之間的一系列電連接來導電連接至外部電路板。
如圖1中所展示，根據一些實施方案，封裝總成100包含囊封IC 120及複數個電容器130之模製物180。亦如圖1中所展示，封裝總成100亦包含囊封記憶體模組142及144及中介層160之模製物182。模製物180及182可由任何適合模製材料(諸如環氧樹脂)形成。
如圖1中所展示，IC 120具有完全無或實質上無模製材料之一暴露表面。如本文中所使用且在各種實施方案中，若IC 120之表面至少99%、約98%、約95%、約90%或約80%無模製材料，則表面被視為實質上無模製材料。暴露表面促進由IC 120產生之熱耗散。在一些實施方案中，一散熱器、蒸發冷卻元件或一主動冷卻元件(諸如一熱電冷卻器)耦合至IC 120之暴露表面以進一步促進熱管理。
圖2A展示根據一繪示性實施方案之一封裝總成200A之一實例實施方案之一仰視圖。如本文中所使用，封裝總成之一仰視圖係指將面向一外部電路板之封裝總成之一視圖，封裝總成經組態以耦合至外部電路板。如圖2A中所展示，封裝總成200A包含晶粒242a及244a、中介層264a及安置於一RDL 210a上之被動組件區域262a及266a。在一些實施方案中，組件242a、244a、262a、264a及266a跨RDL 210a佈置且彼此不重疊(即，彼此不上下堆疊)。
在一些實施方案中，晶粒242a及244a係記憶體模組(諸如相對於圖1所展示及描述之記憶體模組142及144)且因此將不再進一步詳細描述。在一些實施方案中，晶粒242a及244a各係另一類型之積體電路，較佳地具有相對較低功耗要求、較低效能ASIC。在一些實施方案中，被動組件區域262a及266a包含被動電子組件(諸如電容器)以緩和歸因於封裝 總成200A內之主動組件之時變功率需求的電流供應或電壓變動。在替代實施方案中，被動組件區域262a及266a代以用作較小積體電路組件之位置。在一些實施方案中，中介層264a類似於相對於圖1所展示及描述之中介層160。
圖2B展示根據一繪示性實施方案之一封裝總成200B之另一實例實施方案之一仰視圖。如圖2B中所展示，封裝總成200B包含晶粒242b及244b、橫向配置於一RDL 210b上之複數個被動電子組件230b(例如電容器)。封裝總成200B亦包含兩個中介層262b及264b。組件242b、244b、262b、264b及230b跨RDL 210b佈置且彼此不上下堆疊。
在一些實施方案中，晶粒242b及244b係記憶體模組，諸如記憶體模組142及144。在一些實施方案中，晶粒242b及244b之一或兩者係除記憶體模組之外的其他類型之積體電路，諸如具有比耦合至RDL之頂側的ASIC更低之散熱要求的較低功率ASIC。在一些實施方案中，中介層262b及264b各實質上類似於圖1中所展示之中介層160。
在不背離本發明之範疇的情況下，亦可在封裝總成之底側上採用中介層、積體電路晶粒及被動組件之各種替代佈局。
圖3A至圖3H展示用於產生一封裝總成之一程序流程之示意圖。圖3A至圖3H中所展示之程序流程繪示階段300A、300B、300C、300D、300E、300F、300G及300H中之封裝總成之產生進程。例如，圖3A中所展示之階段300A展示經由一釋放層315附接至一載體晶圓305之一RDL 310。在一些實施方案中，RDL 310類似於或實質上類似於相對於圖1所展示及描述之RDL 110。在一些實施方案中，載體晶圓305可為一矽基板或可用作一載體基板之任何適合晶圓。在一些實施方案中，釋放層315 可為半導體製造之技術中已知之任何適合釋放層。
如圖3B中所展示，階段300B繪示安置於RDL 310之一第一側(頂部)上之IC 320a及320b。階段300B亦展示安置於IC 320a及320b附近之複數個被動電組件330(在此情況下為電容器)。在一些實施方案中，複數個電容器放置於IC 320a及320b附近以提供電源完整性(例如為了回應於IC之時變電流汲取而緩和電流供應之變動)。在一些實施方案中，複數個凸塊接合312首先安置於IC 320a及320b上，且IC 320a及320b覆晶接合至RDL 310。
圖3C中所展示之階段300C繪示安置於RDL 310之第一側上之一模製物380。如圖3C中所展示，模製物380包含用於囊封IC 320a及320b、複數個被動電組件330及複數個凸塊接合312之一模製材料(例如環氧樹脂)。在一些實施方案中，IC 320a及320b之各者具有完全或至少實質上無模製材料之一暴露表面。在一些實施方案中，IC 320a及320b之各者具有約99%、約98%、約95%、約90%、約80%、約50%無模製材料之一暴露表面。在一些實施方案中，IC 320a及320b之暴露表面促進由IC 320a及320b產生之熱耗散。
圖3D中所展示之階段300D繪示移除載體晶圓305之後的RDL 310上之經釋放囊封IC 320a及320b。在一些實施方案中，經由一機械、化學或雷射燒蝕方法來發生載體晶圓305之移除。如圖3D中所展示，藉由移除釋放層315來獲得RDL 310上之經釋放囊封IC 320a及320b。在一些實施方案中，經由一化學、蒸汽、雷射、熱或電漿處理來發生釋放層315之移除。對於可透射紫外光波長之載體晶圓，可藉由施加紫外光來觸發釋放。應注意，圖3D中所展示之說明圖相對於圖3A至圖3C中所展示之 結構顛倒定向以繪示結構準備用於下一處理步驟。如圖3D中所展示，RDL 310之整個第二側經展示為將向其添加額外組件的一表面。
圖3E中所展示之階段300E繪示記憶體模組342a、344a、342b及344b及中介層360a及360b附接至RDL 310之第二側。如圖3E中所展示，記憶體模組342a及344a及中介層360a在經囊封IC 320a之一對置側上導電附接至RDL 310之第二側。類似地，階段300E繪示記憶體模組342b及344b及中介層360b在經囊封IC 320b之對置側上導電附接至RDL 310之第二側。在兩個附接中，複數個凸塊接合314(例如焊料或金球)用於提供記憶體模組342a、344a、342b及344b及中介層360a及360b與RDL 310之間的電連接。
在一些實施方案中，記憶體模組342a、344a、342b及344b類似於或實質上類似於相對於圖1所展示及描述之記憶體模組142及144，因此，此處將不再進一步詳細描述。在一些實施方案中，中介層360a及360b實質上類似於相對於圖1所展示及描述之中介層160。
在一些實施方案中，中介層360a及360b分別包含複數個通孔370a及370b。在一些實施方案中，各自中介層360a及360b中之通孔370a及370b經組態以提供IC 320a及320b與一外部電路板(如圖3H中所展示)之間的電連接。在一些實施方案中，通孔370a及370b之各者包含或具有一塗層，其具有(例如)銅、鋁或金之至少一者。
圖3F中所展示之階段300F繪示安置於RDL 310之第二側上之複數個封裝球302及一模製物382。如圖3F中所展示，模製物382包含囊封記憶體模組342a、344a、342b及344b、中介層360a及360b及複數個凸塊接合314之一模製材料。在一些實施方案中，中介層360a及360b之各者 具有完全或實質上無模製材料之一暴露表面。在一些實施方案中，中介層360a及360b之各者具有約99%、約98%、約95%、約90%、約80%、約50%無模製材料之一暴露表面。
圖3G中所展示之階段300G繪示經單粒化以產生個別封裝總成300a及300b之複數個封裝總成。如圖3G中所展示，封裝總成300a包含記憶體模組342a及344a、中介層360a及IC 320a，且封裝總成300b包含記憶體模組342b及344b、中介層360b及IC 320b。
圖3H中所展示之階段300H繪示分別附接至外部電路板390a及390b之單粒化封裝總成300a及300b。如圖3H中所展示，封裝總成300a經由複數個封裝球302來導電附接至外部電路板或基板390a，且封裝總成300b經由複數個封裝球302來導電附接至外部電路板或基板390b。
各自圖3A至3H中所繪示及描述之各個階段300A、300B、300C、300D、300E、300F、300G及300H可概述於下文將描述之一流程圖中。
圖4係根據一繪示性實施方案之用於產生一封裝總成之一方法400之一流程圖。方法400包含在步驟410中提供經由一釋放層附接至一載體晶圓之一重佈層(RDL)。方法400亦包含在步驟420中將一積體電路(IC)(諸如相對於圖1所論述之處理器之任何者)導電附接至RDL之一第一側。方法400亦包含在步驟430中將IC囊封於一模製材料中。方法400亦包含在步驟440中移除釋放層以藉此自RDL上之經囊封IC釋放載體晶圓。方法400亦包含在步驟450中在經囊封IC之一對置側上將一或多個記憶體模組及一中介層導電附接至RDL之一第二側。方法400進一步包含在步驟460中囊封一或多個記憶體模組及中介層以形成封裝總成。在一些實施方 案中，方法400包含囊封一或多個記憶體模組及中介層以形成複數個封裝總成。在一些實施方案中，方法400在步驟470視情況包含單粒化複數個封裝總成以產生個別封裝總成。
在一些實施方案中，一或多個記憶體模組包含以下之一者：隨機存取記憶體(RAM)、靜態RAM、動態RAM(DRAM)、同步動態RAM或雙倍資料速率RAM(DDR RAM)(其包含DDR2 RAM及DDR4 RAM)、LPDDR、GDDR、DBM(資料增強記憶體)或未來記憶體或ASIC。
儘管本說明書含有諸多特定實施細節，但此等不應被解釋為任何發明或可主張內容之範疇之限制，而是應被解釋為專用於特定發明之特定實施例之特徵之描述。亦可在一單一實施方案中組合實施本說明書之單獨實施方案之內文中所描述之特定特徵。相反地，亦可在多個實施方案中單獨或依任何適合子組合實施一單一實施方案之內文中所描述之各種特徵。此外，儘管上文可將特徵描述為作用於特定組合中且甚至最初如此主張，但來自一主張組合之一或多個特徵可在一些情況中自組合刪去且主張組合可針對一子組合或一子組合之變動。
類似地，儘管圖式中依一特定順序描繪操作，但此不應被理解為要求依所展示之特定順序或循序順序執行此等操作或執行所有繪示操作以達成所要結果。在特定情形中，多任務處理及並行處理可為有利的。此外，上述實施方案中之各種系統組件之分離不應被理解為在所有實施方案中需要此分離，而是應瞭解，所描述之程式組件及系統一般可一起整合於一單一軟體產品中或封裝至多個軟體產品中。
所提及之「或」可被解釋為包含性，使得使用「或」所描 述之任何術語可指示一單一描述項、一個以上描述項及所有描述項之任何者。標號「第一」、「第二」、「第三」等等未必意謂指示一順序且一般僅用於區分相同或類似項或元件。
熟習技術者可易於明白本發明中所描述之實施方案之各種修改，且在不背離本發明之精神或範疇的情況下，本文中所界定之一般原理可應用於其他實施方案。因此，申請專利範圍不意欲受限於本文中所展示之實施方案，而是被給予與本文中所揭示之此揭示內容、原理及新穎特徵一致之最廣範疇。
100:封裝總成
102:封裝球
110:重佈層(RDL)
112:凸塊接合
120:積體電路(IC)
130:被動電組件/電容器
142:特殊應用積體電路(ASIC)/記憶體模組
144:ASIC/記憶體模組
160:中介層
180:模製物
182:模製物

Claims (15)

  1. 一種封裝總成，其包括：一重佈層(RDL)；一處理器，其經電及機械耦合至該RDL之一第一側，該處理器使用第一複數個導電接合(conductive bonds)而直接電及機械(electrically and mechanically)耦合至該RDL之該第一側；一中介層(interposer)，其經電及機械耦合至該RDL之一第二側，該第二側與該第一側對置(opposite)，該中介層使用第二複數個導電接合而直接電及機械耦合至該RDL之該第二側，耦合至該RDL之該第二側之該中介層實質上與耦合至該RDL之該第一側之該處理器對置；一積體電路晶粒，其經電及機械耦合至該RDL之該第二側，該積體電路晶粒使用第三複數個導電接合而直接電及機械耦合至該RDL之該第二側；複數個封裝球，其等耦合至與該RDL對置之該中介層之一側以將該封裝總成電及機械耦合至一外部電路板；及一模製材料(mold material)，其囊封該中介層、該RDL及該處理器之一部分，留下該處理器之一表面至少實質上無該模製材料。
  2. 如請求項1之封裝總成，其中該處理器經由該RDL、該中介層及該複數個封裝球來電連接至該外部電路板。
  3. 如請求項2之封裝總成，其中該中介層包括來自穿矽通孔(TSV)、穿 模通孔(TMV)及電鍍通孔(PTH)之一列表的複數個通孔，且至該外部電路板之該電連接係透過該等通孔。
  4. 如請求項1之封裝總成，其中該處理器包括一特殊應用積體電路(ASIC)。
  5. 如請求項1之封裝總成，其中該積體電路晶粒包括一記憶體模組。
  6. 如請求項1之封裝總成，其中該積體電路晶粒安置成相鄰於該中介層且不與該中介層重疊。
  7. 一種封裝總成，其包括：一重佈層(RDL)；一處理器，其經電及機械耦合至該RDL之一第一側，該處理器使用第一複數個導電接合而直接電及機械耦合至該RDL之該第一側；一中介層，其經電及機械耦合至該RDL之一第二側，該第二側與該第一側對置，該中介層使用第二複數個導電接合而直接電及機械耦合至該RDL之該第二側，耦合至該RDL之該第二側之該中介層實質上與耦合至該RDL之該第一側之該處理器對置；一積體電路晶粒，其經電及機械耦合至該RDL之該第二側，該積體電路晶粒使用第三複數個導電接合而直接電及機械耦合至該RDL之該第二側；複數個封裝球(package balls)耦合至與該RDL對置之該中介層之一 側；一模製材料，其囊封該中介層、該RDL及該處理器之一部分，留下該處理器之一表面至少實質上無該模製材料；及一外部電路板，其經電及機械耦合至該複數個封裝球。
  8. 一種用於製造一封裝總成之方法，該方法包括：將一處理器耦合至一重佈層(RDL)之一第一側；將一中介層耦合至與該RDL之該第一側對置之該RDL之一第二側，耦合至該RDL之該第二側之該中介層實質上與耦合至該RDL之該第一側之該處理器對置；將一積體電路晶粒耦合至該RDL之該第二側；將複數個封裝球耦合至與RDL對置之該中介層之一側；及將該處理器之一部分囊封於一模製材料中，俾使與該RDL對置之該處理器之一表面至少實質上無模製材料。
  9. 如請求項8之方法，其中該處理器包括一特殊應用積體電路。
  10. 如請求項8之方法，其中該積體電路晶粒包括一記憶體模組。
  11. 如請求項8之方法，其中該RDL提供該積體電路晶粒與該處理器之間的一電連接。
  12. 如請求項8之方法，其中該RDL、該中介層及該等封裝球提供該處理 器與一外部電路板之間的一電連接。
  13. 如請求項8之方法，其包括經由該等封裝球將該中介層耦合至一外部電路板。
  14. 如請求項8之方法，其中該積體電路晶粒耦合至該RDL，橫向上相鄰於該中介層，且不與該中介層重疊。
  15. 如請求項8之方法，其包括：將額外積體電路晶粒耦合至該RDL之該第二側，使該額外積體電路晶粒橫向上相鄰於該積體電路晶粒或該中介層，且使該額外積體電路晶粒不與該積體電路晶粒或該中介層重疊。
TW108138225A 2019-05-07 2019-10-23 晶圓級扇出特殊應用積體電路橋接記憶體堆疊 TWI747067B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/405,304 2019-05-07
US16/405,304 US10930592B2 (en) 2019-05-07 2019-05-07 Wafer level fan-out application specific integrated circuit bridge memory stack

Publications (2)

Publication Number Publication Date
TW202042367A TW202042367A (zh) 2020-11-16
TWI747067B true TWI747067B (zh) 2021-11-21

Family

ID=69056130

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108138225A TWI747067B (zh) 2019-05-07 2019-10-23 晶圓級扇出特殊應用積體電路橋接記憶體堆疊

Country Status (3)

Country Link
US (1) US10930592B2 (zh)
TW (1) TWI747067B (zh)
WO (1) WO2020226692A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024117976A1 (en) * 2022-11-30 2024-06-06 Agency For Science, Technology And Research A wafer-level package and a method for forming the wafer-level package

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7151010B2 (en) * 2004-12-01 2006-12-19 Kyocera Wireless Corp. Methods for assembling a stack package for high density integrated circuits
US20110068459A1 (en) * 2009-09-23 2011-03-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
US20170062383A1 (en) * 2015-08-31 2017-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Making the Same
KR101942745B1 (ko) * 2017-11-07 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
TW201916197A (zh) * 2017-09-29 2019-04-16 日月光半導體製造股份有限公司 包含雙面重佈層之堆疊半導體封裝組件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10142116A1 (de) 2001-08-30 2002-11-14 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung
US6856009B2 (en) * 2003-03-11 2005-02-15 Micron Technology, Inc. Techniques for packaging multiple device components
US8546929B2 (en) * 2006-04-19 2013-10-01 Stats Chippac Ltd. Embedded integrated circuit package-on-package system
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US8716859B2 (en) * 2012-01-10 2014-05-06 Intel Mobile Communications GmbH Enhanced flip chip package
US9281292B2 (en) * 2012-06-25 2016-03-08 Intel Corporation Single layer low cost wafer level packaging for SFF SiP
US10971476B2 (en) * 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
KR20160090706A (ko) 2015-01-22 2016-08-01 에스케이하이닉스 주식회사 협폭 인터포저를 갖는 반도체 패키지

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7151010B2 (en) * 2004-12-01 2006-12-19 Kyocera Wireless Corp. Methods for assembling a stack package for high density integrated circuits
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
US20110068459A1 (en) * 2009-09-23 2011-03-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
US20170062383A1 (en) * 2015-08-31 2017-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Making the Same
TW201916197A (zh) * 2017-09-29 2019-04-16 日月光半導體製造股份有限公司 包含雙面重佈層之堆疊半導體封裝組件
KR101942745B1 (ko) * 2017-11-07 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지

Also Published As

Publication number Publication date
US20200357743A1 (en) 2020-11-12
US10930592B2 (en) 2021-02-23
TW202042367A (zh) 2020-11-16
WO2020226692A1 (en) 2020-11-12

Similar Documents

Publication Publication Date Title
US9666571B2 (en) Package-on-package structures
TWI616990B (zh) 一種高密度立體封裝的積體電路系統
US8618654B2 (en) Structures embedded within core material and methods of manufacturing thereof
TW201826461A (zh) 堆疊型晶片封裝結構
US9953907B2 (en) PoP device
TWI467726B (zh) 堆疊封裝結構
US20120049339A1 (en) Semiconductor package structure and manufacturing process thereof
US10269676B2 (en) Thermally enhanced package-on-package (PoP)
US20160172292A1 (en) Semiconductor package assembly
US10515887B2 (en) Fan-out package structure having stacked carrier substrates and method for forming the same
US20140151880A1 (en) Package-on-package structures
US7859118B2 (en) Multi-substrate region-based package and method for fabricating the same
KR20150116844A (ko) 패키지 온 패키지 구조들
TW202331992A (zh) 半導體封裝
TWI747067B (zh) 晶圓級扇出特殊應用積體電路橋接記憶體堆疊
TWI733142B (zh) 電子封裝件
Lau 3D IC integration and 3D IC packaging
US20220392861A1 (en) Electronic package and carrier thereof and method for manufacturing the same
US11516925B2 (en) Package stack structure and method for manufacturing the same
CN112397475A (zh) 具有微细间距硅穿孔封装的扇出型封装晶片结构及单元
US20240096835A1 (en) Manufacturing method of electronic package
TWI381512B (zh) 多晶片堆疊結構
US20240021571A1 (en) Hybrid bonding of semiconductor structures to advanced substrate panels
TW202310218A (zh) 半導體封裝及其製造方法
TW202207386A (zh) 封裝結構

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees