TWI744109B - Digital device using three states - Google Patents

Abstract

A digital device is provided. The digital device uses three states, including a ground (GND) state, a voltage (VDD) state, and a float state. On designing a chip, two storage units and a pad circuit are set inside; the pad circuit comprises a current limiter and two switches; and, therefore, less ports are contained than the conventional. That is, one port obtains three states. As comparing to the conventional having only two states, the present invention uses the port having the two storage units connected to the pad circuit for achieving the three states; a circuit featuring “pulling up” and “pulling down” is used to identify the connection state of the port; and the port determines a plurality of definitions through the three states of GND, VDD and float. Thus, a pad is saved for reducing the space and cost of the chip.

Description

Three-state digital structure

The present invention relates to a three-state digital structure, in particular to a circuit characteristic that uses pull up and pull down to identify the connection status of a port, and in particular it refers to the ability to make a port Multiple definitions can be judged by the three states of ground (GND), voltage (VDD) and idle connection (FLOAT).

Image sensors are commonly used in electronic devices, and with the miniaturization of electronic devices, the chip area of the image sensor also needs to be reduced. In the process of reducing the chip area, the number of pins is one of the important determinants. Because the pins in the general chip take up a lot of space and are larger than the general circuit, one more pad (pad) will have one more square position. However, the digital method of traditional technology is two states, one pin has only 0 and 1 The two states cause a large number of pads to be arranged, and therefore are regarded as a burden that increases the area of the overall circuit and therefore also increases the circuit manufacturing cost.

In view of the compact space of the circuit board, it is necessary to save as much space as possible for other valuable functions. However, the above-mentioned traditional design method not only consumes the space and cost of the chip, but also obviously wastes a lot of valuable space on the circuit board. Therefore, general users cannot meet the needs of users in actual use.

The main purpose of the present invention is to overcome the above-mentioned problems encountered by the prior art and provide a way to use the circuit characteristics of pull-up and pull-down to identify the connection status of the port, which can make a port Multiple definitions can be judged by the three states of GND, VDD and FLOAT, which can save a pad and achieve a three-state digital structure that saves chip space and cost.

To achieve the above purpose, the present invention is a three-state digital structure, which includes: a pad The circuit includes a first switch, a current limiter (Current Limiter), coupled between VDD and the first switch, a second switch, and a ground current limiter, coupled Between GND and the second switch, and the first and second switches are commonly connected to a port. Under this port, three configurations can be determined, which are VDD, GND, and FLOAT. The power current limiter may be a pull-up power current limiter for the port, the ground current limiter may be a pull-down ground current limiter for the port, and the pad circuit is provided with a pull-up of the port to VDD Path and the pull-down path from the port to GND; a first storage unit (Storage Unit) is connected to the pad circuit for reading and storing the pull-down path from the port to VDD from the pad circuit The configuration of the port; and a second storage unit connected to the pad circuit for reading and storing the configuration of the port when the port is pulled down from the pad circuit to GND; After the pad circuit switches the pull-up path and the pull-down path through the first and second switches, the storage values of the first storage unit and the second storage unit will generate three storage values due to the three possible states of port connection The combination can be used to identify multiple definitions in a port.

In the above embodiment of the present invention, the first and second switches are kept at The open circuit state in the preset state, and the first and second storage units remain in the disabled state in the preset state when they are not driven.

In the above-mentioned embodiment of the present invention, the pad circuit pulls the circuit above the connection port to VDD When it is in a short-circuit state, the first switch is in a short-circuit state, the first storage unit is in an enabled state, and the second switch is in a disconnected state, and the second storage unit is in a non-enabled state. A storage unit will read and store the port configuration.

In the above embodiment of the present invention, the pad circuit is connected to the pull-down path from the port to GND When running, the first switch is in an open state, the first storage unit is in an inactive state, and the second switch is in a short-circuit state, and the second storage unit is in an enabled state. At this time, the second storage unit The port configuration will be read and stored.

In the above embodiment of the present invention, the power current limiter and the ground current limiter may be electrical Resistance, diode (Diode), or current source.

In the above embodiment of the present invention, the first storage unit and the second storage unit may be Latch, register, capacitor, or memory.

Please refer to "Figure 1 to Figure 3", which are the three-state digital structure of the present invention. Schematic diagram of the configuration circuit, schematic diagram of the circuit in which the ternary digital structure of the present invention is applied in the pull-up state, and schematic diagram of the circuit in which the ternary digital structure of the present invention is applied in the pull-down state. As shown in the figure: the present invention is a three-state digital structure, which includes a pad circuit 1, a first storage unit (Storage Unit) 2, and a second storage unit 3.

The aforementioned pad circuit 1 includes a first switch 11 and a power supply A current limiter (Current Limiter) 12 is coupled between VDD and the first switch 11, a second switch 13 and a ground current limiter 14 are coupled between GND and the second switch 13 And the first and second switches 11 and 13 are connected to a port (port) 4, where a port Three configurations can be determined under 4, which are VDD, GND and FLOAT respectively. The power current limiter 12 is the power current limiter for the pull-up of the port 4. The ground The current limiter 14 is a ground current limiter for the pull down of the port 4, and the pad circuit 1 has a pull-down path from the port 4 to VDD and a pull-down path from the port 4 to GND.

The first storage unit 2 is connected to the pad circuit 1 for switching from the pad circuit 1 The configuration of the port 4 when reading and storing the pull-up path of the port 4 to VDD.

The second storage unit 3 is connected to the pad circuit 1 for switching from the pad circuit 1 The configuration of the port 4 when reading and storing the pull-down path of the port 4 to GND. After the pad circuit 1 switches the pull-up path and the pull-down path through the first and second switches 11, 13, the stored values of the first storage unit 2 and the second storage unit 3 will be connected to port 4 There are three possible states, and three combinations of stored values can be generated to identify multiple definitions in a port 4. If so, a new three-state digital structure is formed by the structure disclosed above.

At the beginning, the first and second switches (SW1, SW2) 11, 13 are not driven Keep in the default state of disconnection during operation to avoid current consumption, while the first and second storage units (Storage Unit1, Storage Unit2) 2, 3 remain in the default state when they are not driven. (Disabled) state, no program is executed, as shown in Figure 1.

When the first control is performed, that is, when the pad circuit 1 is switched to the pull-up path from port 4 to VDD through the first switch 11, the first switch 11 is in a short-circuit state, and the first storage unit 2 is in a consistent state. In the enabled state, and the second switch 13 is in the disconnected state, the second storage unit 3 is in the disabled state and no program is executed. At this time, the configuration of the port 4 will be directly controlled by the first storage unit 2 Read and store. If the connection status of the port 4 is read as VDD, the first storage unit 2 is stored as 1, if the connection status of the port 4 is read as GND, the first storage unit 2 is stored as 0. If the connection status of the port 4 is read as FLOAT, the first storage unit 2 is stored as 1, as shown in Figure 2 and Table 1. Table I Port status VDD GND FLOAT First storage unit 1 0 1

When the second control is performed, that is, when the pad circuit 1 is switched to the pull-down path from port 4 to GND through the second switch 13, the first switch 11 is in an open state, and the first storage unit 2 is not activated. No program is executed, and the second switch 13 is in the short-circuit state, and the second storage unit 3 is in the enabled state. At this time, the configuration of the port 4 will be directly read by the second storage unit 3 and Store, if the connection status of the port 4 is read as VDD, the second storage unit 3 is stored as 1, if the connection status of the port 4 is read as GND, the second storage unit 3 is stored as 0, and if When the connection status of the port 4 is read as FLOAT, the second storage unit 3 is stored as 0, as shown in Figure 3 and Table 2. Table II Port status VDD GND FLOAT Second storage unit 1 0 0

When the pad circuit 1 switches the pull-up path through the first switch 11, the connection status of the port 4 can be directly read and stored through the first storage unit 2. When the pad circuit 1 switches the pull-down path through the second switch 13 At this time, the connection status of port 4 can be directly read and stored through the second storage unit 3. At this time, it can be found that there are three possible combinations for the storage values of the first storage unit 2 and the second storage unit 3. If the connection status is VDD It must be stored as 1, when it is GND, it must be stored as 0, if it is FLOAT, it is 1 and 0, so as long as you look at the combination of the first and second storage units shown in Table 3, you can know the current The port is connected to VDD, GND or FLOAT, and multiple definitions in a port can be determined by the combination of different storage unit 1 and storage unit 2 storage values. Table Three Port status VDD GND FLOAT The first storage unit (pull up) 1 0 1 Second storage unit (drop down) 1 0 0

The present invention uses the circuit characteristics of pull-up and pull-down to identify the connection status of the port, which is advantageous With this technology, a port can be used to determine multiple definitions through the three states of GND, VDD, and FLOAT.

If the switch switches the pad circuit to a pull-up power current limiter structure, the pull-up The power current limiter can protect the port, which can be used to identify the current connection state of the port is GND.

If the switch switches the pad circuit to a pull-down ground current limiter structure, the pull-down The ground current limiter can protect the port, which can be used to identify the current connection status of the port is VDD.

If the port is not connected to VDD or GND, it will be FLOAT.

Therefore, the three-state digital structure provided by the present invention has three states: GND, VDD, and FLOAT. When designing the chip, as long as you set up two current limiters inside, such as resistors, diodes, current sources, etc., two switches and two storage units, such as latches, Registers, capacitors, memory, etc., can have fewer ports than traditional technology. One port can have three states. Compared with the traditional one port can only have two states, the present invention only needs to be One connection port and two more storage units can be connected to this pad circuit to achieve three states. In this way, one pad can be saved and the space and cost of the chip can be saved.

In summary, the present invention is a three-state digital structure, which can effectively improve the conventional The disadvantage is that the circuit characteristics of pull up (Pull Up) and pull down (Pull Down) are used to identify the connection state of the port (port). Using this technology, a port can pass through the ground (GND), voltage (VDD) and empty The three states of FLOAT determine multiple definitions, so that one pad can be saved, and the space and cost of the chip can be saved, so that the production of the present invention can be more advanced, more practical, and more in line with the needs of users. In accordance with the requirements of an invention patent application, Yan filed a patent application in accordance with the law.

However, the above are only the preferred embodiments of the present invention and should not be limited by this The scope of implementation of the present invention; therefore, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the description of the invention should still fall within the scope of the patent of the present invention.

1: Connection pad circuit １１: The first switch 12: Power current limiter 13: The second switch 14: Grounding current limiter 2: The first storage unit 3: The second storage unit 4: Port

Figure 1 is a schematic diagram of the three-state digital structure circuit of the present invention. Figure 2 is a schematic diagram of the circuit in which the ternary digital structure of the present invention is applied in the pull-up state. Figure 3 is a schematic diagram of the circuit in which the ternary digital structure of the present invention is applied in the pull-down state.

1: pad circuit

11: The first switcher

12: Power current limiter

13: The second switcher

14: Ground current limiter

2: The first storage unit

3: The second storage unit

4: Port

Claims (6)

A three-state digital structure, including: A pad circuit including a first switch, a current limiter (Current Limiter), coupled between VDD and the first switch, a second switch, and a ground current limiter , Coupled between the GND and the second switch, and the first and second switches are connected to a port (port). Three configurations can be determined under this port, namely VDD and GND And FLOAT three states, and the power current limiter is the power current limiter of the port's pull up (Pull Up), and the ground current limiter is the ground limit of the port's pull down (Pull Down) A converter, the pad circuit has a pull-up path from the port to VDD and a pull-down path from the port to GND; A first storage unit (Storage Unit) connected to the pad circuit for reading and storing the configuration of the port when the port is pulled up to VDD from the pad circuit; and A second storage unit connected to the pad circuit for reading and storing the configuration of the port when the port is pulled down from the pad circuit to GND; After the pad circuit switches the pull-up path and the pull-down path through the first and second switches, the stored values of the first storage unit and the second storage unit will generate three types of storage due to the three possible states of port connection A combination of values can be used to identify multiple definitions in a port. According to the three-state digital structure described in item 1 of the scope of patent application, the first and second switches are kept in the open state in the preset state when they are not driven, and the first and second storage units are not When driving, it remains in the disabled state under the preset state. According to the three-state digital structure described in item 1 of the scope of patent application, when the pad circuit is in the pull-up path from the port to VDD, the first switch is in a short-circuit state, and the first storage unit is enabled (Enabled) state, and the second switch is in a disconnected state, and the second storage unit is in an inactive state. At this time, the first storage unit will read and store the port configuration. According to the three-state digital structure described in item 1 of the scope of patent application, when the pad circuit is in the pull-down path from the port to GND, the first switch is in an open state, and the first storage unit is disabled State, and the second switch is in a short-circuit state, and the second storage unit is in an enabled state. At this time, the second storage unit will read and store the port configuration. According to the three-state digital structure described in item 1 of the scope of patent application, the power current limiter and the ground current limiter can be resistors, diodes, or current sources. According to the three-state digital structure described in item 1 of the scope of patent application, the first storage unit and the second storage unit can be latches, registers, capacitors, or memory.

Images