TWI830608B - Generic interface system and control method thereof - Google Patents

Abstract

A generic interface system and its control method are disclosed. The generic interface system comprises a transmission interface, a power supply module, a power switch module, a first control module, a detection module, and a second control module. The transmission interface is configured to send a first power and a second power to an external electronic device, and receive a first answer signal, a second answer signal, and a third answer signal sent by the external electronic device. The power supply module is configured to generate the first power and the second power. The power switch module is configured to turn-on the line between the transmission interface and the power supply module according to a control signal. The first control module is configured to generate the control signal to control the power switch module. The detection module is configured to receive the first answer signal, and detect whether the external electronic device exists according to the first answer signal.

Description

Universal interface system and control method

The present invention relates to solid state hard disks, and in particular to a universal interface system suitable for solid state hard disks and a control method thereof.

NF1 solid state drive (SSD) is a solid state drive specification launched by Samsung Electronics in 2017 for new generation data centers. At first, NF1 was called Next Generation Small Form Factor (NGSFF), later it was commonly known as M.3, and it is currently named NF1. The main purpose of Samsung Electronics' NF1 SSD is to achieve the best balance between the size and capacity of the SSD, thereby creating a SSD with the best quality and highest performance.

Compared with traditional M.2 solid-state drives, NF1 solid-state drives have three advantages: First, NF1 solid-state drives have a larger printed circuit board (PCB) area to accommodate more flash memory (Flash memory). ), so that the capacity of NF1 solid-state drive can reach more than 2 to 4 times that of M.2 solid-state drive; secondly, NF1 solid-state drive follows the connector structure of M.2 solid-state drive, and adds enterprise use The functions of the solid-state drive (such as dual-channel options, 12-volt power supply and power-off function, etc.); third, the NF1 solid-state drive supports hot swap function.

Since NF1 SSDs follow the connector structure of M.2 SSDs, NF1 SSDs can be inserted into systems that only support M.2 SSDs, and M.2 SSDs can also be inserted into systems that only support M.2 SSDs. NF1 solid state drive system. However, due to the different pin definitions between M.2 SSDs and NF1 SSDs, when an M.2 SSD is inserted into a system that only supports NF1 SSDs, the system that only supports NF1 SSDs will The high-voltage power supply in the M.2 solid-state drive will cause damage to the M.2 solid-state drive; conversely, when the NF1 solid-state drive is inserted into a system that only supports M.2 solid-state drives, the NF1 solid-state drive will not be affected by the high-voltage power supply. cause damage.

In view of this, the present invention proposes a universal interface system, including: a transmission interface for sending a first power supply and a second power supply to an external electronic device, and receiving a first response sent by the external electronic device. signal, a second response signal and a third response signal; a power supply module electrically connected to the transmission interface for generating the first power supply and the second power supply; a power switch module configured Between the transmission interface and the power supply module, it is used to selectively conduct the line between the transmission interface and the power supply module according to a control signal; a first control module, electrically connected The transmission interface and the power switch module are used to generate the control signal to control the power switch module, and the first control module is further used to execute the firmware of the external electronic device. body; a detection module, electrically connected to the transmission interface and the first control module, for detecting the first response signal to determine whether the external electronic device exists, and for detecting The second response signal and the third response signal are used to determine whether the external electronic device is a solid state drive, wherein the solid state drive is selected from an NF1 solid state drive or an M.2 solid state drive; and a The second control module is electrically connected to the first control module and is used to store the firmware of the external electronic device.

In some embodiments, the detection module is electrically connected to the fifty-second pin (PIN52) of the transmission interface.

In some embodiments, the detection module is electrically connected to a sixth pin (PIN6) and a twenty-sixth pin (PIN26) of the transmission interface.

In some embodiments, the voltage value of the first power supply is 3.3 volts.

In some embodiments, when the detection module detects that the external electronic device is an M.2 solid state drive, the first power supply is through a second pin (PIN2) of the transmission interface , - the fourth pin (PIN4), - the twelfth pin (PIN12), - the fourteenth pin (PIN14), - the sixteenth pin (PIN16), - the eighteenth pin pin (PIN18), a seventieth pin (PIN70), a seventy-second pin (PIN72) and a seventy-fourth pin (PIN74) are transmitted to the external electronic device.

In some embodiments, when the detection module detects that the external electronic device is an NF1 solid state drive, the second power supply is through one of the thirtieth pin (PIN30) of the transmission interface. A thirty-second pin (PIN32), a thirty-fourth pin (PIN34) and a thirty-sixth pin (PIN36) are sent to the external electronic device, and the second power supply The voltage value is 12 volts.

The present invention also proposes a universal interface system control method, which includes: sending a first power supply; detecting a first response signal to determine whether an external electronic device exists, wherein the first response signal is received by the external electronic device. Send; when the external electronic device exists, detect a second response signal and a third response signal sent by the external electronic device to determine whether the external electronic device is a solid-state hard drive, wherein the solid-state drive The hard drive is selected from NF1 solid state drive or M.2 solid state drive; and when the external electronic device is a solid state drive, execute the firmware of the external electronic device and control a power switch module to conduct, so that all The first power supply or a second power supply is sent to the external electronic device.

Please refer to FIG. 1 , which is a module block diagram of the universal interface system 10 in one embodiment of the present invention. In some embodiments, the universal interface system 10 is a computer system, a motherboard in a server system, a backplane or a riser card, etc., which has a slot for inserting a solid state drive. Slotted circuit boards are not limited to this. As shown in Figure 1, the universal interface system 10 includes a transmission interface 100, a power supply module 110, a power switch module 120, a first control module 130, a detection module 140 and a second control module 150. The power supply module 110 is electrically coupled to the transmission interface 100, the power switch module 120 is disposed between the transmission interface 100 and the power supply module 110, and the first control module 130 is electrically connected to the transmission interface 100 and the power switch module. In group 120, the detection module 140 is electrically connected to the transmission interface 100 and the first control module 130, and the second control module 150 is electrically connected to the first control module 130. The structure and function of the transmission interface 100, the power supply module 110, the power switch module 120, the first control module 130, the detection module 140 and the second control module 150 will be explained in detail below, and the settings of each other will also be described. Way.

The transmission interface 100 is used to transmit a first power source V1 and a second power source V2 to an external electronic device to provide power required for the operation of the external electronic device, and receive a first response signal sent by the external electronic device. Van1, a second response signal Van2 and a third response signal Van3. In some embodiments, the transmission interface 100 of the universal interface system 10 conforms to the connector structure of the M.2 solid-state drive (for example, a gold finger slot suitable for the M.2 solid-state drive). Therefore, the external electronic device with a corresponding connector structure of the M.2 solid state drive (such as an M.2 solid state drive or an NF1 solid state drive with a golden finger of the M.2 solid state drive) can be selected electrically connected to the universal interface system 10 , for example, plugged into the universal interface system 10 .

Please refer to FIGS. 2A and 2B at the same time. FIGS. 2A and 2B are pin definition diagrams of M.2 solid-state drives and NF1 solid-state drives in one embodiment of the present invention. As shown in Figure 2A and Figure 2B, the connector structure of the M.2 solid-state drive and the connector structure of the NF1 solid-state drive both include seventy-five pins. Among them, the functions defined by each pin in M.2 solid-state drives and NF1 solid-state drives are slightly different. Taking the seventy-fourth pin (PIN74) as an example, PIN74 of the M.2 solid-state drive is used to transmit a 3.3-volt signal, while PIN74 of the NF1 solid-state drive has an undefined function (N/C).

The power supply module 110 is used to generate the first power supply V1 and the second power supply V2. In some embodiments, the power supply module 110 is used to provide power for each circuit in the universal interface system 10 and to provide power for the external electronic device, wherein the first power supply V1 and the second power supply V2 are the external electronic devices. Electricity consumption of electronic devices. In some embodiments, the voltage value of the first power supply V1 is 3.3 volts, where 3.3 volts is the operating voltage (Operating voltage) of the M.2 solid state drive. In some embodiments, the voltage value of the second power supply V2 is 12 volts, where 12 volts is the operating voltage of the NF1 solid state drive.

The power switch module 120 is used to selectively conduct the line between the transmission interface 100 and the power supply module 110 according to a control signal Vc. Please refer to FIG. 3 , which is a schematic circuit diagram of the power switch module 120 in one embodiment of the present invention. As shown in FIG. 3 , the power switch module 120 includes a plurality of switches Q1 and Q2. Among them, the switch Q1 is set between the power pin group Spp of the transmission interface 100 and the power supply module 110, and the switch Q2 is set between the plurality of pins 101, 102, 103, 104 of the transmission interface 100 and the power supply module 110. . In some embodiments, the power pin group Spp includes a second pin (PIN2), a fourth pin (PIN4), a twelfth pin (PIN12), a tenth pin of the transmission interface 100 Four pins (PIN14), one sixteenth pin (PIN16), one eighteenth pin (PIN18), one seventieth pin (PIN70), one seventy-second pin ( PIN72) and one seventy-fourth pin (PIN74).

In some embodiments, the switch Q1 is used to control the supply of the first power supply V1. When the switch Q1 is turned on, the switch Q1 is electrically connected to the first power supply V1. At this time, the power supply module 110 can provide the first power supply V1 to all pins in the power pin group Spp. When the switch Q1 is not conducting, the switch Q1 is not electrically connected to the first power supply V1. At this time, the power supply module 110 is unable to provide the first power supply V1 to all the pins in the power pin group Spp.

In some embodiments, the switch Q2 is used to control the supply of the second power supply V2. When the switch Q2 is turned on, the power supply module 110 can provide the second power supply V2 to the plurality of pins 101, 102, 103, and 104 of the transmission interface 100; when the switch Q2 is not turned on, the power supply module 110 cannot provide the second power supply. V2 is connected to the plurality of pins 101, 102, 103, and 104 of the transmission interface 100.

The first control module 130 is used to generate the control signal Vc to control the power switch module 120 . As shown in FIG. 3, the control signal Vc includes a first control signal Vc1 and a second control signal Vc2. In some embodiments, the first control signal Vc1 is used to control the switch Q1, and the second control signal Vc2 is used to control the switch Q2. Among them, when the first control signal Vc1 is a first logic level signal, the switch Q1 is turned on so that the first power V1 can be provided to the transmission interface 100; when the first control signal Vc1 is a second logic level signal At this time, the switch Q1 is not conductive so that the first power supply V1 cannot be provided to the transmission interface 100 . Wherein, when the voltage value of the second control signal Vc2 is at the first logic level signal, the switch Q2 is turned on so that the second power V2 can be provided to the transmission interface 100; when the voltage value of the second control signal Vc2 is at When the second logic level signal is present, the switch Q2 is not conductive, so that the second power supply V2 cannot be provided to the transmission interface 100 .

In some embodiments, both the switch Q1 and the switch Q2 are controlled by the first control signal Vc1. Wherein, when the first control signal Vc1 is the first logic level signal, the switch Q1 is turned on and the switch Q2 is not turned on; when the first control signal Vc1 is the second logic level signal, the switch Q1 is turned on. There is no conduction and switch Q2 is conductive.

In some embodiments, both the switch Q1 and the switch Q2 are controlled by the second control signal Vc2. Wherein, when the second control signal Vc2 is the first logic level signal, the switch Q1 is not turned on and the switch Q2 is turned on; when the second control signal Vc2 is the second logic level signal, the switch Q1 is turned on. is turned on and switch Q2 is not turned on.

In some embodiments, the first logic level signal is a high logic level signal representing 1 (for example, 3.3 volts, or other voltage levels such as 5 volts or 12 volts, but is not limited thereto) , and the second logic level signal is a low logic level signal representing 0 (for example, 0 volts, or other voltage levels such as 0.1 volts or 0.5 volts, but is not limited to this). In other embodiments, the first logic level signal is the low logic level signal, and the second logic level signal is the high logic level signal.

The detection module 140 is used to detect the first response signal Van1 to determine whether the external electronic device exists, that is, to detect and determine whether the external electronic device is electrically connected to the universal interface system 10 through the transmission interface 100 . In addition, the detection module 140 is further used to detect the second response signal Van2 and the third response signal Van3 to further determine whether the external electronic device electrically connected to the universal interface system 10 through the transmission interface 100 is a solid-state hard drive. disk, wherein the solid state drive is selected from NF1 solid state drive or M.2 solid state drive. Please refer to FIG. 4 , which is a schematic circuit diagram of the detection module 140 in one embodiment of the present invention. As shown in FIG. 4 , in some embodiments, the detection module 140 includes complex resistors R1, R2, R3 and a logic module 141. Among them, the resistor R1 is set between the pin 105 and the first control module 130, the resistor R2 is set between the pin 106 and the logic module 141, and the resistor R3 is set between the pin 107 and the logic module. Between the groups 141, the logic module 141 is disposed between the resistors R2, R3 and the first control module 130. In some embodiments, the logic module 141 is, for example, but not limited to, an AND gate, an NAND gate, a comparator, other logic elements, or a combination of at least two of the above logic elements.

In some embodiments, the detection module 140 detects the first response signal Van1 through the resistor R1 to determine whether the external electronic device exists, and pulls the second response signal Van2 and the third response signal Van2 through the resistors R2 and R3 respectively. The response signal Van3 is detected through the logic module 141 to detect the second response signal Van2 and the third response signal Van3 to determine whether the external electronic device is an M.2 solid state drive or an NF1 solid state drive. In some embodiments, the logic module 141 has two input terminals and one output terminal. One input terminal of the logic module 141 is electrically connected to the resistor R2, and the other input terminal of the logic module 141 is electrically connected to the resistor R2. Resistor R3, the output terminal of the logic module 141 is electrically connected to the first control module 130. When the signals received by the two input terminals are both a third logic level signal, the output terminal outputs a fourth logic level signal (corresponding to the detection signal Vd); when the two input terminals When at least one of the received signals is a fifth logic level signal, the output terminal outputs a sixth logic level signal (corresponding to the detection signal Vd).

In some embodiments, when the logic module 141 is, for example, an AND gate, the third logic level signal is a high logic level signal representing 1, and the fourth logic level signal is a high logic bit representing 1. The fifth logic level signal is a low logic level signal representing 0, and the sixth logic level signal is the low logic level signal. That is to say, when the signals received by the two input terminals are both the high logic level signal, the output terminal outputs the high logic level signal; when the signals received by the two input terminals are When at least one of the signals is the low logic level signal, the output terminal outputs the low logic level signal.

In some embodiments, when the logic module 141 is, for example, an NAND gate, the third logic level signal is the high logic level signal, and the fourth logic level signal is the low logic level. signal, the fifth logic level signal is the low logic level signal, and the sixth logic level signal is the high logic level signal. That is to say, when the signals received by the two input terminals are both the high logic level signal, the output terminal outputs the low logic level signal; when the signals received by the two input terminals are When at least one of the signals is the low logic level signal, the output terminal outputs the high logic level signal.

It should be noted that the following is a AND gate as an example to illustrate the function of the logic module 141 and further explain the operation of the detection module 140 .

In some embodiments, pin 105 is the fifty-second pin (PIN52) of the transmission interface 100, and the first response signal Van1 is the signal transmitted by PIN52 of the transmission interface 100 in Figure 2B. Please refer to Table 1. Table 1 is a definition table of PIN52, PIN26, and PIN6 in M.2 solid-state drives and NF1 solid-state drives in one embodiment of the present invention (corresponding to Figure 2B). As shown in Table 1, PIN52 of the M.2 SSD is used to transmit a high logic level signal, and PIN52 of the NF1 SSD is also used to transmit a high logic level signal. Therefore, in some embodiments, when the detection module 140 detects that the signal transmitted by PIN52 of the transmission interface 100 (ie, the first response signal Van1) is a high logic level signal, it means that the external electronic device is Universal Interface System 10 exists. That is to say, the external electronic device is electrically connected to the universal interface system 10 , such as being inserted into the universal interface system 10 , or electrically connected to the transmission interface 100 through a cable, and then electrically connected to the universal interface system 10 . When the detection module 140 does not detect any signal transmitted by the PIN 52 of the transmission interface 100 , it means that the external electronic device does not exist for the universal interface system 10 . That is to say, the external electronic device is not directly or indirectly electrically connected to the universal interface system 10 , for example, it is not electrically connected to/plugged into the universal interface system 10 . [Table 1] PIN NF1 solid state drive M.2 SSD 52 High logic level signal High logic level signal 26 low logic level signal High logic level signal 6 low logic level signal High logic level signal

In some embodiments, pin 106 is the twenty-sixth pin (PIN26) of the transmission interface 100, and pin 107 is the sixth pin (PIN6) of the transmission interface 100, wherein the second response signal Van2 It is the signal transmitted by PIN26 of the transmission interface 100 in Figure 2B. The third response signal Van3 is the signal transmitted by PIN6 of the transmission interface 100 in Figure 2B. As shown in Table 1, PIN26 of the NF1 SSD is used to transmit a low logic level signal, while PIN26 of the M.2 SSD is used to transmit a high logic level signal; PIN6 of the NF1 SSD is used to transmit A low logic level signal, while PIN6 of the M.2 solid state drive is used to transmit a high logic level signal. Therefore, in some embodiments, when the external electronic device is an NF1 solid state drive, the second response signal Van2 is a low logic level signal and the third response signal Van3 is also a low logic level signal. At this time The logic module 141 outputs a low logic level detection signal Vd according to the second response signal Van2 and the third response signal Van3; when the external electronic device is an M.2 solid state drive, the second response signal Van2 is a high logic level signal and the third response signal Van3 is also a high logic level signal. At this time, the logic module 141 outputs a high logic level signal based on the second response signal Van2 and the third response signal Van3. Test signal Vd. In other words, when the detection signal Vd output by the logic module 141 is a low logic level signal, it means that the external electronic device is an NF1 solid state drive; when the detection signal Vd output by the logic module 141 is A high logic level signal indicates that the external electronic device is an M.2 solid state drive.

The second control module 150 is used to store the firmware of the external electronic device. As mentioned above, the external electronic device (such as M.2 solid state drive or NF1 solid state drive) with the corresponding M.2 solid state drive connector structure can be plugged into the M.2 solid state drive. The transmission interface 100 of the universal interface system 10 of the disk connector structure. However, the universal interface system 10 must have the firmware of the external electronic device in order to support the functions of the external electronic device. Take M.2 solid-state drives as an example. Since M.2 solid-state drives have the second-generation Universal Serial Bus (USB 2.0) function, USB 2.0 firmware must be present in Universal Interface System 10 to support M. 2 solid state drives. Taking the NF1 solid state drive as an example, since the NF1 solid state drive has a dual-channel option, the firmware with the dual-channel option must be present in Universal Interface System 10 to support the NF1 solid-state drive. Therefore, in some embodiments, when the external electronic device is electrically connected to the universal interface system 10, the first control module 130 executes the firmware of the external electronic device stored in the second control module 150, The universal interface system 10 is caused to support the functions of the external electronic device.

Please refer to FIGS. 1 to 5 . FIG. 5 is an operation flow chart of the universal interface system 10 in one embodiment of the present invention. As shown in FIG. 5 , when the universal interface system 10 starts to operate, the power supply module 110 of the universal interface system 10 sends a first power supply V1 through the power pin group Spp of the transmission interface 100 (step S100 ). Next, the detection module 140 of the universal interface system 10 detects the signal transmitted by the pin 105 of the transmission interface 100 (ie, the first response signal Van1) to determine whether the external electronic device exists (step S110). If the external electronic device does not exist, the universal interface system 10 turns off the power supply module 110 (step S120) to save power; if the external electronic device exists, the detection module 140 detects the transmission interface 100. The second response signal Van2 transmitted by the pin 106 and the third response signal Van3 transmitted by the pin 107 of the transmission interface 100 are used to determine whether the external electronic device is a solid state drive (step S130), wherein the solid state drive The system can be selected from NF1 SSD or M.2 SSD. If the external electronic device is not a solid state drive, the universal interface system 10 turns off the power supply module 110 (step S120) to avoid incompatibility problems that may cause damage to the external electronic device or the universal interface system 10; if The external electronic device is a solid state hard drive. The first control module 130 of the universal interface system 10 executes the firmware of the external electronic device and controls the power switch module 120 of the universal interface system 10 to turn on, so that the first power supply V1 Or the second power V2 is sent to the external electronic device (step S140 ), where the firmware of the external electronic device is stored in the second control module 150 .

In some embodiments, when the detection module 140 detects that the external electronic device is an NF1 solid-state drive, the second power supply V2 is connected through one of the thirtieth pin (PIN30) and a third pin of the transmission interface 100. Twelve pins (PIN32), a thirty-fourth pin (PIN34) and a thirty-sixth pin (PIN36) are sent to the external electronic device, of which pin 101 is the transmission interface 100 PIN30, pin 102 is the PIN32 of the transmission interface 100, pin 103 is the PIN34 of the transmission interface 100, and pin 104 is the PIN36 of the transmission interface 100. As shown in Figure 2B, PIN30, PIN32, PIN34, and PIN36 of the NF1 solid-state drive are used to transmit 12-volt signals. Therefore, when the NF1 solid state drive is plugged into the universal interface system 10, the universal interface system 10 sends the second power supply V2 of 12 volts to PIN30, PIN32, PIN34, and PIN36 of the NF1 solid state drive, so that the NF1 solid state drive can normal operation.

In some embodiments, when the detection module 140 detects that the external electronic device is an M.2 solid state drive, the first power V1 is transmitted to the external electronic device through the power pin set Spp of the transmission interface 100 . As shown in Figure 2B, PIN2, PIN4, PIN12, PIN14, PIN16, PIN18, PIN70, PIN72, and PIN74 of the M.2 solid-state drive are used to transmit 3.3 volt signals. Therefore, when the M.2 solid-state drive is plugged into the universal interface system 10, the universal interface system 10 sends the first power supply V1 of 3.3 volts to the PIN2, PIN4, PIN12, PIN14, PIN16, PIN18, PIN70, PIN72, and PIN74 enable the M.2 solid-state drive to operate normally.

Please refer to Figure 6, which is a module block diagram of the universal interface system 10' in another embodiment of the present invention. As shown in Figure 6, in some embodiments, the architecture of the universal interface system 10' is substantially the same as the architecture of the universal interface system 10 shown in Figure 1. The difference between the two is that the universal interface system 10' will be universal The first control module 130 and the detection module 140 of the interface system 10 are integrated into a first control module 130'. In some embodiments, the first control module 130 and the first control module 130' are complex programmable logic devices (Complex Programmable Logic Device, CPLD), programmable logic devices (Programmable Logic Device, PLD), field Components that can execute programming programs such as Field Programmable Gate Array (FPGA) or Microcontroller Unit (MCU) are not limited to this. Therefore, the universal interface system 10' can realize the functions of the first control module 130 and the detection module 140 in Figure 1 through the first control module 130'.

To sum up, according to some embodiments of the universal interface system 10, when an external electronic device is plugged into the universal interface system 10, the universal interface system 10 detects the signal transmitted by the specific pin of the transmission interface 100, This is used to determine whether the external electronic device is an NF1 solid state drive or an M.2 solid state drive, thereby preventing the universal interface system 10 from providing erroneous power and causing damage to the external electronic device.

Although the present invention has been disclosed in the above embodiments, they are not intended to limit the creation of the present invention. Anyone with ordinary skill in the art may make slight modifications and modifications without departing from the spirit and scope of the disclosure. changes, but these slight modifications and changes are still within the patentable scope of the present invention.

10: Universal interface system 10’: Universal interface system 100:Transmission interface 101~107: Pin 110:Power supply module 120:Power switch module 130:First control module 130’: First control module 140:Detection module 141: Logic module 150: Second control module Q1: switch Q2: switch R1~R3: resistor S100~S140: steps Spp: power pin group V1: first power supply V2: Second power supply Van1: first response signal Van2: second response signal Van3: The third response signal Vc: control signal Vc1: first control signal Vc2: second control signal Vd: detection signal

Figure 1 is a module block diagram of a universal interface system in one embodiment of the present invention. FIG. 2A is a pin definition diagram (1) of an M.2 solid-state drive and an NF1 solid-state drive in an embodiment of the present invention. Figure 2B is a pin definition diagram (2) of the M.2 solid state drive and the NF1 solid state drive in one embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a power switch module in one embodiment of the present invention. FIG. 4 is a schematic circuit diagram of a detection module in an embodiment of the present invention. Figure 5 is an operation flow chart of the universal interface system in one embodiment of the present invention. FIG. 6 is a module block diagram of a universal interface system in another embodiment of the present invention.

10: Universal interface system

100:Transmission interface

101~107: Pin

110:Power supply module

120:Power switch module

130:First control module

140:Detection module

150: Second control module

V1: first power supply

V2: Second power supply

Van1: first response signal

Van2: second response signal

Van3: The third response signal

Vc: control signal

Claims (10)

A common interface system that includes: a transmission interface for sending a first power supply and a second power supply to an external electronic device, and receiving a first response signal, a second response signal and a third response signal sent by the external electronic device; a power supply module electrically coupled to the transmission interface for generating the first power supply and the second power supply; A power switch module is disposed between the transmission interface and the power supply module to selectively conduct the line between the transmission interface and the power supply module according to a control signal; A first control module, electrically connected to the transmission interface and the power switch module, for generating the control signal to control the power switch module, and for executing the firmware of the external electronic device; A detection module, electrically connected to the transmission interface and the first control module, is used to detect the first response signal to determine whether the external electronic device exists, and is used to detect the second response signal and The third response signal is used to determine whether the external electronic device is a solid state drive, wherein the solid state drive is selected from NF1 solid state drive or M.2 solid state drive; and A second control module, electrically connected to the first control module, is used to store the firmware of the external electronic device. The universal interface system as described in claim 1, wherein the detection module is electrically connected to one of the fifty-second pins (PIN52) of the transmission interface. The universal interface system as described in claim 1, wherein the detection module is electrically connected to a sixth pin (PIN6) and a twenty-sixth pin (PIN26) of the transmission interface. The universal interface system as claimed in claim 1, wherein the voltage value of the first power supply is 3.3 volts. The universal interface system as described in claim 4, wherein when the detection module detects that the external electronic device is an M.2 solid state drive, the first power supply is through one of the second pins of the transmission interface ( PIN2), a fourth pin (PIN4), a twelfth pin (PIN12), a fourteenth pin (PIN14), a sixteenth pin (PIN16), a eighteenth pin A pin (PIN18), a seventieth pin (PIN70), a seventy-second pin (PIN72) and a seventy-fourth pin (PIN74) are transmitted to the external electronic device. The universal interface system as described in claim 1, wherein when the detection module detects that the external electronic device is an NF1 solid-state drive, the second power supply is through one of the thirtieth pin (PIN30) of the transmission interface. ), a thirty-second pin (PIN32), a thirty-fourth pin (PIN34) and a thirty-sixth pin (PIN36) are transmitted to the external electronic device, and the second power supply The voltage value is 12 volts. A universal interface system control method, including: Send a first power source; Detect whether a first response signal is received from an external electronic device to determine whether the external electronic device exists, wherein the first response signal is sent when the external electronic device receives the first power supply; When the external electronic device exists, detect a second response signal and a third response signal sent by the external electronic device to determine whether the external electronic device is a solid state drive, wherein the solid state drive is selected from NF1 Solid state drive or M.2 solid state drive; and When the external electronic device is a solid-state hard drive, the firmware of the external electronic device is executed and a power switch module is controlled to be turned on, so that the first power supply or the second power supply is transmitted to the external electronic device. The universal interface system control method as described in claim 7, wherein the voltage value of the first power supply is 3.3 volts. The universal interface system control method as described in claim 8, wherein when a detection module detects that the external electronic device is an M.2 solid state drive, the first power supply is through a second driver of a transmission interface. pin (PIN2), a fourth pin (PIN4), a twelfth pin (PIN12), a fourteenth pin (PIN14), a sixteenth pin (PIN16), a Eighteen pins (PIN18), one seventieth pin (PIN70), one seventy-second pin (PIN72), and one seventy-fourth pin (PIN74) are transmitted to the external electronic device. The universal interface system control method as described in claim 7, wherein when a detection module detects that the external electronic device is an NF1 solid state drive, the second power supply is through a thirty-second pin of a transmission interface (PIN30), a thirty-second pin (PIN32), a thirty-fourth pin (PIN34) and a thirty-sixth pin (PIN36) are transmitted to the external electronic device, and the second The voltage value of the power supply is 12 volts.

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