TWI831326B - Memory module - Google Patents
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- TWI831326B TWI831326B TW111130447A TW111130447A TWI831326B TW I831326 B TWI831326 B TW I831326B TW 111130447 A TW111130447 A TW 111130447A TW 111130447 A TW111130447 A TW 111130447A TW I831326 B TWI831326 B TW I831326B
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Abstract
Description
本案關於一種記憶體模組,尤指一種接收線性電能的記憶體模組。This case relates to a memory module, especially a memory module that receives linear power.
通常,記憶體模組僅具有單一輸入端口,且須利用單一輸入端口同時接收訊號及電能,而為了同時接收訊號及電能,傳統記憶體模組所接收的電能通常為交換式電源(switching power supply)所提供的交換式電能。然而,由於傳統記憶體模組所接收的交換式電能係利用電子零件的高速切換而進行變壓,造成其具有波動較大的特性,因此交換式電能造成的雜訊較高,而使記憶體模組接收交換式電能時的雜訊亦較高,進而造成傳統記憶體模組的穩定性較低且頻率較低。Usually, a memory module only has a single input port and must use a single input port to receive signals and power at the same time. In order to receive signals and power at the same time, the power received by a traditional memory module is usually a switching power supply. ) provided by the exchange of electrical energy. However, since the switching power received by traditional memory modules is transformed by high-speed switching of electronic components, it has large fluctuation characteristics. Therefore, the noise caused by switching power is high, which makes the memory Noise is also higher when the module receives switched power, resulting in lower stability and lower frequency of traditional memory modules.
因此,如何發展一種克服上述缺點的記憶體模組,實為目前迫切之需求。Therefore, how to develop a memory module that overcomes the above shortcomings is currently an urgent need.
本案之目的在於提供一種記憶體模組,其分別利用訊號輸入接腳及電源輸入端口接收控制訊號及線性電能,由於線性電能具有波動較小的特性,因此本案的記憶體模組所接收的線性電能具有雜訊較低的優勢,且本案的記憶體模組接收線性電能時的雜訊亦較低,故本案的記憶體模組的穩定性較高且頻率較高,甚至可達到超頻的等級,進而提升本案的記憶體模組的效能。The purpose of this case is to provide a memory module that uses signal input pins and power input ports to receive control signals and linear power. Since linear power has the characteristics of small fluctuations, the memory module of this case receives linear power. Electric power has the advantage of lower noise, and the memory module in this case also has lower noise when receiving linear power. Therefore, the memory module in this case has higher stability and higher frequency, and can even reach overclocking levels. , thereby improving the performance of the memory module in this case.
為達上述目的,本案之一實施例為一種記憶體模組,包含電路板、至少一記憶體晶片、至少一訊號輸入接腳及電源輸入端口。至少一記憶體晶片設置於電路板上。至少一訊號輸入接腳設置於電路板上,係用以接收控制訊號,訊號輸入接腳經由電路板內的布線電連接於至少一記憶體晶片,以使記憶體模組對至少一記憶體晶片進行控制。電源輸入端口設置於電路板上,係用以接收至少一線性電能,電源輸入端口經由電路板內的布線電連接於至少一記憶體晶片,以使記憶體模組對至少一記憶體晶片進行供電。To achieve the above object, one embodiment of the present invention is a memory module, including a circuit board, at least one memory chip, at least one signal input pin and a power input port. At least one memory chip is disposed on the circuit board. At least one signal input pin is disposed on the circuit board for receiving control signals. The signal input pin is electrically connected to at least one memory chip through wiring in the circuit board, so that the memory module can control at least one memory chip. The chip is controlled. The power input port is disposed on the circuit board and is used to receive at least one linear power. The power input port is electrically connected to at least one memory chip through wiring in the circuit board, so that the memory module operates on the at least one memory chip. Power supply.
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖式在本質上係當作說明之用,而非用於限制本案。Some typical embodiments embodying the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various changes in different aspects without departing from the scope of this case, and the descriptions and drawings are essentially for illustrative purposes and are not used to limit this case.
請參閱第1圖及第2圖,其中第1圖為本案之記憶體模組的結構上視圖,第2圖為第1圖所示的記憶體模組的結構下視圖。本案的記憶體模組1可為動態隨機存取記憶體(Dynamic Random Access Memory, DRAM)、固態硬碟(Solid-State Drive, SSD)或第五代雙倍數據率同步動態隨機存取記憶體(Double Data Rate Synchronous fifth-generation Dynamic Random Access Memory, DDR5 SDRAM)等。記憶體模組1設置於電子裝置的主電路板(未圖式)上,且可接收至少一電能來源,即由線性電源供應器7(linear power supply)所提供的線性電能,線性電能的電壓可為5V,其中線性電源供應器7可設置於電子裝置的主電路板上,即電子裝置可利用內部供電的方式提供電能給記憶體模組1,或者線性電源供應器7可設置於電子裝置外的設備中,即電子裝置可利用外部供電的方式提供電能給記憶體模組1。Please refer to Figures 1 and 2. Figure 1 is a structural top view of the memory module in this case, and Figure 2 is a structural bottom view of the memory module shown in Figure 1. The memory module 1 in this case can be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a solid state drive (Solid-State Drive, SSD) or a fifth-generation double data rate synchronous dynamic random access memory. (Double Data Rate Synchronous fifth-generation Dynamic Random Access Memory, DDR5 SDRAM), etc. The memory module 1 is disposed on the main circuit board (not shown) of the electronic device and can receive at least one power source, that is, linear power provided by a linear power supply 7 (linear power supply). The voltage of the linear power It can be 5V, in which the linear power supply 7 can be disposed on the main circuit board of the electronic device, that is, the electronic device can provide power to the memory module 1 using an internal power supply, or the linear power supply 7 can be disposed on the electronic device. In external equipment, that is, the electronic device can provide power to the memory module 1 using an external power supply.
如第1圖及第2圖所示,記憶體模組1包含電路板2、至少一記憶體晶片3、至少一訊號輸入接腳4、電源輸入端口5。第1圖中係示出記憶體模組1的電路板2的第一面及位於電路板2的第一面上的電子元件,第2圖中則係示出記憶體模組1的電路板2的相對於第一面的第二面及位於電路板2的第二面上的電子元件。電路板2具有第一側21、第二側22、第三側23及第四側24,第一側21及第二側22相對設置,第三側23及第四側24相對設置。如第1圖所示,本實施例的記憶體模組1包含複數個記憶體晶片3,複數個記憶體晶片3設置於電路板2的第一面上,複數個記憶體晶片3中的部份記憶體晶片3依序排列且相鄰於電路板2的第二側22及第三側23,複數個記憶體晶片3中的另外部分記憶體晶片3依序排列且相鄰於電路板2的第二側22及第四側24。如第1圖及第2圖所示,本實施例的記憶體模組1包含複數個訊號輸入接腳4,複數個訊號輸入接腳4構成記憶體模組1的金手指,且分別設置於電路板2的第一面及第二面上,且相鄰於電路板2的第二側22,更位於第三側23及第四側24之間,其中訊號輸入接腳4用以接收控制訊號,而未接收任何電能,訊號輸入接腳4更經由電路板2內的布線電連接於複數個記憶體晶片3,以使記憶體模組1根據控制訊號對複數個記憶體晶片3進行控制。電源輸入端口5可包含USB type-A、USB type-B或是USB type-C端口,且設置於電路板2的第一面上,並相鄰於電路板2的第一側21,而與訊號輸入接腳4間隔設置,其中電源輸入端口5用以接收線性電源供應器7所提供的線性電能,而未接收任何控制訊號,且電源輸入端口5更經由電路板2內的布線電連接於複數個記憶體晶片3,以使記憶體模組1根據線性電能對複數個記憶體晶片3進行供電。As shown in Figures 1 and 2, the memory module 1 includes a circuit board 2, at least one memory chip 3, at least one signal input pin 4, and a power input port 5. The first figure shows the first side of the circuit board 2 of the memory module 1 and the electronic components located on the first side of the circuit board 2. The second figure shows the circuit board of the memory module 1. The second side of 2 relative to the first side and the electronic components located on the second side of the circuit board 2 . The circuit board 2 has a first side 21 , a second side 22 , a third side 23 and a fourth side 24 . The first side 21 and the second side 22 are arranged oppositely, and the third side 23 and the fourth side 24 are arranged oppositely. As shown in Figure 1, the memory module 1 of this embodiment includes a plurality of memory chips 3. The plurality of memory chips 3 are disposed on the first surface of the circuit board 2. Parts of the plurality of memory chips 3 are The memory chips 3 are arranged in sequence and adjacent to the second side 22 and the third side 23 of the circuit board 2 , and other memory chips 3 in the plurality of memory chips 3 are arranged in sequence and adjacent to the circuit board 2 the second side 22 and the fourth side 24. As shown in Figures 1 and 2, the memory module 1 of this embodiment includes a plurality of signal input pins 4. The plurality of signal input pins 4 constitute the golden fingers of the memory module 1 and are respectively provided on The first and second sides of the circuit board 2 are adjacent to the second side 22 of the circuit board 2 and are located between the third side 23 and the fourth side 24. The signal input pin 4 is used to receive control signal without receiving any power. The signal input pin 4 is electrically connected to the plurality of memory chips 3 through the wiring in the circuit board 2, so that the memory module 1 performs operations on the plurality of memory chips 3 according to the control signal. control. The power input port 5 may include a USB type-A, USB type-B or USB type-C port, and is disposed on the first side of the circuit board 2, adjacent to the first side 21 of the circuit board 2, and connected to the first side 21 of the circuit board 2. The signal input pins 4 are arranged at intervals, and the power input port 5 is used to receive linear power provided by the linear power supply 7 without receiving any control signals, and the power input port 5 is electrically connected through the wiring in the circuit board 2 to the plurality of memory chips 3, so that the memory module 1 supplies power to the plurality of memory chips 3 based on linear power.
於本實施例中,記憶體模組1更包含至少一電源管理晶片6(Power Management IC),設置於電路板2的第一面及第二面上,且經由電路板2內的布線電連接於電源輸入端口5及複數個記憶體晶片3,以經由電源輸入端口5接收線性電能,並將線性電能進行分壓,例如將5V的線性電能分壓為2.5V、1.2V及0.6V, ,以分別對對應的記憶體晶片3進行供電。於本實施例中,複數個訊號輸入接腳4中的其中之一為觸發接腳,用以接收控制訊號中的睡眠訊號或觸發訊號,以對對應的記憶體晶片進行睡眠控制或喚醒控制,進而使對應的記憶體晶片進入睡眠狀態或由睡眠狀態轉為甦醒狀態。In this embodiment, the memory module 1 further includes at least one power management chip 6 (Power Management IC), which is disposed on the first side and the second side of the circuit board 2 and is connected via wiring circuits in the circuit board 2 Connected to the power input port 5 and a plurality of memory chips 3 to receive linear power through the power input port 5 and divide the linear power, for example, divide the 5V linear power into 2.5V, 1.2V and 0.6V. , to supply power to the corresponding memory chips 3 respectively. In this embodiment, one of the plurality of signal input pins 4 is a trigger pin for receiving a sleep signal or a trigger signal in the control signal to perform sleep control or wake-up control on the corresponding memory chip. Then the corresponding memory chip enters the sleep state or changes from the sleep state to the awake state.
綜上所述,本案的記憶體模組分別利用訊號輸入接腳及電源輸入端口接收控制訊號及線性電能,由於線性電能具有波動較小的特性,因此相較於傳統記憶體模組利用單一輸入端口同時接收訊號及交換式電能,本案的記憶體模組所接收的線性電能具有雜訊較低的優勢,且本案的記憶體模組接收線性電能時的雜訊亦較低,故本案的記憶體模組的穩定性較高且頻率較高,甚至可達到超頻的等級,進而提升本案的記憶體模組的效能。To sum up, the memory module in this case uses the signal input pin and the power input port to receive the control signal and linear power respectively. Since the linear power has the characteristics of less fluctuation, compared with the traditional memory module that uses a single input The port receives signals and switched power at the same time. The linear power received by the memory module in this case has the advantage of lower noise, and the memory module in this case also has lower noise when it receives linear power. Therefore, the memory in this case The body module has higher stability and higher frequency, and can even reach overclocking levels, thus improving the performance of the memory module in this case.
1:記憶體模組 2:電路板 21:第一側 22:第二側 23:第三側 24:第四側 3:記憶體晶片 4:訊號輸入接腳 5:電源輸入端口 6:電源管理晶片 7:線性電源供應器1: Memory module 2:Circuit board 21: First side 22: Second side 23:Third side 24:Fourth side 3: Memory chip 4: Signal input pin 5:Power input port 6:Power management chip 7: Linear power supply
第1圖為本案之記憶體模組的結構上視圖。 第2圖為第1圖所示的記憶體模組的結構下視圖。 Figure 1 is a structural top view of the memory module in this case. Figure 2 is a structural bottom view of the memory module shown in Figure 1 .
1:記憶體模組 1: Memory module
2:電路板 2:Circuit board
21:第一側 21: First side
22:第二側 22: Second side
23:第三側 23:Third side
24:第四側 24:Fourth side
3:記憶體晶片 3: Memory chip
4:訊號輸入接腳 4: Signal input pin
5:電源輸入端口 5:Power input port
6:電源管理晶片 6: Power management chip
7:線性電源供應器 7: Linear power supply
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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TW200818210A (en) * | 2006-08-02 | 2008-04-16 | Feringo Inc | Memory device and hub controller |
TW200839767A (en) * | 2006-10-23 | 2008-10-01 | Virident Systems Inc | Methods and apparatus of dual inline memory modules for flash memory |
US20100281309A1 (en) * | 2009-04-30 | 2010-11-04 | Gilbert Laurenti | Power Management Events Profiling |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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TW200818210A (en) * | 2006-08-02 | 2008-04-16 | Feringo Inc | Memory device and hub controller |
TW200839767A (en) * | 2006-10-23 | 2008-10-01 | Virident Systems Inc | Methods and apparatus of dual inline memory modules for flash memory |
US20100281309A1 (en) * | 2009-04-30 | 2010-11-04 | Gilbert Laurenti | Power Management Events Profiling |
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