TWI743882B - Flexible wireless communication chip and wireless communication tag - Google Patents

Abstract

A flexible wireless communication chip includes a flexible substrate and a wireless communication circuit disposed on the flexible substrate. The wireless communication circuit includes thin film transistors. Each of the thin film transistors has a first terminal, a second terminal and a control terminal, and vertical projections of the first terminal and the second terminal on the flexible substrate are arranged in a first direction. First directions of the thin film transistors of the wireless communication circuit are substantially parallel. A wireless communication tag including the flexible wireless communication chip is also provided.

Description

Flexible wireless communication chip and wireless communication label

The present invention relates to various electronic devices, and particularly relates to a flexible wireless communication chip and a wireless communication tag.

Near Field Communication (NFC) technology allows two electronic devices equipped with antenna functions to communicate wirelessly within a distance of a few centimeters. This non-contact data exchange mechanism has the advantages of high response speed, high security, convenience, etc. Therefore, in recent years, many products on the market have integrated near-field wireless communication functions, such as electronic ticket cards (for example: leisure card Etc.), electronic payment devices (for example: smart phones, smart watches, etc.), etc. Users only need to bring an object with a near-field wireless communication tag (NFC tag) close to a card reader (NFC reader) to complete identity verification and data exchange in a short time, providing users with a more convenient lifestyle.

A near-field wireless communication tag (NFC tag) includes an antenna and a wireless communication chip electrically connected to the antenna. In order to make the NFC tag easy to install on electronic products of various appearances, the NFC tag and its wireless communication chip need to be flexible. In other words, the wireless communication chip needs to use a flexible substrate to carry the wireless communication circuit. However, when a wireless communication circuit is formed on a flexible substrate with a low melting point, the multiple thin film transistors of the wireless communication circuit are prone to have different physical characteristics, which affects the performance of the wireless communication chip/near field wireless communication tag.

The invention provides a flexible wireless communication chip with good performance.

The invention provides a wireless communication tag with good performance.

The flexible wireless communication chip of the present invention includes a flexible substrate and a wireless communication circuit arranged on the flexible substrate. The wireless communication circuit includes a plurality of thin film transistors. Each thin film transistor has a first end, a second end and a control end, and a plurality of vertical projections of the first end and the second end on the flexible substrate are arranged in the first direction. The plurality of first directions of the plurality of thin film transistors of the wireless communication circuit are substantially parallel.

The wireless communication tag of the present invention includes the above-mentioned flexible wireless communication chip and an antenna electrically connected to the wireless communication circuit of the flexible wireless communication chip.

In an embodiment of the present invention, the above-mentioned flexible substrate is bent in the second direction, and the first direction and the second direction are substantially perpendicular.

In an embodiment of the present invention, the above-mentioned wireless communication circuit includes a D flip-flop, the plurality of thin film transistors include all the first thin film transistors of the D flip-flop, and all the first thin film transistors of the D flip-flop The first directions of a thin film transistor are substantially parallel.

In an embodiment of the present invention, the above-mentioned wireless communication circuit includes a power supply line, a common line, and a D flip-flop. D flip-flops include "reverse or" gates and "reverse" gates. The "reverse-OR" gate includes a first thin film transistor and a second thin film transistor among a plurality of thin film transistors, a first input line, a second input line and a first output line, and the first end of the first thin film transistor And the first end of the second thin film transistor are electrically connected to the first output line, and the control end of the first thin film transistor and the control end of the second thin film transistor are electrically connected to the first input line and the second input line, respectively , And the second end of the first thin film transistor and the second end of the second thin film transistor are electrically connected to the common line. The "reverse" gate includes a third thin film transistor and a fourth thin film transistor among a plurality of thin film transistors, a third input line and a second output line, and the first end of the third thin film transistor is electrically connected to the power supply Line, the control end of the third thin film transistor and the control end of the fourth thin film transistor are electrically connected to the third input line, and the second end of the third thin film transistor and the first end of the fourth thin film transistor are electrically connected To the second output line, and the second end of the fourth thin film transistor is electrically connected to the common line. The first direction of the first thin film transistor, the first direction of the second thin film transistor, the first direction of the third thin film transistor, and the first direction of the fourth thin film transistor are substantially parallel.

In an embodiment of the present invention, the above-mentioned wireless communication circuit includes a power supply line, a common line, and a D flip-flop. The D flip-flop includes multiple "reverse OR" gates. Each "reverse-OR" gate includes a first thin film transistor and a second thin film transistor among a plurality of thin film transistors, a first input line, a second input line and a first output line, and the first thin film transistor One end and the first end of the second thin film transistor are electrically connected to the first output line, and the control end of the first thin film transistor and the control end of the second thin film transistor are electrically connected to the first input line and the second Input line, and the second end of the first thin film transistor and the second end of the second thin film transistor are electrically connected to the common line. Multiple "reverse-or" gates include the first "reverse-or" gate, the second "reverse-or" gate and the third "reverse-or" gate. The first output line of the first "reverse-or" gate is electrically connected to the second The second input line of the "inverse OR" gate, and the first input line of the second "inverse OR" gate is electrically connected to the first input line of the third "inverse OR" gate. The multiple first directions of the first thin film transistor and the second thin film transistor of the first “OR” gate, the multiple first directions of the first thin film transistor and the second thin film transistor of the second “OR” gate The direction is substantially parallel to the first direction of the first thin film transistor and the second thin film transistor of the third "reverse-OR" gate.

In an embodiment of the present invention, the above-mentioned first "reverse OR" gate, second "reverse OR" gate and third "reverse OR" gate are arranged on the same side of the common line.

In an embodiment of the present invention, the above-mentioned first "reverse OR" gate, second "reverse OR" gate and third "reverse OR" gate are arranged in order in the first direction.

In an embodiment of the present invention, the above-mentioned wireless communication circuit includes a frequency divider, a decoder, and a memory. The plurality of thin film transistors of the wireless communication circuit includes a plurality of first thin film transistors of the frequency divider. The decoder is electrically connected to the frequency divider. The plurality of thin film transistors of the wireless communication circuit includes a plurality of second thin film transistors of the decoder. The memory is electrically connected to the decoder. The plurality of thin film transistors of the wireless communication circuit includes a plurality of third thin film transistors of the memory. The plurality of first directions of the plurality of first thin film transistors of the frequency divider, the plurality of first directions of the plurality of second thin film transistors of the decoder, and the plurality of first directions of the plurality of third thin film transistors of the memory The directions are essentially parallel.

In an embodiment of the present invention, the above-mentioned wireless communication circuit further includes a counter, which is electrically connected to the frequency divider and the decoder. The multiple thin film transistors of the wireless communication circuit include multiple fourth thin film transistors of the counter, and multiple first directions of the multiple first thin film transistors of the frequency divider and multiple fourth thin film transistors of the counter. The first directions are substantially parallel.

In an embodiment of the present invention, a part of the frequency divider, a part of the counter, and a part of the decoder are sequentially arranged in the first direction.

Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable range of deviation or standard deviation based on optical properties, etching properties, or other properties, instead of using one standard deviation for all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

FIG. 1 is a schematic diagram of a flexible wireless communication chip 10 according to an embodiment of the present invention.

Please refer to FIG. 1, the flexible wireless communication chip 10 includes a flexible substrate 110 and a wireless communication circuit C disposed on the flexible substrate 110. The material of the flexible substrate 110 includes a flexible material. For example, in this embodiment, the material of the flexible substrate 110 may include organic polymers, such as polyimide (PI), polyethylene naphthalate (PEN), and poly(p-phenylene). Polyethylene terephthalate (PET), polycarbonates (PC), polyether sulfone (PES) or polyarylate (polyarylate), or other suitable materials, or at least two of the foregoing A combination of these materials.

The wireless communication circuit C includes a divider (Divider) DV, a decoder (Decoder) DC_3-8, DC_4-16 electrically connected to the divider DV, and a memory electrically connected to the decoder DC_3-8, DC_4-16 Body ROM. In this embodiment, the wireless communication circuit C further includes a counter (Counter) CNT, which is electrically connected to the frequency divider DV and the decoders DC_3-8 and DC_4-16. In addition, the wireless communication circuit C may optionally include a buffer BF (Buffer), which is electrically connected to the frequency divider DV and the counter (Counter) CNT.

FIG. 2 is a schematic diagram of a thin film transistor 120 according to an embodiment of the invention.

Please refer to FIG. 1 and FIG. 2, the wireless communication circuit C includes a plurality of thin film transistors 120. Each thin film transistor 120 has a first terminal 121, a second terminal 122, a control terminal 123, and a semiconductor pattern 124. The first terminal 121 and the second terminal 122 are respectively electrically connected to two different regions of the semiconductor pattern 124. The first terminal The multiple vertical projections of 121 and the second end 122 on the flexible substrate 110 are arranged in the first direction x.

In this embodiment, the control terminal 123 of the thin film transistor 120 is, for example, formed on the first metal layer; the first terminal 121 and the second terminal 122 of the thin film transistor 120 are, for example, formed on the second metal layer; The material is, for example, polysilicon (poly-Si); but the invention is not limited to this.

It is worth noting that the plurality of first directions x of the plurality of thin film transistors 120 of the wireless communication circuit C are substantially parallel. That is to say, in the manufacturing process of the flexible wireless communication chip 10, the Excimer-Laser Annealing (ELA) method is used to convert multiple semiconductor materials (for example, amorphous silicon; not shown) into multiple semiconductor materials. When a plurality of semiconductor patterns 124 (for example, polysilicon) of a thin film transistor 120 are used, the laser beam can scan the plurality of semiconductor materials in the same direction/angle, so that the plurality of thin film transistors 120 of the wireless communication circuit C The plurality of semiconductor patterns 124 have the same or similar physical properties. Thereby, the electrical performance of the plurality of thin film transistors 120 of the wireless communication circuit C is more consistent, which helps to improve the electrical performance of the flexible wireless communication chip 10.

Please refer to FIG. 1, specifically, in this embodiment, the plurality of first directions x of the plurality of thin film transistors 120 of the frequency divider DV, and the plurality of second directions of the plurality of thin film transistors 120 of the decoder DC_4-16 One direction x, the plurality of first directions x of the plurality of thin film transistors 120 of the memory ROM, the plurality of first directions x of the plurality of thin film transistors 120 of the counter CNT, and the plurality of thin film transistors 120 of the buffer BF The multiple first directions x are substantially parallel.

Furthermore, in this embodiment, the first direction x of all the thin film transistors 120 of the frequency divider DV, the first direction x of all the thin film transistors 120 of the decoder DC_3-8, and the first direction x of all the thin film transistors 120 of the decoder DC_4-16 The first direction x of all thin film transistors 120, the first direction x of all thin film transistors 120 of the memory ROM, the first direction x of all thin film transistors 120 of the counter CNT, and the first direction x of all thin film transistors 120 of the buffer BF The first direction x is substantially parallel. That is to say, in this embodiment, the first direction x of all the thin film transistors 120 of the wireless communication circuit C is substantially the same.

FIG. 3 shows the circuit symbol of a D flip-flop DFF according to an embodiment of the present invention.

4 is a schematic diagram of an equivalent circuit of a D flip-flop DFF according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit layout of a D flip-flop DFF according to an embodiment of the present invention.

Please refer to Figure 1, Figure 3, Figure 4 and Figure 5. In this embodiment, the wireless communication circuit C may include a plurality of D-flip-flops DFF (D-Flip-flop), and each D-flip-flop DFF The multiple first directions x of all the thin film transistors 120 are substantially parallel. For example, in this embodiment, the counter CNT and the frequency divider DV may include their respective D flip-flops DFF, and the D flip-flops DFF of the counter CNT have multiple first directions x and The first directions x of all the thin film transistors 120 of the D flip-flop DFF of the frequency divider DV are substantially parallel.

Please refer to FIG. 3, FIG. 4, and FIG. 5. Specifically, in this embodiment, each D flip-flop DFF may include at least one "inverted OR" gate NOR and at least one "inverted" gate INV, one of which is The plurality of first directions x of the plurality of thin film transistors 120 of the inverted OR gate NOR are substantially parallel, and the plurality of first directions x of the plurality of thin film transistors 120 of the “inverted” gate INV are substantially parallel, and a " The plurality of first directions x of the plurality of thin film transistors 120 of the inverted OR gate NOR and the plurality of first directions x of the plurality of thin film transistors 120 of an “inverted” gate INV are also substantially parallel.

FIG. 6 shows the circuit symbol of an "inverted OR" gate NOR according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an equivalent circuit of an "inverted OR" gate NOR according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of the circuit layout of an "inverted OR" gate NOR according to an embodiment of the present invention.

Please refer to FIG. 6, FIG. 7 and FIG. 8. For example, in this embodiment, each "inverted OR" gate NOR may include the first thin film transistor 120-1 and the second thin film transistor 120 among the plurality of thin film transistors 120. The two thin film transistors 120-2, the first input line in1, the second input line in2, and the first output line out1, the first end 121 of the first thin film transistor 120-1 and the first end 121 of the second thin film transistor 120-2 One end 121 is electrically connected to the first output line out1, and the control end 123 of the first thin film transistor 120-1 and the control end 123 of the second thin film transistor 120-2 are electrically connected to the first input line in1 and the first output line, respectively. Two input lines in2, and the second end 122 of the first thin film transistor 120-1 and the second end 122 of the second thin film transistor 120-2 are electrically connected to the common line VSS. Referring to FIG. 8, in this embodiment, in the actual circuit layout, the first end 121 of the first thin film transistor 120-1 and the first end 121 of the second thin film transistor 120-2 can share a conductive pattern. However, the present invention is not limited to this.

Please refer to FIG. 6, FIG. 7 and FIG. 8. In this embodiment, each "inverted OR" gate NOR can also optionally include the fifth thin film transistor 120-5 and the sixth thin film transistor 120 among the plurality of thin film transistors 120. The thin film transistor 120-6, the first terminal 121 of the fifth thin film transistor 120-5 is electrically connected to the power supply line VDD, and the control terminal 123 of the fifth thin film transistor 120-5 is electrically connected to the first input line in1 , The second end 122 of the fifth thin film transistor 120-5 is electrically connected to the first end 121 of the sixth thin film transistor 120-6, and the control end 123 of the sixth thin film transistor 120-6 is electrically connected to the second The input line in2, and the second end 122 of the sixth thin film transistor 120-6 is electrically connected to the first output line out1. Referring to FIG. 8, in this embodiment, in the actual circuit layout, the second end 122 of the fifth thin film transistor 120-5 and the first end 121 of the sixth thin film transistor 120-6 can share a conductive pattern. However, the present invention is not limited to this.

5 and 8, in this embodiment, the first direction x of the first thin film transistor 120-1 of the "inverted OR" gate NOR, the first direction x of the second thin film transistor 120-2, and the first direction x of the second thin film transistor 120-2 in this embodiment The first direction x of the fifth thin film transistor 120-5 and the first direction x of the sixth thin film transistor 120-6 are substantially parallel.

It should be noted that the present invention does not limit the "reverse-OR" gate NOR must be composed of the first thin film transistor 120-1, the second thin film transistor 120-2, the fifth thin film transistor 120-5, and the second thin film transistor 120-1 of FIG. Six thin film transistors are composed of 120-6. In other embodiments, the "inverted OR" gate NOR can also be other types of circuits.

FIG. 9 shows the circuit symbol of an "inverted" gate INV according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of an equivalent circuit of an "inverted" gate INV according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of the circuit layout of an "inverted" gate INV according to an embodiment of the present invention.

Please refer to FIG. 9, FIG. 10 and FIG. 11. In this embodiment, each "inverted" gate INV includes a third thin film transistor 120-3 and a fourth thin film transistor 120- among the plurality of thin film transistors 120. 4. The third input line in3 and the second output line out2, the first terminal 121 of the third thin film transistor 120-3 is electrically connected to the power supply line VDD, and the control terminal 123 and the first terminal of the third thin film transistor 120-3 are electrically connected to the power supply line VDD. The control terminal 123 of the four thin film transistor 120-4 is electrically connected to the third input line in3, the second terminal 122 of the third thin film transistor 120-3 and the first terminal 121 of the fourth thin film transistor 120-4 are electrically connected It is connected to the second output line out2, and the second end 122 of the fourth thin film transistor 120-4 is electrically connected to the common line VSS.

Referring to FIGS. 5 and 11, the first direction x of the third thin film transistor 120-3 of the "inverted" gate INV and the first direction x of the fourth thin film transistor 120-4 are substantially parallel.

Please refer to FIG. 5, more specifically, in this embodiment, the first thin film transistor 120-1, the second thin film transistor 120-2, the fifth thin film transistor 120-5 and The multiple first directions x of the sixth thin film transistor 120-6 are also substantially parallel to the first directions x of the third thin film transistor 120-3 and the fourth thin film transistor 120-4 of the "inverse" gate INV.

Please refer to FIG. 3, FIG. 4 and FIG. 5. For example, in this embodiment, the D flip-flop DFF may include a first "reverse OR" gate NOR-1, a second "reverse OR" gate NOR-2, The third ``inverse-or'' gate NOR-3, the fourth ``inverse-or'' gate NOR-4, the fifth ``inverse-or'' gate NOR-5, the sixth ``inverse-or'' gate NOR-6 and an ``inverse'' gate INV , Where the first input line in1 of the first "reverse OR" gate NOR-1 can be regarded as the data input terminal D of the D flip-flop DFF, and the second input line in2 of the first "reverse OR" gate NOR-1 is electrically connected To the first output line out1 of the fifth NOR gate NOR-5 and the second input line in2 of the sixth NOR gate NOR-6, the first output line of the first NOR gate NOR-1 out1 is electrically connected to the second input line in2 of the second “inverted-OR” gate NOR-2, and the first input line in1 of the second “inverted-OR” gate NOR-2 is electrically connected to the fourth “inverted-OR” gate NOR The first output line out1 of -4 and the first input line in1 of the third "inverted OR" gate NOR-3, the first output line out1 of the second "inverted OR" gate NOR-2 is electrically connected to the "inverted" gate The third input line in3 of INV and the first input line in1 of the fourth "inverted OR" gate NOR-4, and the second output line out2 of the "inverted" gate INV is electrically connected to the fifth "inverted OR" gate NOR-5 When the second input line in2 of the fourth "inverse OR" gate NOR-4 and the first input line in1 of the fifth "inverse OR" gate NOR-5 are electrically connected to the flip-flop DFF Pulse input terminal CLK, the first output line out1 of the fifth "inverted OR" gate NOR-5 is electrically connected to the second input line in2 of the sixth "inverted OR" gate NOR-6, and the third "inverted OR" gate NOR The second input line in2 of -3 and the first output line out1 of the sixth "inverse OR" gate NOR-6 are electrically connected to the inverted value terminal QB of the temporary data output terminal Q of the D flip-flop DFF, and the third The first output line out1 of the "inverse OR" gate NOR-3 and the first input line in1 of the sixth "inverse OR" gate NOR-6 are electrically connected to the temporary data output terminal Q of the D flip-flop DFF.

Please refer to FIG. 5, in this embodiment, the first "reverse OR" gate NOR-1, the second "reverse OR" gate NOR-2, the third "reverse OR" gate NOR-3, and the fourth "reverse OR" gate NOR-1 in this embodiment Gate NOR-4, the fifth "inverted-OR" gate NOR-5 and the sixth "inverted-OR" gate NOR-6 multiple first thin film transistors 120-1, multiple second thin film transistors 120-2, multiple The third thin film transistor 120-3 and the fourth thin film transistor 120- of the first direction x and the "inverse" gate INV of the fifth thin film transistor 120-5 and the sixth thin film transistor 120-6 The multiple first directions x of 4 are substantially parallel.

It should be noted that the present invention does not limit the D flip-flop DFF to be composed of the first "reverse-OR" gate NOR-1, the second "reverse-OR" gate NOR-2, and the third "reverse-OR" gate of FIG. 4. NOR-3, the fourth "inverse OR" gate NOR-4, the fifth "inverse OR" gate NOR-5, the sixth "inverse OR" gate NOR-6 and the "inverse" gate INV. In other embodiments, the "inverted OR" gate NOR can also be other types of circuits.

Referring to FIG. 5, in this embodiment, since the first direction x of each thin film transistor 120 of the D flip-flop DFF is the same, the first "inverted OR" gate NOR-1 and the second "inverted OR" gate NOR-2, the third ``inverse or'' gate NOR-3, the fourth ``inverse or'' gate NOR-4, the fifth ``inverse or'' gate NOR-5, the sixth ``inverse or'' gate NOR-6 and the The gate INV can be set on the same side of a common line VSS, the first “inverted-OR” gate NOR-1, the second “inverted-OR” gate NOR-2, the “inverted” gate INV, and the fourth “inverted-OR” gate NOR -4. The fifth "reverse-or" gate NOR-5, the third "reverse-or" gate NOR-3 and the sixth "reverse-or" gate NOR-6 can be arranged in order in the first direction x, so that D is positive The layout area of the inverter DFF is small, which helps to reduce the overall area of the flexible wireless communication chip 10.

Please refer to FIG. 1. In addition, in this embodiment, since the first directions x of the plurality of thin film transistors 120 of the wireless communication circuit C are substantially parallel, the plurality of functional circuits of the wireless communication circuit C can be roughly in accordance with The order of processing signals is arranged on the flexible substrate 110, which helps to reduce the overall layout area of the wireless communication circuit C, and realizes the miniature flexible wireless communication chip 10.

For example, in this embodiment, the frequency divider DV, the buffer BF, the counter CNT, the decoder DC_3-8, and the memory ROM can be sequentially arranged on the flexible substrate 110, wherein a part of the frequency divider DV, A part of the counter CNT and a part of the decoder DC_3-8 can be arranged in sequence in the first direction x of the thin film transistor 120.

FIG. 12 is a schematic diagram of a semi-finished product 1A of a wireless communication tag according to an embodiment of the present invention.

1 and 12, after the multiple flexible wireless communication chips 10 are manufactured, the multiple flexible wireless communication chips 10 can be arranged on a tape 21 to facilitate the flexible wireless communication chips 10 and Transport and/or storage of the antenna 30 (drawn in Figure 13) before connection. In the semi-finished product 1A of the wireless communication tag, the wireless communication circuit C of the wireless communication chip 10 is arranged between the flexible substrate 110 of the wireless communication chip 10 and the tape 21, that is, the film surface of the wireless communication chip 10 faces the wireless communication The reel 22 of the semi-finished product 1A of the label.

The tape 21 is adapted to be wound on the reel 22 to be bent in the second direction y, and the flexible substrate 110 of the wireless communication chip 10 is also bent in the second direction y along with the tape 21. It is worth noting that whether it is in the semi-finished product 1A or the finished product of the wireless communication tag (such as the wireless communication tag 1 in Figure 13), the first direction x and the second direction y of the thin film transistor 120 of the wireless communication chip 10 (ie, bending Direction) vertical. In this way, the electrical changes caused by the bending of the thin film transistor 120 can be reduced or avoided, and the reliability of the flexible wireless communication chip 10 can be improved.

FIG. 13 is a schematic diagram of a wireless communication tag 1 according to an embodiment of the present invention.

1 and 13, the wireless communication tag 1 includes a flexible wireless communication chip 10 and an antenna 30 electrically connected to the wireless communication circuit C of the flexible wireless communication chip 10. In this embodiment, the flexible wireless communication chip 10 may include a plurality of pads P disposed on the flexible substrate 110 and electrically connected to the wireless communication circuit C; a plurality of pads of the flexible wireless communication chip 10 P can be connected to both ends of the antenna 30 with silver glue, so that the wireless communication circuit C of the flexible wireless communication chip 10 and the antenna 30 are electrically connected. However, the present invention is not limited to this. In other embodiments, the flexible wireless communication chip 10 may also be electrically connected to the antenna 30 in other ways. For example, in one embodiment, the antenna 30 may be formed on the flexible wireless communication chip 10 in a printing direction, so as to be electrically connected to the wireless communication circuit C of the flexible wireless communication chip 10.

In summary, the flexible wireless communication chip/wireless communication tag of an embodiment of the present invention includes a flexible substrate and a wireless communication circuit disposed on the flexible substrate, wherein the wireless communication circuit includes a plurality of thin film transistors, each The thin film transistor has a first end, a second end, and a control end. A plurality of vertical projections of the first end and the second end on the flexible substrate are arranged in a first direction.

In particular, the plurality of first directions of the plurality of thin film transistors of the wireless communication circuit are substantially parallel. Thereby, in the manufacturing process of the flexible wireless communication chip, the laser beam can scan multiple semiconductor materials in the same direction/angle, so that the multiple semiconductor patterns of multiple thin film transistors of the wireless communication circuit have the same or Similar physical characteristics, thereby improving the electrical properties of the flexible wireless communication chip/wireless communication tag.

1: Wireless communication label 1A: Semi-finished products 10: Flexible wireless communication chip 21: Reel 22: Scroll 30: Antenna 110: Flexible substrate 120: thin film transistor 120-1: The first thin film transistor 120-2: The second thin film transistor 120-3: The third thin film transistor 120-4: The fourth thin film transistor 120-5: Fifth thin film transistor 120-6: The sixth thin film transistor 121: first end 122: second end 123: Control terminal 124: Semiconductor pattern BF: Buffer C: wireless communication circuit CNT: counter D: Data input terminal DV: Frequency divider DC_3-8, DC_4-16: decoder DFF: D flip-flop in1: the first input line in2: second input line in3: third input line INV: ``inverse'' gate NOR: ``reverse or'' gate NOR-1: The first ``reverse or'' gate NOR-2: The second ``reverse or'' gate NOR-3: The third ``reverse or'' gate NOR-4: The fourth ``reverse or'' gate NOR-5: The fifth ``reverse or'' gate NOR-6: The sixth ``reverse or'' gate out1: the first output line out2: second output line P: pad Q: Temporary data output terminal QB: Inverted value terminal ROM: memory VSS: common line VDD: power supply line x: first direction y: second direction

FIG. 1 is a schematic diagram of a flexible wireless communication chip 10 according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a thin film transistor 120 according to an embodiment of the invention. FIG. 3 shows the circuit symbol of a D flip-flop DFF according to an embodiment of the present invention. 4 is a schematic diagram of an equivalent circuit of a D flip-flop DFF according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a circuit layout of a D flip-flop DFF according to an embodiment of the present invention. FIG. 6 shows the circuit symbol of an "inverted OR" gate NOR according to an embodiment of the present invention. FIG. 7 is a schematic diagram of an equivalent circuit of an "inverted OR" gate NOR according to an embodiment of the present invention. FIG. 8 is a schematic diagram of the circuit layout of an "inverted OR" gate NOR according to an embodiment of the present invention. FIG. 9 shows the circuit symbol of an "inverted" gate INV according to an embodiment of the present invention. FIG. 10 is a schematic diagram of an equivalent circuit of an "inverted" gate INV according to an embodiment of the present invention. FIG. 11 is a schematic diagram of the circuit layout of an "inverted" gate INV according to an embodiment of the present invention. FIG. 12 is a schematic diagram of a semi-finished product 1A of a wireless communication tag according to an embodiment of the present invention. FIG. 13 is a schematic diagram of a wireless communication tag 1 according to an embodiment of the present invention.

10: Flexible wireless communication chip

110: Flexible substrate

120: thin film transistor

BF: Buffer

C: wireless communication circuit

CNT: counter

DV: Frequency divider

DC_3-8, DC_4-16: decoder

P: pad

ROM: memory

x: first direction

Claims (10)

A flexible wireless communication chip includes: a flexible substrate; and a wireless communication circuit arranged on the flexible substrate, wherein the wireless communication circuit includes a plurality of thin film transistors; each of the thin film transistors has a first One end, a second end, and a control end. A plurality of vertical projections of the first end and the second end on the flexible substrate are arranged in a first direction; the thin film transistors of the wireless communication circuit The plurality of first directions of the D flip-flop are substantially parallel; the wireless communication circuit includes a D flip-flop, the thin film transistors include all the first thin film transistors of the D flip-flop, and the D flip-flop The first directions of all the first thin film transistors are substantially parallel. The flexible wireless communication chip according to claim 1, wherein the flexible substrate is bent in a second direction, and the first direction and the second direction are substantially perpendicular. The flexible wireless communication chip according to claim 1, wherein the wireless communication circuit includes a power supply line and a common line, and the D flip-flop includes: a "reverse OR" gate including the thin film transistors A first thin film transistor and a second thin film transistor of the first thin film transistors, a first input line, a second input line and a first output line, the first thin film transistor The first end and the first end of the second thin film transistor are electrically connected to the first output line, and the control end of the first thin film transistor and the control end of the second thin film transistor are respectively electrically connected Connected to the first input line and the second input line, and the second end of the first thin film transistor and the second end of the second thin film transistor are electrically connected to the common line; and a "reverse" The gate includes a third thin film transistor and a fourth thin film transistor among the thin film transistors, a third input line and a second output line, and the first terminal of the third thin film transistor is Electrically connected to the power supply line, the control end of the third thin film transistor and the control end of the fourth thin film transistor are electrically connected to the third input line, and the second end of the third thin film transistor And the first end of the fourth thin film transistor is electrically connected to the second output line, and the second end of the fourth thin film transistor is electrically connected to the common line; the first end of the first thin film transistor The first direction, the first direction of the second thin film transistor, the first direction of the third thin film transistor, and the first direction of the fourth thin film transistor are substantially parallel. The flexible wireless communication chip according to claim 1, wherein the wireless communication circuit includes a power supply line and a common line, and the D flip-flop includes: a plurality of "reverse OR" gates, each of which "reverse" The OR gate includes a first thin film transistor and a second thin film transistor of the first thin film transistors among the thin film transistors, a first input line, a second input line, and a first output Line, the first end of the first thin film transistor and the first end of the second thin film transistor are electrically connected to the first output line, the control end of the first thin film transistor and the second thin film The control terminal of the transistor is electrically connected to the first input line and the second input line, respectively, And the second end of the first thin film transistor and the second end of the second thin film transistor are electrically connected to the common line; the "inverted OR" gates include a first "inverted OR" gate, a The second "reverse OR" gate and a third "reverse OR" gate, the first output line of the first "reverse OR" gate is electrically connected to the second input line of the second "reverse OR" gate, The first input line of the second “OR” gate is electrically connected to the first input line of the third “OR” gate; the first thin film transistor of the first “OR” gate and the The first direction of the second thin-film transistor, the first thin-film transistor of the second “reverse-OR” gate, the multiple first directions of the second thin-film transistor, and the third “reverse-OR” gate The first directions of the first thin film transistor and the second thin film transistor are substantially parallel. The flexible wireless communication chip according to claim 4, wherein the first "reverse-or" gate, the second "reverse-or" gate and the third "reverse-or" gate are arranged on the same side of the shared line. The flexible wireless communication chip according to claim 4, wherein the first "reverse-or" gate, the second "reverse-or" gate and the third "reverse-or" gate are sequentially arranged in the first direction . A flexible wireless communication chip includes: a flexible substrate; and a wireless communication circuit arranged on the flexible substrate, wherein the wireless communication circuit includes a plurality of thin film transistors; each of the thin film transistors has a first One end, a second end and a control end, the first end and the second end are on the flexible substrate The vertical projections are arranged in a first direction; the first directions of the thin-film transistors of the wireless communication circuit are substantially parallel; wherein the wireless communication circuit includes: a frequency divider, and the plurality of first directions of the wireless communication circuit The thin film transistor includes a plurality of first thin film transistors of the frequency divider; a decoder is electrically connected to the frequency divider, wherein the thin film transistors of the wireless communication circuit include a plurality of second thin film transistors of the decoder. Thin film transistors; and a memory electrically connected to the decoder, wherein the thin film transistors of the wireless communication circuit include a plurality of third thin film transistors of the memory; the first ones of the frequency divider The first directions of the thin film transistors, the first directions of the second thin film transistors of the decoder, and the first directions of the third thin film transistors of the memory are substantially parallel. The flexible wireless communication chip according to claim 7, wherein the wireless communication circuit further includes: a counter electrically connected to the frequency divider and the decoder, wherein the thin film transistors of the wireless communication circuit include The fourth thin film transistors of the counter, and the first directions of the first thin film transistors of the frequency divider and the first directions of the fourth thin film transistors of the counter are substantially parallel . The flexible wireless communication chip according to claim 8, wherein a part of the frequency divider, a part of the counter, and a part of the decoder are sequentially arranged in the first direction. A wireless communication tag includes: the flexible wireless communication chip according to any one of claims 1 to 9; and an antenna electrically connected to the wireless communication circuit of the flexible wireless communication chip.

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