TWI741606B - Chip - Google Patents

Abstract

A chip is provided. The chip includes a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The plurality of first sub-transistors and the plurality of second sub-transistors are staggeredly disposed in a first row and a second row of the circuit block. The first transistor disposed in the first row and the second row receives a first input signal through different signal lines. The second transistor disposed in the first row and the second row receives a second input signal through different signal lines.

Description

Chip

The present invention relates to a wafer, and particularly to a semiconductor wafer.

In today's electronic devices, when the chip in the electronic device is cracked, the cracking often affects the signal or voltage transmission in the chip, and thus causes the circuit blocks in the chip to be completely disabled.

The invention provides a chip, which can effectively avoid the complete disabling of circuit blocks caused by chipping.

The chip of the present invention includes circuit blocks. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel with each other. The second transistor is divided into a plurality of second sub-transistors connected in parallel with each other. The first sub-transistor and the second sub-transistor are alternately arranged in the first row and the second row of the circuit block. The first transistors arranged in the first row and the second row respectively receive the first input signal through different signal lines. The second transistors arranged in the first row and the second row are respectively transparent The second input signal is received through a different signal line.

The chip of the present invention includes circuit blocks, power rails, and power circuits. The power trajectory is divided into a first power trajectory and a second power trajectory connected in series. The power track is coupled to the circuit block. The power supply circuit is divided into a first power supply circuit and a second power supply circuit. The power circuit is coupled to the power rail. The power circuit provides the first voltage to the circuit block through the power rail. Two ends of the first power rail are respectively coupled to the first power circuit and the second power circuit. Two ends of the second power rail are respectively coupled to the first power circuit and the second power circuit.

Based on the above, the first transistor and the second transistor are alternately arranged in the first row and the second row in the circuit block, and input signals are received through different signal lines. In this way, when a chip occurs on the chip At this time, the complete disabling of the circuit block can be effectively avoided.

10, 20, 30a, 30b: circuit block

40, 41: chip

100~108, 200~213, 300a~305a, 300b~305b, 306~311, 400, 401, 401a, 401b, 410~413: signal line

402, 403, 414~417: power supply circuit

IN1, IN2: Input signal

CRK: Cracked

M1-1~M1-4, M2-1~M2-4, N1-1~N1-4, N2-1~N2-4, N3-1~N3-4, N4-1~N4-4, P1- 1~P1-4, P2-1~P2-4, P3-1~P3-4, P4-1~P4-4: Transistor

V1: first voltage

V2: second voltage

FIG. 1A is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 1B is a schematic diagram of a cracked CRK in a circuit block according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 3A is a schematic diagram of a circuit block according to an embodiment of the invention.

FIG. 3B is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 4A is a schematic diagram of a wafer according to an embodiment of the present invention.

FIG. 4B is a schematic diagram of a wafer according to an embodiment of the present invention.

Please refer to FIG. 1A, which is a schematic diagram of a circuit block 10 according to an embodiment of the present invention. The circuit block 10 has transistors M1, M2, and signal lines 100-106. In short, the transistors M1 and M2 are respectively arranged in the first row and the second row in the circuit block 10. The transistors M1 and M2 arranged in the first row can obtain the input signal and the first voltage through the signal lines 100, 101, and 106. The transistors M1 and M2 arranged in the second row can obtain the input signal and the first voltage through the signal lines 102, 103, and 106. In other words, the transistors M1 and M2 in the circuit block 10 obtain the input signal and the first voltage by being arranged in the first row and the second row and using different signal lines respectively. In this way, the circuit block 10 is It can effectively avoid the failure or abnormality of the transistors M1 and M2 when the signal lines 101~106 are cracked.

The first thing to say is that the signal lines and signal lines 100~106 shown at the bottom of the screen in Figure 1A are arranged on different layers or different heights. The signal lines and transistors M1 and M2 arranged on different layers or different heights can pass through Via a plug (Via) for connection. Therefore, when the connection is made through the signal line shown at the bottom of the net, the transistors M1 and M2 can be connected across the signal lines 100 to 106 to receive an appropriate signal. This should be a common knowledge in the field.

In detail, the transistor M1 has sub-transistors M1-1~M1-4, and the sub-transistors M1-1~M1-4 are connected to each other in parallel, so the sub-transistors M1-1~M1-4 can be equal The effect is a single transistor M1 to operate. Similarly, the sub-transistors M2-1~M2-4 are connected in parallel with each other, and can be equivalent to a single transistor M2 to operate. For example, the transistors M1 and M2 can be N type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET), P type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET), P type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET), P type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) Semiconductor Field-Effect Transistor, PMOSFET) or other suitable transistors.

The sub-transistors M1-1 to M1-4 and M2-1 to M2-4 may have substantially the same length and width. The sub-transistors M1-1~M1-4 are sequentially arranged in the first row of the first column, the second row of the second column, the third row of the first column, and the fourth row of the second column. The sub-transistor M2- 1~M2-4 are sequentially arranged in the first row of the second column, the second row of the first column, the third row of the second column, and the fourth row of the first column. Therefore, in each column and each row of the circuit block 10, the sub-transistors M1-1 to M1-4 of the transistor M1 and the sub-transistors M2-1 to M2-4 of the transistor M2 are interleaved with each other. The sub-transistors M1-1 to M1-4 of the transistor M1 and the sub-transistors M2-1 to M2-4 of the transistor M2 are alternately arranged in the first row and the second row in a checkerboard manner.

The signal lines 100 and 101 are arranged on the upper side of the circuit block 10, and the signal lines 102 and 103 are arranged on the lower side of the circuit block. The signal lines 100 and 101 are adjacent to the first row of the circuit block 10, and the signal lines 100 and 101 are away from the second row of the circuit block 10. The signal lines 102 and 103 are adjacent to the second row of the circuit block 10, and the signal lines 102 and 103 are away from the first row of the circuit block 10. The signal lines 100 and 101 can be used to provide input signals IN1 and IN2 to the first row of sub-transistors, respectively. The signal lines 102 and 103 can be used to provide input signals IN1 and IN2 to the second row of sub-transistors, respectively.

The signal line 104 is arranged on the right side of the circuit block 10, and the signal line 104 The two ends are respectively coupled to the signal lines 100 and 102. The signal line 105 is arranged on the left side of the circuit block 10, and two ends of the signal line 105 are respectively coupled to the signal lines 101 and 103. In other words, the signal lines 104 and 105 are correspondingly arranged on the two sides of the circuit block 10 respectively. The signal lines 100, 102, and 104 can jointly form a U-shaped structure surrounding the transistors M1 and M2. The signal lines 101, 103, and 105 can jointly form another U-shaped structure surrounding M1, M2. The openings of the two U-shaped structures are arranged corresponding to each other.

The signal line 106 completely surrounds the transistors M1 and M2. The signal line 106 is located on the upper side of the circuit block 10 and can be arranged between the signal lines 100 and 101 and the first row of the circuit block 10. The signal line 106 is located on the lower side of the circuit block 10 and can be arranged between the signal lines 103 and 104 and the second row of the circuit block 10. The signal line 106 is in the right side of the circuit block 10 and can be arranged between the signal line 105 and the fourth row of the circuit block 10. The signal line 106 is in the left side of the circuit block 10 and can be arranged between the signal line 105 and the first row of the circuit block 10.

The signal lines 100, 102, 104 can provide the input signal IN1 to the transistors M1, M2, the signal line 101, 103, 105 can provide the input signal IN2 to the transistors M1, M2, and the signal line 106 can provide the first voltage V1 to the transistors M1, M2. .

In this embodiment, the first terminal of the transistor M1 receives the input signal IN1, the second terminal of the transistor M1 receives the first voltage V1, and the third terminal of the transistor M1 receives the input signal IN2. In order to achieve the above-mentioned coupling relationship, the first ends of the sub-transistors M1-1 and M1-3 in the first column of the transistor M1 are coupled to the signal line 100, and the sub-transistors M1-1 and M1-3 are The second end is coupled to the signal line 106. The first ends of the sub-transistors M1-2 and M1-4 in the second column of the transistor M1 are coupled to the signal line 102, and the sub-transistors The second ends of M1-2 and M1-4 are coupled to the signal line 106. All the sub-transistors M1-1~M1-4 of the transistor M1 couple the third end of each sub-transistor M1-1~M1-4 to each other through the signal line 107 and receive the input signal IN2, wherein the signal line 107 is arranged at Between the first row and the second row of the circuit block 10. The signal line 107 is arranged diagonally and interlaced to connect the third ends of the sub-transistors M1-1 to M1-4 interlaced in the first row and the second row.

Similarly, the first terminal of the transistor M2 receives the input signal IN2, the second terminal of the transistor M2 receives the first voltage V1, and the third terminal of the transistor M1 receives the input signal IN1. In order to achieve the above-mentioned coupling relationship, the first ends of the sub-transistors M2-2 and M2-4 in the first column of the transistor M2 are coupled to the signal line 101, and the first ends of the sub-transistors M2-2 and M2-4 The second end is coupled to the signal line 101. The first ends of the sub-transistors M2-1, M2-3 in the second column of the transistor M2 are coupled to the signal line 102, and the second ends of the sub-transistors M2-1, M2-3 are coupled to the signal line 106. All the sub-transistors M2-1~M2-4 of the transistor M1 couple the third end of each sub-transistor M2-1~M2-4 to each other through the signal line 108 and receive the input signal IN1, wherein the signal line 108 is arranged at Between the first row and the second row of the circuit block 10. The signal line 108 is alternately arranged obliquely to connect to the third ends of the sub-transistors M2-1 to M2-4 arranged alternately in the first row and the second row.

Therefore, the sub-transistors M1-1~M1-4 of the transistor M1 and the sub-transistors M2-1~M2-4 of the M2 in the circuit block 10 are connected in each row and each column of the circuit block 10 as Staggered settings. The transistors M1-1, M2-1, M1-3, M2-4 arranged in the first row can receive input signals IN1, IN2 through signal lines 100, 101, 106 And the first voltage V1, the transistors M2-1, M1-1, M2-3, M1-4 arranged in the second row can receive the input signals IN1, IN2 and the first voltage V1 through the signal lines 102, 103, and 106. Therefore, the circuit block 10 can effectively prevent the transistor M1 or the transistor M2 from being completely disabled when a crack occurs on any one of the signal lines 100 to 103.

Furthermore, by interleaving the sub-transistors M1-1~M1-4 and M2-1~M2-4 in the first row and the second row of the circuit block 10, the non-ideal gradient of the manufacturing process can also be changed. Evenly distributed to transistors M1 and M2. In other words, by interleaving the transistors M1 and M2 in each row and each row, the impact of process non-idealities on the transistors M1 and M2 can be effectively reduced. When the transistors M1 and M2 have a differential circuit structure, a better matching effect can be achieved through the design of the circuit block 10.

FIG. 1B is a schematic diagram of a circuit block 10 having a cracked CRK according to an embodiment of the present invention. In this embodiment, the circuit block 10 can be arranged on a flexible substrate. Due to the bendability of the flexible substrate, the cracking CRK is more likely to occur in the circuit block 10 on the flexible substrate. In detail, the cracked CRK occurs on the signal lines 100, 101, and 106 of the circuit block 10, that is, the cracked CRK occurs on the upper side of the circuit block 10. Therefore, the first end of the sub-transistor M1-1 cannot receive the input signal IN1, and the first end of the sub-transistor M2-2 and M2-4 cannot receive the input signal IN2. In other words, when cracking of the CRK occurs, the sub-transistors M1-1, M2-2, and M2-4 in the first column cannot operate normally.

However, the first end of the transistor M1-3 in the first row can receive the input signal IN1 by the signal line 100, and the second end of the transistor M1-3 can receive the first voltage V1 by the ring-shaped signal line 106. In addition, in the second column of sub-transistors M2-1, M1-2, M2-3, M1-4 can receive input signals IN1 and IN2 on the signal lines 102 and 103, respectively. In addition, the third ends of the sub-transistors M1-1 to M1-4 can receive the input signal IN2 through the signal line 107, and the third ends of the sub-transistors M2-1 to M2-4 can receive the input signal IN1 through the signal line 108. Therefore, the transistor M1-3 in the first column and the sub-transistors M2-1, M1-2, M2-3, and M1-4 in the second column can operate normally.

In short, the circuit block 10 is alternately arranged in the first row and the second row through the sub-transistors M1-1 to M1-4 and M2-1 to M2-4. In addition, the circuit block 10 also provides input signals IN1 on both sides of the circuit block 10 through the signal lines 100 and 102, and provides input signals IN2 on both sides of the circuit block 10 through the signal lines 101 and 103. In this way, when the circuit block 10 has a cracked CRK, it can effectively prevent the cracked CRK from occurring on the only signal line connected to the transistor M1 or M2, which will result in the complete failure of one of the transistors M1 or M2. In other words, when the CRK cracking occurs in the circuit block 10, the transistors M1 and M2 can still receive the input signals IN1, IN2 and the first voltage V1 to operate without completely disabling the circuit block 10.

In another embodiment, a person with ordinary knowledge in the art can of course modify the circuit block 10 according to different design requirements. For example, the transistors M1 and M2 of the circuit block 10 can be divided into more than four. That is to say, the number of rows of the circuit block 10 can be increased or decreased, as long as the number of rows of the circuit block 10 is at least two rows. For example, the signal lines 100, 102, and 104 of the circuit block 10 may not need to have a U-shaped structure. That is to say, the signal lines 100, 102, 104 are also replaced by signal line structures that completely or partially surround the transistors M1 and M2, as long as the circuit block 10 can receive the input signal IN1 on both the upper and lower sides. That's it. The same modification is of course applicable to the news The signal lines 101, 103, 105 can be replaced by signal lines that completely surround the transistors M1, M2. In this way, the input signals IN1 and IN2 are provided by completely surrounding signal lines, and the circuit block 10 can completely prevent any sub-transistor M1-1~M1-4, M2-1~M2-4 from failure due to cracking. .

FIG. 2 is a schematic diagram of a circuit block 20 according to an embodiment of the present invention. The circuit block 20 has transistors P1, P2, N1, N2. In this embodiment, the transistors P1 and P2 can be P-type MOSFETs, and the transistors N1 and N2 can be N-type MOSFETs. Transistor P1 has sub-transistors P1-1 to P1-4, and transistor P2 has sub-transistors P2-1 to P2-4. Transistor N1 has sub-transistors N1-1 to N1-4, and transistor N2 has sub-transistors N2-1 to N2-4.

Sub-transistors P1-1~P1-4, P2-1~P2-4 can have substantially the same length and width, and sub-transistors N1-1~N1-4, N2-1~N2-4 can have substantially the same length and width. Same length and width. Sub-transistors P1-1~P1-4 are arranged in the first row, first row, second row, second row, first column, third row, and second column, fourth row, in order. Sub-transistor P2- 1~P2-4 are sequentially arranged in the first row of the second column, the second row of the first column, the third row of the second column, and the fourth row of the first column. Therefore, in each column and each row of the circuit block 10, the sub-transistors P1-1 to P1-4 of the transistor P1 and the sub-transistors P2-1 to P2-4 of the transistor P2 are interleaved with each other. The sub-transistors P1-1 to P1-4 of the transistor P1 and the sub-transistors P2-1 to P2-4 of the transistor P2 are alternately arranged in the first row and the second row in a checkerboard manner.

The sub-transistors N1-1~N1-4 are sequentially arranged in the first row of the third column, the second row of the fourth column, the third row of the third column, and the fourth row of the fourth column. The sub-transistor N2- 1 ~N2-4 are sequentially set in the first row of the fourth column, the second row of the third column, the third row of the fourth column, and the fourth row of the third column. Therefore, in each column and each row of the circuit block 10, the sub-transistors N1-1 to N1-4 of the transistor N1 and the sub-transistors N2-1 to N2-4 of the transistor N2 are interleaved with each other. The sub-transistors N1-1 to N1-4 of the transistor N1 and the sub-transistors N2-1 to N2-4 of the transistor N2 are alternately arranged in the third and fourth rows in a checkerboard manner.

The signal line 200 is arranged on the upper side of the circuit block 20, the signal line 202 is arranged between the second row and the third row of the circuit block 20, and the signal line 204 is arranged on the lower side of the circuit block 20. The signal line 201 is arranged on the upper side of the circuit block 20, the signal line 203 is arranged between the second row and the third row of the circuit block 20, and the signal line 205 is arranged on the lower side of the circuit block 20. The signal line 206 is connected to the signal lines 200, 202, and 204, and the signal line 207 is connected to the signal lines 201, 203, and 205. The signal line 208 completely surrounds the transistors P1 and P2, and the signal line 209 completely surrounds the transistors N1 and N2. The signal lines 200, 202, and 204 can be used to provide the input signal IN1, the signal lines 201, 203, and 205 can be used to provide the input signal IN2, the signal line 208 can be used to provide the first voltage V1, and the signal line 209 can be used to provide the first voltage V1.

In addition, the signal line 210 is arranged between the first row and the second row of the circuit block 20. The signal line 210 is arranged diagonally and alternately to connect the sub-transistors arranged alternately in the first row and the second row. The third end of P1-1~P1-4. Similarly, the signal line 211 is arranged between the first row and the second row of the circuit block 20 to connect the third ends of the sub-transistors P2-1 to P2-4. The signal line 212 is arranged between the third row and the fourth row of the circuit block 20 to connect the third ends of the sub-transistors N1-1 to N1-4. Signal The line 213 is arranged between the third row and the fourth row of the circuit block 20 to connect the third ends of the sub-transistors N2-1 to N2-4.

Therefore, the sub-transistors P1-1, P2-2, P1-3, and P2-4 in the first row of the circuit block 20 can obtain the input signals IN1, IN2 and the first voltage V1 through the signal lines 200, 201, and 208. The sub-transistors P2-1, P1-2, P2-3, and P1-4 in the second row of the circuit block 20 can obtain the input signals IN1, IN2 and the first voltage V1 through the signal lines 202, 203, and 208. The sub-transistors N1-1, N2-2, N1-3, and N2-4 in the third row of the circuit block 20 can obtain the input signals IN1, IN2 and the second voltage V2 through the signal lines 202, 203, and 209. The sub-transistors N2-1, N1-2, N2-3, and N1-4 in the fourth row of the circuit block 20 can obtain the input signals IN1, IN2 and the second voltage V2 through the signal lines 204, 205, and 209.

In this way, when the cracked CRK occurs in the circuit block 20, the transistors P1, P2, N1, N2 can still receive the input signals IN1, IN2, the first voltage V1, and the second voltage V2 to operate without causing the circuit area Block 20 is completely disabled.

FIG. 3A is a schematic diagram of a circuit block 30a according to an embodiment of the present invention. The circuit block 30a has transistors N3, N4, P3, and P4. Transistors P3 and P4 can be P-type MOSFETs, and transistors N3 and N4 can be N-type MOSFETs. Transistor P3 has sub-transistors P3-1 to P3-4, and transistor P4 has sub-transistors P4-1 to P4-4. Transistor N3 has sub-transistors N3-1 to N3-4, and transistor N4 has sub-transistors N4-1 to N4-4.

Sub-transistors P3-1~P3-4, P4-1~P4-4 can have substantially the same length and width, and sub-transistors N3-1~N3-4, N4-1~N4-4 can have substantially the same length and width. identical Length and width. The sub-transistors N3-1~N3-4 are sequentially arranged in the first row of the first column, the second row of the second column, the third row of the first column, and the fourth row of the second column. The sub-transistor N4- 1~N4-4 are sequentially arranged in the first row of the second column, the second row of the first column, the third row of the second column, and the fourth row of the first column. Therefore, in each column and each row of the circuit block 30a, the sub-transistors N3-1 to N3-4 of the transistor N3 and the sub-transistors N4-1 to N4-4 of the transistor N4 are interleaved with each other. The sub-transistors N3-1 to N3-4 of the transistor N3 and the sub-transistors N4-1 to N4-4 of the transistor N4 are alternately arranged in the first row and the second row in a checkerboard manner.

The sub-transistors P3-1~P3-4 are arranged in the fifth row in the first column, the sixth row in the second column, the seventh row in the first column, and the eighth row in the second column. The sub-transistors P4-1 ~P4-4 is sequentially set in the fifth row of the second column, the sixth row of the first column, the seventh row of the second column, and the eighth row of the first column. Therefore, in each column and each row of the circuit block 30a, the sub-transistors P3-1 to P3-4 of the transistor P3 and the sub-transistors P4-1 to P4-4 of the transistor P4 are interleaved with each other. The sub-transistors P3-1 to P3-4 of the transistor P3 and the sub-transistors P4-1 to P4-4 of the transistor P4 are alternately arranged in the first row and the second row in a checkerboard manner.

The signal line 300a is arranged on the upper side of the circuit block 30a, and the signal line 302a is arranged on the lower side of the circuit block 30a. The signal line 301a is arranged on the upper side of the circuit block 30a, and the signal line 303a is arranged on the lower side of the circuit block 30a. The signal line 304a is connected to the signal lines 300a and 302a, and the signal line 305a is connected to the signal lines 301a and 303a. The signal line 306 completely surrounds the transistors P3 and P4, and the signal line 307 completely surrounds the transistors N3 and N4. The signal lines 300a, 302a can be used to provide the input signal IN1, and the signal line 301a, 303a can be used to provide the input signal IN2, the signal line 306 can be used to provide the first voltage V1, and the signal line 307 can be used to provide the first voltage V1.

In addition, the signal lines 308, 309, 310, 311 are arranged between the first row and the second row of the circuit block 30a, and the signal lines 308 can be connected to the sub-transistors P3 alternately arranged in the first row and the second row. -1 to the third end of P3-4, the signal line 309 can be connected to the third end of the sub-transistors P4-1 to P4-4 alternately arranged in the first row and the second row, and the signal line 310 can be connected to The third end of the sub-transistors N3-1~N3-4 arranged alternately in the first row and the second row, the signal line 311 can be connected to the sub-transistors N4- arranged alternately in the first row and the second row. 1~The third end of N4-4.

Therefore, the sub-transistors N3-1, N4-2, N3-3, N4-4, P3-1, P4-2, P3-3, and P4-4 in the first row of the circuit block 30a can pass through the signal lines 300a, 301a, 306, and 307 obtain input signals IN1, IN2, a first voltage V1, and a second voltage V2. The subtransistors N4-1, N3-2, N4-3, N3-4, P4-1, P3-2, P4-3, and P3-4 in the second row of the circuit block 30a can pass through the signal lines 302a, 303a, 306 and 307 obtain the first voltage V1 and the second voltage V2 of the input signals IN1 and IN2.

In this way, when the cracked CRK occurs in the circuit block 30a, the transistors P3, P4, N3, and N4 can still receive the input signals IN1, IN2, the first voltage V1, and the second voltage V2 to operate without causing the circuit area Block 30a is completely disabled.

FIG. 3B is a schematic diagram of a circuit block 30b according to an embodiment of the present invention. The circuit block 30b depicted in FIG. 3B is similar to the circuit block 30a depicted in FIG. 3A, so the same components use the same symbols. The difference between the circuit block 30a and the circuit block 30b is that the signal lines 300a, 301a, 302a, 303a, 304a, 305a in the circuit block 30a The circuit block 30b is replaced by signal lines 300b, 301b, 302b, 303b, 304b, and 305b, respectively.

The signal line 300b is arranged on the upper side of the circuit block 30b, and the signal line 302b is arranged on the lower side of the circuit block 30b. The signal line 301b is arranged on the upper side of the circuit block 30b, and the signal line 303b is arranged on the lower side of the circuit block 30b. The signal line 304b is connected to the signal lines 300b and 302b, and the signal line 305b is connected to the signal lines 301b and 303b. The signal lines 300b and 302b can be used to provide the input signal IN1, and the signal lines 301b and 303b can be used to provide the input signal IN2.

Therefore, the sub-transistors N3-1, N4-2, N3-3, N4-4, P3-1, P4-2, P3-3, and P4-4 in the first row of the circuit block 30b can pass through the signal lines 300b, 301b, 306, and 307 obtain input signals IN1, IN2, a first voltage V1, and a second voltage V2. The sub-transistors N4-1, N3-2, N4-3, N3-4, P4-1, P3-2, P4-3, P3-4 in the second row of the circuit block 30b can pass through the signal lines 302b, 303b, 306 and 307 obtain the first voltage V1 and the second voltage V2 of the input signals IN1 and IN2.

In this way, when the cracked CRK occurs in the circuit block 30b, the transistors P3, P4, N3, N4 can still receive the input signals IN1, IN2, the first voltage V1, and the second voltage V2 to operate without causing the circuit area Block 30b is completely disabled.

FIG. 4A is a schematic diagram of a wafer 40 according to an embodiment of the present invention. The chip 40 is provided with a plurality of circuit blocks 10/20/30, power rail lines 400 and 401, and power supply circuits 402 and 403. The power supply circuits 402 and 403 can provide the first voltage V1 to the power rail lines 400 and 401. The circuit block 10/20/30 is coupled to the power rails 400 and 401 to receive the first voltage V1. In one embodiment, the chip 40 may be arranged on a flexible substrate. Due to the flexibility of the flexible substrate Due to the bending characteristics, cracks are more likely to occur in the signal lines 400 and 401 on the flexible substrate.

In detail, the two ends of the power rail 400 are coupled to the power supply circuits 402 and 403. The two ends of the power rail 401 are coupled to the power supply circuits 402 and 403. In this way, the power traces 400 and 402 can jointly form a ring structure to surround the chip 40. In this way, when a crack occurs in the power trajectory 400 or the power trajectory 402, the chip 40 can still stably transmit the first voltage V1 to all circuit blocks through the ring structure of the power trajectories 400 and 402. /30, therefore, no circuit block 10/20/30 in the chip 40 will be disabled due to cracking.

In addition, through the provision of power supply circuits 402 and 403 in the chip 40, the first voltage V1 provided on the power rails 400 and 401 can be stabilized. The attenuation of the first voltage V1 is caused by the impedance of the tracks 400 and 401.

In addition, as circled in FIG. 4A, the power trajectories 400 and 401 may have various implementations. In an embodiment, the power trajectory 401a may be a straight-line connection structure. In another embodiment, the power trajectory 401b can have a square wave-like structure. In this way, when the chip 40 is disposed on a flexible substrate, the power trajectory 401b can provide the chip 40 through the square wave-like structure. When the whole is bent, the flexibility is better and the chip 40 is prevented from cracking.

FIG. 4B is a schematic diagram of a wafer 41 according to an embodiment of the present invention. The chip 41 is provided with a plurality of circuit blocks 10/20/30, power rails 410-413, and power circuits 414-417. The power circuits 414-417 can provide the first voltage V1 to the power rails 410-413. Circuit block 10/20/30 is coupled to power rails 410~413 to receive the first voltage V1. In one embodiment, the chip 41 may be disposed on a flexible substrate. Due to the bendability of the flexible substrate, cracks are more likely to occur in the signal lines 410 to 413 on the flexible substrate.

In detail, the two ends of the power rail 410 are coupled to the power supply circuits 414 and 415. The two ends of the power rail 411 are coupled to the power circuits 415 and 416, the two ends of the power rail 412 are coupled to the power circuits 416 and 417, and the two ends of the power rail 413 are coupled to the power circuits 417 and 414. In this way, the power traces 410 to 413 can jointly form a ring structure to surround the chip 41. In this way, when a crack occurs in one or more of the power rails 410 to 413, the chip 41 can still stabilize the first voltage V1 through the ring structure of the power rails 410 to 413 and the power circuit 414 to 417. The ground is transmitted to all the circuit blocks 10/20/30, therefore, no circuit block 10/20/30 in the chip 41 will be disabled due to cracking.

In addition, by providing power circuits 414 to 417 in the chip 41, the first voltage V1 provided on the power rails 410 to 413 can be stabilized, thereby further improving the power rails 410 to 413 when the first voltage V1 is transmitted. The impedance of the tracks 410-413 causes the attenuation of the first voltage V1.

In summary, in the present invention, different transistors are alternately arranged in the first row and the second row of the circuit block, and input signals are provided to the first row and the second row of transistors through different signal lines. In this way, when cracks occur on the chip, the complete disabling of the circuit block can be effectively avoided.

10: Circuit block

100~108: signal line

IN1, IN2: Input signal

M1-1~M1-4, M2-1~M2-4: Transistor

V1: first voltage

Claims (9)

A chip includes: a circuit block, including: a first transistor divided into a plurality of first sub-transistors connected in parallel with each other; and a second transistor divided into a plurality of first sub-transistors connected in parallel with each other Two sub-transistors, wherein the first sub-transistors and the second sub-transistors are alternately arranged in a first row and a second row of the circuit block, and are arranged in the first row and the second row of the circuit block. The first transistor in the second row receives a first input signal through different signal lines, and the second transistors in the first row and the second row receive a second input signal through different signal lines, respectively . The chip according to claim 1, wherein the first sub-transistors and the second sub-transistors are alternately arranged in each row of the circuit block. The chip according to claim 1, wherein the first transistors arranged in the first row and the second row receive the first input signal through a first signal line and a third signal line, respectively, and are arranged in the The second transistors in the first row and the second row receive the second input signal through a second signal line and a fourth signal line, respectively. The chip according to claim 3, wherein the first signal line and the second signal line are arranged on a first side of the circuit block, and the third signal line and the fourth signal line The signal line is arranged on a second side of the circuit block, the first side is adjacent to the first row, and the second side is adjacent to the second row. The chip according to claim 3, wherein the circuit block further includes: a fifth signal line, two ends of the fifth signal line are respectively coupled to the first signal line and the third signal line; and a sixth signal line A signal line, both ends of the sixth signal line are respectively coupled to the second signal line and the fourth signal line, wherein the first signal line, the third signal line and the fifth signal line surround the first transistor And the second transistor, the second signal line, the fourth signal line, and the sixth signal line surround the first transistor and the second transistor. According to the chip of claim 3, the circuit block further includes a seventh signal line completely surrounding the first transistor and the second transistor, and the first transistor and the second transistor are connected by the seventh transistor. The signal line receives a first voltage. The wafer according to claim 1, wherein the first transistor and the second transistor have the same conductivity type. The chip according to claim 1, wherein the chip further includes: a power track, divided into a first power track and a second power track connected in series, the power track being coupled to the circuit Block; and a power circuit, divided into a first power circuit and a second power circuit, the power circuit is coupled to the power rail, the power circuit provides a first voltage to the circuit through the power rail Block, Two ends of the first power rail are respectively coupled to the first power circuit and the second power circuit, and two ends of the second power rail are respectively coupled to the first power circuit and the second power circuit . The chip according to claim 8, wherein the power track completely surrounds the chip.

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