CN111933641A - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN111933641A CN111933641A CN202011099926.2A CN202011099926A CN111933641A CN 111933641 A CN111933641 A CN 111933641A CN 202011099926 A CN202011099926 A CN 202011099926A CN 111933641 A CN111933641 A CN 111933641A
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 141
- 239000002184 metal Substances 0.000 claims description 63
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 20
- 230000005540 biological transmission Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The invention discloses an electrostatic discharge protection circuit, which comprises an internal integrated circuit, a plurality of signal conversion circuits, a plurality of electrostatic protection modules and wiring among the electrostatic protection modules, wherein the internal integrated circuit comprises a plurality of input/output interfaces with the same array structure, one end of each signal conversion circuit is connected with one input/output interface, and the other end of each signal conversion circuit is connected with an external signal terminal; one end of each electrostatic protection module is connected with the external signal terminal; the signal conversion circuit and the electrostatic protection module which are simultaneously connected with the same external signal terminal are arranged in a non-corresponding mode. The electrostatic discharge protection circuit provided by the invention can reduce the damage of electrostatic discharge to the signal conversion circuit.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an electrostatic discharge protection circuit.
Background
In recent years, in a semiconductor integrated circuit, an electrostatic discharge (ESD) protection line is provided between a signal input terminal and an internal chip in order to prevent electrostatic breakdown due to Static electricity from the outside or the like. In the prior art, the connection between the electrostatic protection circuits generally adopts a minimum path connection mode, which easily causes the signal conversion circuit between the internal chip and the external signal to be damaged by static electricity, and thus the electrostatic shock cannot be effectively protected, the reliability of the semiconductor device is affected, and the service life of the semiconductor device is reduced.
Disclosure of Invention
The invention aims to provide an electrostatic discharge protection circuit, which can realize electrostatic protection on an internal integrated circuit and electrostatic protection on a signal conversion circuit.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides an electrostatic discharge protection circuit, which at least comprises:
an internal integrated circuit including a plurality of input/output interfaces of the same array structure;
a plurality of signal conversion circuits disposed around the internal integrated circuit, one end of each of the signal conversion circuits being connected to one of the plurality of input/output interfaces, the other end of each of the signal conversion circuits being connected to an external signal terminal;
a plurality of electrostatic protection modules, one end of each electrostatic protection module being connected to one of the external signal terminals, each electrostatic protection module being disposed corresponding to one of the plurality of signal conversion circuits;
the signal conversion circuit and the electrostatic protection module which are connected with the same external signal terminal are arranged in a non-corresponding mode, a data connection path is arranged between the signal conversion circuit and the electrostatic protection module which are connected with the same external signal terminal at the same time, and the data connection path is longer than the distance between the signal conversion circuit and the electrostatic protection module which are arranged in a corresponding mode.
In an embodiment of the invention, the esd protection circuit includes a semiconductor substrate and a plurality of metal layers, the plurality of metal layers are disposed on the semiconductor substrate, and the inter-integrated circuit, the plurality of signal conversion circuits and the plurality of esd protection modules are disposed on the semiconductor substrate.
In an embodiment of the invention, the external signal terminal is disposed on another surface of the metal layers opposite to the esd protection modules, and the corresponding positions of the external signal terminal and the esd protection modules are the same.
In an embodiment of the invention, the other end of the electrostatic protection module is connected to a power supply or a ground.
In an embodiment of the invention, each of the external signal terminals is directly connected to the esd protection module at the same position on the other side of the metal layers.
In an embodiment of the invention, a plurality of data connection paths are included between the plurality of esd protection modules and the plurality of conversion circuits, and the plurality of data connection paths constitute the metal layers of different layers.
In an embodiment of the invention, the esd protection circuit includes a first external signal terminal and a second signal conversion circuit, the first external signal terminal is located on one side of the internal integrated circuit, and the second signal conversion circuit is located on the other side of the internal integrated circuit opposite to the first external signal terminal.
In an embodiment of the present invention, the first external signal terminal is connected to one end of the second signal conversion circuit, and a data connection path between the first external signal terminal and the second signal conversion circuit passes through one side of the internal integrated circuit.
In an embodiment of the present invention, the internal integrated circuit includes a first input/output interface, and the first input/output interface is located at one side of the first external signal terminal.
In an embodiment of the invention, the other end of the second signal conversion circuit is connected to the first input/output interface, and a data connection path between the second signal conversion circuit and the first input/output interface passes through one side of the internal integrated circuit.
The esd protection circuit according to the present invention includes the internal integrated circuit, the signal conversion circuits, and the esd protection modules, and the wiring among the parts, wherein the internal integrated circuit includes a plurality of input/output interfaces with the same array structure, the external signal terminal is connected to the corresponding esd protection module, and the other end of the esd protection module is connected to the nearest ground or power supply, so as to obtain the most effective discharging path; the signal conversion circuit and the electrostatic protection module which are connected with the same external signal terminal are arranged in a non-corresponding manner, so that a longer data connection path is obtained, and the damage of electrostatic impact on the signal conversion circuit is effectively reduced; and the other end of the signal conversion circuit is connected with the input/output interface. According to the electrostatic discharge protection circuit provided by the invention, the distance between the external signal terminal and the signal conversion circuit is prolonged, and the damage of electrostatic impact on the signal conversion circuit is reduced while the electrostatic protection on the internal integrated circuit is realized.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a layout diagram of ESD protection.
3 FIG. 3 2 3 is 3 a 3 cross 3- 3 sectional 3 view 3 A 3- 3 A 3' 3 of 3 FIG. 3 1 3. 3
Fig. 3 is another layout diagram of the esd protection circuit of fig. 1.
3 fig. 3 4 3 is 3 a 3 sectional 3 view 3 of 3 a 3- 3 a 3' 3 in 3 fig. 3 3 3. 3
FIG. 5 is a layout diagram of an ESD protection circuit with multiple I/O interfaces having the same array structure.
FIG. 6 is a layout diagram of the ESD protection circuit with the data connection paths on the same side of the IC according to the present invention.
FIG. 7 is a layout diagram of ESD protection with data connection paths on both sides of an inter-IC according to an embodiment of the present invention.
FIG. 8 is a layout diagram of ESD protection with data connection paths on both sides of an inter-IC according to another embodiment of the present invention.
Description of reference numerals:
10 an internal integrated circuit; 20 a signal conversion circuit; 30 an electrostatic protection module; 40 external signal terminals; 101 a first input/output interface; 102 a second input/output interface; 103 a third input/output interface; 104 a fourth input/output interface; 105 a fifth input/output interface; 106 a sixth input/output interface; 201 a first signal conversion circuit; 202 a second signal conversion circuit; 203 a third signal conversion circuit; 204 a fourth signal conversion circuit; 205 a fifth signal conversion circuit; 206 sixth signal conversion circuitry; 301 a first electrostatic protection module; 302 a second electrostatic protection module; 303 a third electrostatic protection module; 304 a fourth electrostatic protection module; 305 a fifth electrostatic protection module; 306 a sixth electrostatic protection module; 401 a first external signal terminal; 402 a second external signal terminal; 403 a third external signal terminal; 404 a fourth external signal terminal; 405 a fifth external signal terminal; 406 a sixth external signal terminal; 500 a semiconductor substrate; 501 a first metal layer; 502 a second metal layer; 60, punching; r1~ R6, R10, R11, R20, R21 data connection path.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The electrostatic discharge circuit provided by the invention can be applied to a semiconductor integrated circuit, and can effectively protect an internal integrated circuit 10 and reduce the damage of electrostatic impact on a signal conversion circuit 20.
Referring to fig. 1, in an embodiment of the invention, the invention provides an esd protection circuit, which includes an internal integrated circuit 10, a plurality of signal conversion circuits 20, a plurality of esd protection modules 30, a plurality of external signal terminals 40, and a wiring between the internal integrated circuit and each external signal terminal, where the wiring is a data connection path. The internal integrated circuit 10 includes a plurality of Input/Output (I/O) interfaces having the same array, and a plurality of signal conversion circuits 20 having the same structure and the same function and arranged around the internal integrated circuit 10 and corresponding to the plurality of Input/Output (I/O) interfaces, and a plurality of electrostatic discharge protection modules 30 having the same number and the same structure and function and arranged corresponding to the plurality of signal conversion circuits 20. Each external signal terminal 40 is connected to one end of an esd protection module 30, the esd protection module 30 discharges the static electricity, each external signal terminal 40 is simultaneously connected to one end of the signal conversion circuit 20, and the other end of the signal conversion circuit 20 is connected to the same Input/Output (I/O) interface of the plurality of arrays on the ic 10.
Referring to fig. 1 to 2, in an embodiment of the invention, the inter-integrated circuit 10, the signal conversion circuits 20 and the esd protection modules 30 are disposed on a semiconductor substrate 500, the semiconductor substrate 500 includes a plurality of metal layers, and the inter-integrated circuit 10, the signal conversion circuits 20 and the esd protection modules 30 are embedded on the semiconductor substrate 500. A plurality of windows, namely, external signal terminals 40 are disposed on the other surfaces of the plurality of metal layers, that is, the other surfaces of the plurality of metal layers, which are opposite to the internal integrated circuit 10, the plurality of signal conversion circuits 20, and the plurality of electrostatic protection modules 30, the external signal terminals 40 are connected to external lines, and data signals are transmitted to external circuits through the external signal terminals 40. In other embodiments, in order to improve the overall layout of the semiconductor integrated circuit and the layout among the internal integrated circuit 10, the plurality of signal conversion circuits 20, and the plurality of electrostatic protection modules 30, the internal integrated circuit 10, the signal conversion circuit 20, and the electrostatic protection module 30 are flexibly disposed on the semiconductor substrate 500 according to the connection path or the actual layout requirement.
Referring to fig. 1 to 2, in an embodiment of the invention, the semiconductor substrate 500 includes a plurality of metal layers, and insulating layers are disposed between different metal layers and between the metal layers and the semiconductor substrate 500, the insulating layers having a signal isolation function, and the number of the metal layers can be set according to the number of devices on the semiconductor substrate 500 and the connection manner. In the present embodiment, the semiconductor substrate 500 includes two metal layers, a first metal layer 501 and a second metal layer 502. The same metal layer comprises a plurality of data connection paths, the data connection paths arranged in the same layer form a metal layer, signal isolation is realized between the metal layers of different layers and between the different data connection paths through the insulating layers, mutual interference between signals is avoided, and data connection paths are arranged between the external signal terminal 40 and the electrostatic protection module 30, between the external signal terminal 40 and the signal conversion circuit 20, and between the signal conversion circuit 20 and the internal integrated circuit 10. In order to prevent the intersection of a plurality of data connection paths and avoid the confusion of data information, the data connection paths which are arranged on the same metal layer and have the intersection phenomenon and the data connection paths which are arranged on the same metal layer and have the signal interference phenomenon are arranged in different metal layers. The data transmission between different metal layers is realized by arranging a through hole 60 between the metal layers of different layers, connecting data connection paths of different metal layers, and realizing the connection between the data connection paths between the metal layers of different layers by filling metal in the through hole 60, and arranging a through hole 60 in an insulating layer between the metal layer and the semiconductor substrate 500, and connecting elements and the metal layers on the semiconductor substrate 500, wherein the through hole 60 is made of a conductive material, and is used for connecting the data transmission between the metal layers of different layers, the elements and the data connection paths.
Referring to fig. 1-2, in an embodiment of the invention, the inter-integrated circuit 10 is disposed on a semiconductor substrate 500, and the inter-integrated circuit 10 is an integrated circuit formed by combining a plurality of devices, which is not limited by the invention. The inter-integrated circuit 10 includes a plurality of Input/Output (I/O) interfaces having the same array structure, for example, 6 Input/Output (I/O) interfaces, which are respectively a first Input/Output (I/O) interface 101, a second Input/Output (I/O) interface 102, a third Input/Output (I/O) interface 103, a fourth Input/Output (I/O) interface 104, a fifth Input/Output (Input/Output, I/O) interface 105, and a sixth Input/Output (Input/Output, I/O) interface 106. The Input/Output (I/O) interfaces have the same array, that is, the Input/Output (I/O) interfaces have the same structure and the same function. In the present embodiment, a plurality of signal conversion circuits 20 are arranged side by side on the side where the internal integrated circuit 10 is arranged, and the number of signal conversion circuits 20 is the same as the number of Input/Output (I/O) interfaces. Each signal conversion circuit 20 is correspondingly provided with an electrostatic protection module 30, a plurality of electrostatic protection modules 30 are also arranged in a row, and the number of the electrostatic protection modules 30 is the same as that of the signal conversion circuits 20. The plurality of signal conversion circuits 20 have the same configuration and function. A plurality of external signal terminals 40 are disposed on the other side of the plurality of metal layers opposite to the other side of the plurality of electrostatic protection modules 30, and each external signal terminal 40 is located at a position opposite to each electrostatic protection module 30 on the other side of the plurality of metal layers.
Referring to fig. 1 to 2, in an embodiment of the present invention, each external signal terminal 40 is directly connected to the corresponding electrostatic protection module 30 on the other side of the metal layers through the data connection path in the metal layers, in this embodiment, the first external signal terminal 401 is directly connected to the first esd protection module 301 through the plurality of metal layers, the second external signal terminal 402 is directly connected to the second esd protection module 302 through the plurality of metal layers, the third external signal terminal 403 is directly connected to the third esd protection module 303 through the plurality of metal layers, the fourth external signal terminal 404 is directly connected to the fourth esd protection module 304 through the plurality of metal layers, the fifth external signal terminal 405 is directly connected to the fifth esd protection module 305 through the plurality of metal layers, and the sixth external signal terminal 406 is directly connected to the sixth esd protection module 306 through the plurality of metal layers. The ESD protection modules 30 are disposed adjacent to a power or ground, and the other end of each ESD protection module 30 is selectively connected to the nearest ground or to the nearest power, depending on its location in the integrated circuit. Each external signal terminal 40 is connected to an esd protection module 30, and a minimum discharge path is formed between the other end of the esd protection module 30 and ground or (power supply), and the discharge path has the most effective esd protection effect, so that when esd occurs, the electrostatic current flowing into a subsequent circuit to cause circuit damage can be reduced.
Referring to fig. 1 to 2, in an embodiment of the invention, after each external signal terminal 40 is connected to the esd protection module 30 to implement esd, each external signal terminal 40 is connected to one end of a signal conversion circuit 20. The electrostatic protection module 30 and the signal conversion circuit 20 connected to the same external signal terminal 40 are not disposed correspondingly, and this connection manner can increase the length of the data connection path between the electrostatic protection module 30 and the signal conversion circuit 20. In the present embodiment, the first external signal terminal 401 is connected to one end of the fourth signal conversion circuit 204, the second external signal terminal 402 is connected to one end of the fifth signal conversion circuit 205, and the third external signal terminal 403 is connected to one end of the sixth signal conversion circuit 206; the fourth external signal terminal 404 is connected to one end of the first signal conversion circuit 201, the fifth external signal terminal 405 is connected to one end of the second signal conversion circuit 202, and the sixth external signal terminal 406 is connected to one end of the third signal conversion circuit 203. To prevent the line crossing, the data connection path R1 between the first external signal terminal 401 and the fourth signal conversion circuit 204, the data connection path R2 between the second external signal terminal 402 and the fifth signal conversion circuit 205, and the data connection path R3 between the third external signal terminal 403 and the sixth signal conversion circuit 206 are disposed at the same metal layer, and the data connection paths between the other external signal terminals 40 and the signal conversion circuit 20 are disposed at another metal layer. In the present embodiment, the data connection path R1, the data connection path R2, and the data connection path R3 are disposed in the second metal layer 502, the data connection paths between the other external signal terminals 40 and the signal conversion circuit 20, including the data connection path R4, the data connection path R5, and the data connection path R6, are disposed in the first metal layer 501, and the through-holes 60 are disposed between the metal layers of different layers, so that the connections between the data connection paths between the metal layers of different layers, between the data connection paths and the external signal terminals, and between the data connection paths and the devices on the semiconductor substrate 500 can be realized. On the basis that the lengths of a plurality of data connection paths between the plurality of signal conversion circuits 20 and the plurality of electrostatic protection modules 30 are similar and the trends are the same, the connection mode strengthens the data connection path between each signal conversion circuit 20 and each electrostatic protection module 30 to the maximum extent, reduces the damage of electrostatic impact on the signal conversion circuits 20, and simultaneously prevents crosstalk between data signals.
Referring to fig. 1 to 2, in an embodiment of the invention, an external signal input from an external signal terminal 40 is converted into an internal signal recognizable by an internal integrated circuit 10 through electrostatic discharge of an electrostatic protection module 30 and signal conversion of a signal conversion circuit 20. Each external signal terminal 40 is connected to its corresponding Input/Output (I/O) interface through the signal conversion circuit 20. In the present embodiment, the first external signal terminal 401 is connected to the first Input/Output (Input/Output, I/O) interface 101 through the fourth signal conversion circuit 204, the second external signal terminal 402 is connected to the second Input/Output (Input/Output, I/O) interface 102 through the fifth signal conversion circuit 205, the third external signal terminal 403 is connected to the third Input/Output (Input/Output, I/O) interface 103 through the sixth signal conversion circuit 206, the fourth external signal terminal 404 is connected to the fourth Input/Output (Input/Output, I/O) interface 104 through the first signal conversion circuit 201, the fifth external signal terminal 405 is connected to the fifth Input/Output (Input/Output, I/O) interface 105 through the second signal conversion circuit 202, the sixth external signal terminal 406 is connected to the sixth Input/Output (Input/Output, I/O) interface 106. Data transmission paths between the first signal conversion circuit 201 and the fourth Input/Output (Input/Output, I/O) interface 104, between the second signal conversion circuit 202 and the fifth Input/Output (Input/Output, I/O) interface 105, and between the third signal conversion circuit 203 and the sixth Input/Output (Input/Output, I/O) interface 106 are disposed in the same metal layer, which is a first metal layer 501, and data transmission paths between other signal conversion circuits 20 and the Input/Output (Input/Output, I/O) interfaces are disposed in another metal layer, which is a second metal layer 502. By such a connection manner, while the data transmission path between the electrostatic protection module 30 and the signal conversion circuit 20 is increased, the difference in the length of the total data transmission path between each external signal terminal 40 and each Input/Output (I/O) interface is small, and the trend of each total data transmission path is similar, so that the time difference in data information transmission between different Input/Output (I/O) interfaces cannot be caused. Wherein the total data transmission path is a sum of data transmission paths from the external signal terminal 40 to the electrostatic protection circuit 30, from the external signal terminal 40 to the signal conversion circuit 20, and from the signal conversion circuit 20 to the Input/Output (I/O) interface.
Referring to fig. 1, in an embodiment of the invention, the signal conversion circuit 20 is a device for converting an internal signal and an external signal, and the signal conversion circuit may be a circuit composed of a group of PMOS or NMOS, or a single PMOS or NMOS, or in some embodiments, a Bipolar Junction Transistor (BJT) or other devices. The esd protection module 30 is a device for protecting the signal conversion circuit 20 and the internal integrated circuit 10 from static electricity, and the specific circuit thereof may be a combination of transistors or a combination of transistors and a ballast resistor, and the invention is not limited thereto.
Referring to fig. 3 to 4, in the circuit design, the esd protection module 30 and the signal conversion circuit 20 connected to the same external signal terminal 40 are usually the esd protection module 30 and the signal conversion circuit 20 correspondingly disposed. The Input/Output (Input/Output, I/O) interfaces are correspondingly arranged in the circuit connection, each Input/Output (Input/Output, I/O) interface has a corresponding signal conversion circuit 20 and an electrostatic protection module 30, and are not shared with other Input/Output (Input/Output, I/O) interfaces, and in the layout of the circuit layout, the signal conversion circuit 20 and the electrostatic protection module 30 which are correspondingly arranged on each Input/Output (Input/Output, I/O) interface are placed at positions corresponding to each other, so that connection among all parts is facilitated. For example, in an embodiment provided by the present invention, the connection manner of the corresponding setting includes: the first external signal terminal 401 is connected to the first electrostatic protection module 301, and then connected to the first signal conversion circuit 201, and the other end of the first signal conversion circuit 201 is connected to the first Input/Output (I/O) interface 101; the second external signal terminal 402 is connected to the second electrostatic protection module 302, and then connected to the second signal conversion circuit 202, and the other end of the second signal conversion circuit 202 is connected to the second Input/Output (I/O) interface 102; the subsequent external signal terminal 40 is connected to the corresponding electrostatic protection module 30, signal conversion circuit 20, and Input/Output (I/O) interface, and the connection and wiring method between the first external signal terminal 401 and the second external signal terminal 402 is referred to. Compared with the connection method provided by the present invention, the connection method of the electrostatic protection module 30 and the signal conversion circuit 20 is relatively short, so that the signal conversion circuit 30 is easily damaged by electrostatic discharge. Modifying it to the connection mode provided by the present invention increases the data connection path between the electrostatic protection module 30 and the signal conversion circuit 20. The signal conversion circuit 20 is more effectively protected from static electricity.
Referring to fig. 1 to 4, in the manufacturing process of the semiconductor device, if the connection method shown in fig. 3 to 4 is used to cause the EDS test failure, it may be modified into the connection method shown in fig. 1 and 2. Because the internal integrated circuit 10 has the Input/Output (I/O) interfaces with the same array structure, and the plurality of signal conversion circuits 20 have the same structure and function, it is equivalent to only changing the device numbers and connection modes of the signal conversion circuits 20, and because the function and structure of each signal conversion module 20 are the same, only changing the wiring modes between the external signal terminal 40 and the signal conversion circuit 20, between the signal conversion circuit 20 and the Input/Output (I/O) interfaces, and thus the damage of the electrostatic discharge to the signal conversion circuit 20 can be reduced. When an ESD failure occurs using the wiring and routing scheme employed in fig. 3-4. In the electrostatic discharge protection circuit with the structure, the ESD characteristic can be improved only by adopting the wiring and wiring mode of the invention, and the ESD characteristic can be improved only by post-stage modification without re-running simulation, so that the cost is saved.
Referring to fig. 5 to 8, in another embodiment of the present invention, the internal integrated circuit 10 includes, for example, 2 Input/Output (I/O) interfaces with the same array structure, which are a first Input/Output (I/O) interface 101 and a second Input/Output (I/O) interface 102, respectively, where the first Input/Output (I/O) interface 101 is located at one side of the internal integrated circuit 10, and the second Input/Output (I/O) interface 102 is located at one side of the internal integrated circuit 10 opposite to the first Input/Output (I/O) interface 101. The first signal conversion circuit 201, the first electrostatic protection module 301, and the first external signal terminal 401 are respectively included on one side of the first Input/Output (I/O) interface 101 according to a distance from the first Input/Output (I/O) interface 101 from near to far. The second signal conversion circuit 202, the second electrostatic protection module 302, and the second external signal terminal 402 are respectively included on one side of the second Input/Output (I/O) interface 102, according to a distance from the second Input/Output (I/O) interface 102 from near to far. The above portions are all disposed on one side of the semiconductor substrate 500.
Referring to fig. 5, in the conventional wiring scheme, a first external signal terminal 401 and a second external signal terminal are connected to a corresponding esd protection module 30 and a corresponding signal conversion circuit 20 at the same time. As shown in fig. 5, the first external signal terminal 401 is connected to one end of the first esd protection module 301 and one end of the first signal conversion circuit 201, and the other end of the first signal conversion circuit 201 is directly connected to the first Input/Output (I/O) interface 101 of the internal integrated circuit 10; the second external signal terminal 402 is connected to both one end of the second esd protection module 302 and one end of the second signal conversion circuit 202, and the other end of the second signal conversion circuit 202 is directly connected to the second Input/Output (I/O) interface 102 of the internal integrated circuit 10.
Referring to fig. 6 to 8, in another embodiment of the present invention, according to a connection and wiring method provided by the present invention, the first external signal terminal 401 is connected to one end of the first esd module 301, and the other end of the first esd module 301 is connected to a ground or a power source. Meanwhile, the first external signal terminal 401 is connected to the second signal conversion circuit 202 through a data connection path R10, the second signal conversion circuit 202 is located on the other side of the internal integrated circuit 10 with respect to the first external signal terminal 401, and the other end of the second signal conversion circuit 202 is connected to the first Input/Output (I/O) interface 101 through a data connection path R11. The second external signal terminal 402 is connected to one end of the second esd protection module 302, while the second external signal terminal 402 is connected to one end of the first signal conversion circuit 201 through a data connection path R20, the first signal conversion circuit 201 is located on the other side of the internal integrated circuit 10 opposite to the second external signal terminal 402, and the other end of the first signal conversion circuit 201 is connected to the second Input/Output (I/O) interface 201 through a data connection path R21, which increases the connection distance between the esd protection module 30 and the signal conversion circuit 20. Meanwhile, in order to prevent the data connection paths from crossing, the data connection path R10 and the data connection path R11 are located in the same metal layer, and the data connection path R20 and the data connection path R21 are located in another metal layer. Referring to fig. 6 to 8, the present invention provides different wiring schemes for the data connection path R10, the data connection path R11, the data connection path R20 and the data connection path R21. In the wiring scheme shown in fig. 6, the data connection path R10, the data connection path R11, the data connection path R20, and the data connection path R21 are located on the same side of the internal integrated circuit 10, the data connection path R10 and the data connection path R11 are located in the same metal layer, and the data connection path R20 and the data connection path R21 are located in another metal layer. In the wiring scheme shown in fig. 7, the data connection path R10 and the data connection path R20 are located on one side of the internal integrated circuit 10, the data connection path R11 and the data connection path R21 are located on the other side of the internal integrated circuit 10 with respect to the data connection path R10, the data connection path R10 and the data connection path R11 are located on the same metal layer, and the data connection path R20 and the data connection path R21 are located on another metal layer. In the wiring scheme shown in fig. 8, the data connection path R10, the data connection path R11, and the data connection path R20 are located on one side of the internal integrated circuit 10, the data connection path R20 is located on the other side of the internal integrated circuit 10 with respect to the data connection path R10, the data connection path R10 and the data connection path R11 are located on the same metal layer, and the data connection path R20 and the data connection path R21 are located on another metal layer.
The invention provides an electrostatic discharge protection circuit, which comprises an internal integrated circuit (10), a plurality of signal conversion circuits (20), a plurality of electrostatic protection modules (30) and wiring among all parts, wherein the internal integrated circuit (10) comprises a plurality of input/output interfaces with the same array structure, an external signal terminal (40) is connected with the corresponding electrostatic protection module (30), and the other end of the electrostatic protection module (30) is connected with the nearest ground wire or power supply to obtain the most effective discharge path; the signal conversion circuit 20 and the electrostatic protection module 30 which are simultaneously connected with the same external signal terminal 40 are not correspondingly arranged, so that a longer data connection path is obtained, and the damage of electrostatic impact on the signal conversion module is reduced. According to the electrostatic discharge protection circuit provided by the invention, the distance between the external signal terminal 40 and the signal conversion circuit 20 is prolonged, and the damage of electrostatic impact on the signal conversion circuit 20 is reduced while the electrostatic protection on the internal integrated circuit 10 is realized.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. An ESD protection circuit, comprising:
an internal integrated circuit including a plurality of input/output interfaces of the same array structure;
a plurality of signal conversion circuits disposed around the internal integrated circuit, one end of each of the signal conversion circuits being connected to one of the plurality of input/output interfaces, the other end of each of the signal conversion circuits being connected to an external signal terminal;
a plurality of electrostatic protection modules, one end of each electrostatic protection module being connected to one of the external signal terminals, each electrostatic protection module being disposed corresponding to one of the plurality of signal conversion circuits;
the signal conversion circuit and the electrostatic protection module which are connected with the same external signal terminal are arranged in a non-corresponding mode, a data connection path is arranged between the signal conversion circuit and the electrostatic protection module which are connected with the same external signal terminal at the same time, and the data connection path is longer than the distance between the signal conversion circuit and the electrostatic protection module which are arranged in a corresponding mode.
2. The ESD protection circuit of claim 1, wherein the ESD protection circuit comprises a semiconductor substrate and a plurality of metal layers disposed on the semiconductor substrate, and wherein the inter-integrated circuit, the plurality of signal conversion circuits, and the plurality of ESD protection modules are disposed on the semiconductor substrate.
3. The ESD protection circuit of claim 2, wherein the external signal terminal is disposed on the other side of the metal layers opposite to the ESD protection modules, and the external signal terminal is located at the same position as the ESD protection modules.
4. The ESD protection circuit of claim 1, wherein the other end of the ESD protection module is connected to a power or ground.
5. The ESD protection circuit of claim 2 wherein each of the external signal terminals is directly connected to the ESD protection module at the same location on the other side of the metal layers.
6. The ESD protection circuit of claim 2, wherein a plurality of data connection paths are included between the ESD modules and the conversion circuits, and the data connection paths form different layers of the metal layer.
7. The ESD protection circuit of claim 1, wherein the ESD protection circuit comprises a first external signal terminal and a second signal conversion circuit, the first external signal terminal is located on one side of the internal IC, and the second signal conversion circuit is located on the other side of the internal IC opposite to the first external signal terminal.
8. The ESD protection circuit of claim 7, wherein the first external signal terminal is connected to one end of the second signal conversion circuit, and the data connection path between the first external signal terminal and the second signal conversion circuit passes through one side of the internal IC.
9. The ESD protection circuit of claim 8, wherein the internal IC includes a first I/O interface, the first I/O interface being located on a side of the first external signal terminal.
10. The esd protection circuit of claim 9, wherein the other end of the second signal conversion circuit is connected to the first input/output interface, and a data connection path between the second signal conversion circuit and the first input/output interface passes through one side of the internal integrated circuit.
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| CN202011099926.2A CN111933641B (en) | 2020-10-15 | 2020-10-15 | Electrostatic discharge protection circuit |
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| CN202011099926.2A CN111933641B (en) | 2020-10-15 | 2020-10-15 | Electrostatic discharge protection circuit |
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| CN111933641B CN111933641B (en) | 2020-12-22 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050262461A1 (en) * | 2004-05-21 | 2005-11-24 | Hsin-Wo Fang | Input/output circuits with programmable option and related method |
| CN104681003A (en) * | 2013-11-29 | 2015-06-03 | 晨星半导体股份有限公司 | Control circuit and signal conversion circuit of display device |
| CN104956475A (en) * | 2013-01-25 | 2015-09-30 | 夏普株式会社 | Semiconductor device |
| US20180204831A1 (en) * | 2015-09-14 | 2018-07-19 | Intel IP Corporation | Advanced node cost reduction by esd interposer |
| US10325901B1 (en) * | 2017-01-05 | 2019-06-18 | Xilinx, Inc. | Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same |
-
2020
- 2020-10-15 CN CN202011099926.2A patent/CN111933641B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050262461A1 (en) * | 2004-05-21 | 2005-11-24 | Hsin-Wo Fang | Input/output circuits with programmable option and related method |
| CN104956475A (en) * | 2013-01-25 | 2015-09-30 | 夏普株式会社 | Semiconductor device |
| CN104681003A (en) * | 2013-11-29 | 2015-06-03 | 晨星半导体股份有限公司 | Control circuit and signal conversion circuit of display device |
| US20180204831A1 (en) * | 2015-09-14 | 2018-07-19 | Intel IP Corporation | Advanced node cost reduction by esd interposer |
| US10325901B1 (en) * | 2017-01-05 | 2019-06-18 | Xilinx, Inc. | Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same |
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Effective date of registration: 20240408 Address after: 230000 No. 88, xifeihe Road, Hefei comprehensive free trade zone, Xinzhan District, Hefei City, Anhui Province Patentee after: Hefei crystal integrated circuit Co.,Ltd. Country or region after: China Address before: No.18-h1105, Yinchun Road, science and technology R & D base, Maigaoqiao entrepreneurship Park, Qixia District, Nanjing, Jiangsu Province, 210000 Patentee before: Nanjing crystal drive integrated circuit Co.,Ltd. Country or region before: China |