KR100631958B1 - Electrostatic discharge protection circuit - Google Patents

Abstract

An ESD protection circuit is provided to improve the ESD protection performance by reducing the number of contacts formed on an N+ region of each diode. An ESD protection circuit includes a first diode connected between an input/output pad and a power voltage line, and a second diode connected between the input/output pad and a ground voltage line. The first diode is provided with a P-type substrate(401), an N-type well(402), a P+ region(403) formed to bar shape in the N-type well, an isolation region(404) for surrounding the P+ region, an N+ region(405) for surrounding the isolation region. A plurality of contacts(406) formed according to the bar shape, and a plurality of second contacts(407) for surrounding the isolation region.

Description

Electrostatic Discharge Protection Circuits {ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT}

1 is a circuit diagram of an input / output circuit of a conventional semiconductor device.

2A is a partial cross-sectional view of an ESD protection unit according to a conventional embodiment.

2B is a partial layout view of an ESD protection unit according to a conventional embodiment.

3 is a partial layout view of an ESD protection unit according to another conventional embodiment.

4 is a partial layout view of an ESD protection unit according to an embodiment of the present invention.

5 is a partial layout view of an ESD protection unit according to another embodiment of the present invention.

6 is a partial layout view of an ESD protection unit according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

401 P-type semiconductor substrate 402 N-type well

403: P + region 404: Separation region

405: N + region 406: P + region contact

407: N + region contact

The present invention relates to an electrostatic discharge protection circuit that can prevent damage to internal devices caused by static electricity.

In general, there are various types of failure modes generated in semiconductor integrated circuits, but electrical overstress and electrostatic discharge (ESD) are referred to as failure modes caused by electrical phenomena. There is this.

Here, the ESD phenomenon is a phenomenon generated by the flow of static electricity, and classified into a human body model (HBM), a machine model (MM), and a charged device model (CDM) according to the causes of static electricity. do. The human body model is an electrostatic phenomenon by the human body, the machine model is an electrostatic phenomenon by contact with the measuring equipment, and the device charging model is a phenomenon in which the static electricity accumulated in the device is discharged instantaneously by instantaneous grounding with the outside.

Since the electrostatic current caused by the ESD phenomenon is concentrated to the most vulnerable portion of the transistor, melting occurs in the junction, the contact, or the gate oxide layer, causing failure. Therefore, in order to protect the inside of the chip from such external ESD, the semiconductor device includes an ESD protection circuit for each pad PAD from which an external signal is received.

1 is a circuit diagram of an input / output circuit of a conventional semiconductor device.

As shown, an input / output circuit of a conventional semiconductor device receives an input / output pad 101 and an input / output pad 101 that receive an external signal from an internal circuit 107 via a resistor 104. Input buffer 106 to transmit to), output buffer 102 to transmit the signal generated in the internal circuit 107 to the outside through the input / output pad 101, from the outside through the input / output pad 101 ESD protection unit 110 for transmitting the applied static electricity through various paths, power clamp unit 103 for transferring the applied static electricity through the ESD protection circuit to the power supply voltage line 108 or ground voltage line 109, and It consists of an NMOS transistor 105 which protects the input buffer 106 from ESD applied via the output pad 101.

Here, the ESD protection unit 110 is composed of two diodes (110a, 110b), the diode (110a) is connected between the power supply voltage line 108 and the input / output pad 101, the diode (110b) It is connected between the input / output pad 101 and the ground voltage line 109. The cathode terminal of the diode 110a is connected to the power supply voltage line 108, the anode terminal of the diode 110a is connected to the cathode terminal of the diode 110b, and the anode terminal of the diode 110b is connected to the ground voltage line. 109 is connected.

The ESD protection unit 110 having such a configuration is a diode (110a, 110b) in the normal operation of the input / output circuit to which the signal voltage between the ground voltage (Vss) and the power supply voltage (Vcc) is applied to the input / output pad 101 ) Are all reverse biased. Therefore, the ESD protection unit 110 is turned off and does not affect the normal operation of the input / output circuit. However, when the static electricity occurs between the input / output pad 101 and the power pads (not shown), the ESD protection unit 110 turns on the diode 110a or the diode 110b to provide an electrostatic discharge path. Static electricity flows into the internal circuit 107 to prevent the internal circuit 107 from being destroyed.

Hereinafter, the configuration of the ESD protection unit 110 will be described in detail with reference to FIGS. 2A and 2B.

2A is a partial cross-sectional view of an ESD protection unit according to a conventional embodiment.

As shown, the diode 110a includes an N-type well 202 formed on the surface of the P-type substrate 201, a P + region 203 formed in a bar shape on the N-type well 202, and a P + region 203. A separation region 204 formed in the N-type well 202 in the form of enclosing), an N + region 205 formed in the N-type well 202 in the form of enclosing the isolation region 204, and formed on the substrate surface. An insulating film 206 is included. Here, the P + region 203 is connected to the input / output pad 101 through the contact 207, and the N + region 205 is connected to the power supply voltage line 108 through the contact 208.

2B is a partial layout view of an ESD protection unit according to an exemplary embodiment. Here, the arrow shown in FIG. 2B indicates the direction in which the electrostatic current flows.

As shown, the diode 110a encloses a plurality of contacts 207 formed at equal intervals along the bar shape on the P + region 203 and the P + region 203 on the N + region 205. And a plurality of contacts 208 formed such that the plurality of contacts are 208. Here, the number of contacts 208 formed on the N + region 205 is formed in a greater number than the number of contacts 207 formed on the P + region 203.

Meanwhile, the plurality of contacts 208 formed in the vertical direction to correspond to the plurality of contacts 207 formed on the P + region 203 serve to prevent a latch-up phenomenon.

The diode 110a having such a structure has a maximum current than the contacts 207 in the middle of the contacts 207 formed on the P + region 203 when an electrostatic current flows through the contact 207 to the P + region 203. There is a problem that more electrostatic current flows to the contacts 207 on the outside.

In detail, the electrostatic current flows only into the N + region contacts 208 formed in parallel with each other among the contacts 207 formed on the P + region 203. However, the outermost of the contacts 207 formed on the P + region 203, that is, the contacts 207 disposed at both ends of the P + region 203, are contacts 208 of a plurality of N + regions surrounding the periphery thereof. A large amount of electrostatic current flows through

In other words, the contacts 208 formed at both side edge adjacent portions of the contacts 207 of the plurality of P + regions among the contacts 208 of the plurality of N + regions are adjacent to both side edges of the contacts 207 of the plurality of P + regions. In addition, it has a relatively high formation density compared to the contacts 208 formed. Accordingly, the contacts 207 located at both ends of the plurality of contacts 207 formed on the P + region 203 receive more electrostatic currents than the contacts 207 located at the center thereof, and thus a large amount of electrostatic currents are generated. It may cause damage.

Accordingly, the ESD protection unit 110 may be configured such that when an electrostatic current flows through the contact 207 to the P + region 203, the contacts 207 at both ends of the contacts 207 formed on the P + region 203 are formed. There is a problem that the ESD protection is poor due to the damage.

In order to solve this problem, conventionally, an ESD protection unit having a structure as shown in FIG. 3 is used.

3 is a partial layout view of an ESD protection unit according to another exemplary embodiment.

As shown, the diode according to another embodiment of the present invention reduces the number of contacts 306 formed on the P + region 303 than the diode shown in FIG. 2, or the P + region (denoted as 'S'). 303) a structure in which the separation region 304 between the outer shell and the N + region 305 is increased.

The diode having such a structure is formed on the contacts 307 at both ends of the contacts 307 formed on the P + region 303 and on the N + region contact 308 for preventing latch-up, that is, the P + region 303. The contact 307 located at both ends of the plurality of contacts 307 formed on the P + region 303 by increasing the distance between the plurality of contacts 307 and the plurality of contacts 308 formed correspondingly in the vertical direction. There is an effect of reducing the electrostatic current flowing into the. In other words, the contacts 307 located at both ends of the contacts formed on the P + region 303 are formed at a sufficient distance from the N + region contacts 308 for preventing the latchup, so that the contacts 307 are located at both ends. There is an effect that the flowing static current is reduced.

However, the diode according to another embodiment of the present invention increases the isolation region 304 between the P + region 303 and the N + region 305 denoted as 'S', so that the P + region 303 is reduced to decrease the area efficiency. There is a problem. In other words, the diode according to another conventional embodiment is a P + region 303 that delivers an electrostatic current as the separation region 304 between the P + region 303 denoted as 'S' and the N + region 305 increases. Decreases. Accordingly, the diode according to another embodiment of the prior art has a problem that the area occupied by the P + region 303 in the diode of the same size is reduced, thereby reducing the ESD protection performance.

In addition, according to another embodiment of the conventional diode, the contacts 307 at both ends of the contacts 307 formed in the P + region 303 are formed at a sufficient distance from the latch-up prevention N + region contacts 308. However, a number of N + region contacts 308 remain around contacts 307 located at both ends. Accordingly, the diode according to another exemplary embodiment is located at both ends due to the plurality of N + region contacts 308 formed around the contacts 307 located at both ends of the contacts 307 formed at the P + region 303. There is a problem that the electrostatic current applied to the contact 307 does not decrease much.

Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to provide an ESD protection unit capable of improving ESD protection performance without reducing the P + region.

In accordance with an aspect of the present invention, an electrostatic discharge having a first diode connected between an input / output pad and a power supply voltage line and a second diode connected between an input / output pad and a ground voltage line. A protection is provided, wherein the first diode comprises: a P-type substrate; An N-type well formed on the P-type substrate; A P + region formed in a bar shape on the N-type well; An isolation region formed in the N-type well and surrounding the P + region; An N + region formed in said N well to surround said isolation region; A plurality of first contacts spaced apart at equal intervals from each other along the bar shape on the P + region; And a plurality of second contacts formed to surround the separation region on the N + region, wherein the contacts formed at adjacent side edges of the plurality of first contacts among the plurality of second contacts are formed in the plurality of second contacts. The formation density is lower than that of the contacts formed outside the edge portions adjacent to both side edges of the one contact.

In the above configuration, the plurality of second contacts are characterized in that they have the same formation density in the remaining portions except for the adjacent portions of both side edges of the plurality of first contacts.

According to another embodiment of the present invention to achieve the above object, a static electricity having a first diode connected between the input / output pad and the power supply voltage line and a second diode connected between the input / output pad and the ground voltage line A discharge protection unit is provided, wherein the second diode comprises: a P-type substrate; A P type well formed on the P type substrate; An N + region formed in a bar shape on the P-type well; An isolation region formed in the P type well and surrounding the N + region; A P + region formed in said P type well and surrounding said isolation region; A plurality of first contacts formed on the N + region and spaced apart at equal intervals from each other along a bar shape; And a plurality of second contacts formed to surround the separation region on the P + region, wherein the contacts formed at adjacent side edges of the plurality of first contacts among the plurality of second contacts are formed in the plurality of second contacts. The formation density is lower than that of the contacts formed outside the edge portions adjacent to both side edges of the one contact.

In the above configuration, the plurality of second contacts are characterized in that they have the same formation density in the remaining portions except for the adjacent portions of both side edges of the plurality of first contacts.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a partial layout view of an ESD protection unit according to an embodiment of the present invention.

As shown, the ESD protection unit according to an embodiment of the present invention is composed of two diodes connected in series between the power supply line and the ground voltage line in the same way as the ESD protection unit shown in FIG. It is made of the same structure.

Diodes provided in the ESD protection unit according to an embodiment of the present invention is a bar on the P-type substrate 401, the N-type well 402 formed on the P-type substrate 401, N-type well 402, respectively A P + region 403 formed in a shape, an isolation region 404 formed in the N-type well 402 and surrounding the P + region 403, and an N + region formed in the N-type well 402 and surrounding the isolation region 404 ( 405, a plurality of contacts 406 formed at equal intervals along the bar shape on the P + region 403, and a plurality of contacts 407 formed to surround the isolation region 404 on the N + region 405. ).

Here, the plurality of contacts 407 formed on the N + region 405 may include a plurality of latchup preventing contacts 407 disposed in a vertical direction to correspond to the plurality of contacts 406 formed on the P + region 403; A plurality of contacts 407 are formed spaced apart from each other in the longitudinal direction along the bar shape of the P + region 403. In addition, the contacts 407 formed at adjacent edges of both ends of the contacts 406 of the plurality of P + regions among the contacts 407 of the plurality of N + regions may be formed in addition to the adjacent portions of both side edges of the contacts 406 of the plurality of P + regions. It has a relatively low formation density compared to the formed contacts 407.

The diode according to the embodiment of the present invention having such a structure significantly reduces the electrostatic current flowing through the contacts 406 at both ends of the contacts 406 formed on the P + region 403 when static electricity is generated. do.

In detail, the contacts 407 on the plurality of N + regions formed at equal intervals in the longitudinal direction along the bar shape of the P + region 403 are formed in fewer numbers than the plurality of contacts 406 on the P + region 403. . That is, the plurality of contacts 407 formed on the N + region 405 are formed at equal intervals from each other except for the dotted line portion 408 shown in the drawing.

Accordingly, according to an embodiment of the present invention, a diode having a contact of an N + region as much as a dashed portion 408 may be adjacent to an adjacent portion of the contacts 406 located at both ends of the plurality of contacts 406 formed on the P + region 403. By reducing the number 406, there is an effect of reducing the electrostatic current flowing to the contacts 406 located at both ends. In other words, only the contacts 407 of the N + region for preventing latchup are adjacent to the contacts 406 located at both ends of the plurality of contacts 406 formed on the P + region 403. Accordingly, the diode according to the embodiment of the present invention reduces the electrostatic current flowing to the contacts 406 located at both ends of the plurality of contacts 406 formed on the P + region 403 when the static electricity occurs, ESD protection performance Has the effect of improving.

For reference, the diode of the ESD protection unit illustrated in FIG. 4 represents the configuration of the diode 110a of the ESD protection unit 110 illustrated in FIG. 1. Although not shown, the diode 110b of the ESD protection unit 110 is different from the diode 110a in that the N-type well 402 is a P-type well, the P + region 403 is an N + region and an N + region 405. This P + region is formed to produce the same effect as the diode 110a.

5 is a partial layout view of an ESD protection unit according to another embodiment of the present invention, and FIG. 6 is a partial layout view of an ESD protection unit according to another embodiment of the present invention.

As shown, the diode of the ESD protection part shown in Figs. 5 and 6 has the same structure as the diode of the ESD protection part shown in Fig. 4 except for the contact of the N + region. That is, in FIGS. 5 and 6, unlike the ESD protection unit illustrated in FIG. 4, the contact 507 and the contact 607 may be selectively applied to the dotted portion 508 of FIG. 5 and the dotted portion 608 of FIG. 6, respectively. Show that you can form. That is, the diode of the ESD protection unit illustrated in FIG. 5 is except for a portion of the plurality of contacts 506 formed on the P + region 503 corresponding to the contacts 506 located at both ends in the dotted line portion 508. The contact 507 is formed in the remaining part. In addition, the diode of the ESD protection unit shown in FIG. 6 contacts the portion of the plurality of contacts 606 formed on the P + region 603 in parallel with the contact 606 located at both ends of the plurality of contacts 606 formed in the dotted line 608. And form 607.

For reference, the diode of the ESD protection unit illustrated in FIGS. 5 and 6 has the same effect as the diode of the ESD protection unit illustrated in FIG. 4.

As described above, the diode according to the present invention reduces the number of contacts in the N + region at adjacent portions with contacts located at both ends of the plurality of contacts formed on the P + region. It is effective to prevent the contacts located at both ends from being destroyed by the electrostatic current. That is, the diode according to the present invention reduces the electrostatic current flowing to both side contacts among the plurality of contacts formed on the P + region when static electricity is generated, and thus can withstand a larger electrostatic current.

In addition, the diode according to the present invention is used in a semiconductor circuit, thereby reducing the pin capacitance. Here, the pin capacitance refers to a capacitance component of each of the external pins of the semiconductor package electrically connected to the pad, and the pin capacitance reduces signal transmission speed and signal integrity.

Looking at this in detail, one of the main components of the pin capacitance is the junction capacitance of the ESD protection. That is, the ESD protection unit has a large area for ESD protection, and there is a problem in that the ESD protection unit is electrically connected to each pad to increase the pin capacitance.

However, the ESD protection unit according to the present invention has the same ESD protection performance as the conventional diode structure and at the same time has a smaller area than the conventional diode structure. That is, although the diode structure shown in FIG. 3 is conventionally used to improve the ESD protection performance, the diode shown in FIG. 3 increases the separation region between the P + region and the N + region, thereby reducing the P + region and decreasing the area efficiency. There is a problem. In contrast, the diode according to the present invention improves ESD protection by reducing the number of contacts formed on the N + region, instead of reducing the number of contacts in the P + region or increasing the isolation region.

Therefore, the ESD protection unit according to the present invention has excellent ESD protection performance in the same area as the conventional one by reducing the number of contacts formed on the N + region. Accordingly, the ESD protection unit according to the present invention has the same ESD protection performance as in the prior art, and reduces the area of contact with each pad by using a smaller area than the conventional one, thereby reducing the pin capacitance than the conventional ESD protection unit. have.

According to the configuration as described above of the present invention, in the ESD protection unit consisting of two diodes, by reducing the number of contacts formed on the N + region of each diode, there is an effect that the ESD protection performance is improved.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (4)

An electrostatic discharge protection unit comprising a first diode connected between an input / output pad and a power supply voltage line and a second diode connected between an input / output pad and a ground voltage line, The first diode, P-type substrate; An N-type well formed on the P-type substrate; A P + region formed in a bar shape on the N-type well; An isolation region formed in the N-type well and surrounding the P + region; An N + region formed in said N well to surround said isolation region; A plurality of first contacts spaced apart at equal intervals from each other along the bar shape on the P + region; And And a plurality of second contacts formed to surround the isolation region on the N + region. Electrostatic discharge, characterized in that the contact formed in the portion adjacent to both side edges of the plurality of first contacts of the plurality of second contacts is lower than the contacts formed outside the edge portion adjacent to both sides of the plurality of first contacts Protection. The method of claim 1, And the plurality of second contacts have the same formation density in the remaining portions except for the adjacent portions of both side edges of the plurality of first contacts. An electrostatic discharge protection unit comprising a first diode connected between an input / output pad and a power supply voltage line and a second diode connected between an input / output pad and a ground voltage line, The second diode, P-type substrate; A P type well formed on the P type substrate; An N + region formed in a bar shape on the P-type well; An isolation region formed in the P type well and surrounding the N + region; A P + region formed in said P type well and surrounding said isolation region; A plurality of first contacts formed on the N + region and spaced apart at equal intervals from each other along a bar shape; And And a plurality of second contacts formed to surround the isolation region on the P + region. Electrostatic discharge, characterized in that the contact formed in the portion adjacent to both side edges of the plurality of first contacts of the plurality of second contacts is lower than the contacts formed outside the edge portion adjacent to both sides of the plurality of first contacts Protection. The method of claim 3, wherein And the plurality of second contacts have the same formation density in the remaining portions except for the adjacent portions of both side edges of the plurality of first contacts.

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