JP2012049444A - Protection circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protection circuit in which ESD strength is improved in a small area.SOLUTION: The protection circuit includes: a first diode in which a direction from a ground potential line to a power supply voltage line is a forward direction of a current; a second diode in which a direction from the ground potential line to a signal line is the forward direction of the current; a third diode in which the direction from the ground potential line to the power supply voltage line is the forward direction of the current; and a fourth diode in which a direction from the signal line to the power supply voltage line is the forward direction of the current. The first and second diodes share a first diffusion layer connected to the ground potential line, and the third and fourth diodes share a second diffusion layer which is connected to the power supply voltage line and has a different conductivity property from the first diffusion layer.

Description

  The present invention relates to a protection circuit and a semiconductor device for protecting a semiconductor element from static electricity.

  2. Description of the Related Art In recent years, semiconductor devices including semiconductor integrated circuits have been miniaturized as the degree of integration has improved, and it has become a challenge to prevent electrostatic breakdown, which is a breakdown phenomenon due to surge inflow due to external electrostatic discharge. .

  A discharge phenomenon that occurs when an electrostatically charged object comes into contact with another object and is called between these objects is called ESD (Electro Static Discharge). When ESD occurs in a semiconductor element, the semiconductor element may be damaged. There are the following three models as typical ESD models. (A) Disruption model that occurs when electric charge charged on the human body touches the device: HBM (Human Body Model), (b) Metal equipment and devices that have a larger capacity than the human body and have a low discharge resistance Destruction model that occurs when a contact occurs: MM (Machine Model), (c) Destruction model that occurs when the device package or lead frame is charged by friction, etc., and this charge is discharged through the device terminals: CDM (Charge Device Model) ), There are three types.

  When ESD occurs, a high current flows through the semiconductor element in a short period of time, so that thermal destruction of the semiconductor element due to Joule heat occurs in the semiconductor element. Furthermore, in recent years, when a MOS transistor, which is the mainstream of LSI (Large-Scale Integration) silicon devices, is used as a semiconductor element, a high electric field due to ESD is applied to the gate oxide film of the MOS transistor, causing dielectric breakdown. In order to avoid such thermal breakdown and dielectric breakdown, various protection circuits are formed between the internal circuit of the semiconductor device and the input / output terminals, and the high voltage surge that flows when ESD occurs is transmitted to the internal circuit. Measures are taken to prevent it. This protection circuit is called an ESD protection circuit.

  As a typical ESD protection circuit, there is a diode method. FIG. 10 is a diagram illustrating an example of a diode-type protection circuit.

  As shown in FIG. 10, the internal circuit 19 of the semiconductor device is connected to a signal input / output terminal 10 via a signal line 13 and is connected to a Vdd terminal 11 and a Vdd line 14 to which a power supply voltage (Vdd) is applied. And a Vss terminal 12, which is a terminal to which a ground potential (Vss) is applied, and a Vss line 15.

  A diode 66 is connected between the signal line 13 and the Vdd line 14. The diode 66 is connected from the signal line 13 to the Vdd line 14 in the forward direction. A diode 67 is connected between the signal line 13 and the Vss line 15. The diode 67 is connected from the Vss line 15 to the signal line 13 in the forward direction. An example of a protection circuit using a diode is disclosed in Patent Document 1.

  In the protection circuit shown in FIG. 10, when a positive voltage higher than Vdd is applied to the input / output terminal 10, the diode 66 connected to the Vdd line 14 is turned on, a current flows through the Vdd line 14, and the signal line 13 The diode 66 passes current through the Vdd line 14 until the voltage is lower than Vdd. On the other hand, when a negative voltage lower than Vss is applied to the input / output terminal 10, the diode 67 connected to the Vss line 15 is turned on, current flows from the Vss line 15, and the voltage of the signal line 13 is higher than Vss. The diode 67 causes a current to flow through the signal line 13 until it becomes. Therefore, regardless of whether positive or negative surge flows into the input / output terminal 10, these surges can be released to the power supply line via the diode 66 or the diode 67, and the internal connected to the signal line 13 The destruction of the circuit 19 can be prevented.

  However, in the above-described circuit, when a negative voltage is applied to the input / output terminal 10 with respect to the Vdd terminal 11, the diode 66 connected to the signal line 13 and the Vdd line 14 may break down. , Current flows in the opposite direction. Since the ESD protection capability when performing an operation involving reverse breakdown of the junction of the diffusion layer of the diode 66 is significantly lower than the ESD protection capability of the forward operation, the diode 66 is easily destroyed. Further, when a current flows in the forward direction through the diode 67 connected to the Vss line 15 and the signal line 13, the current further flows to the Vdd line 14 via the internal circuit 19, thereby destroying the internal circuit 19. End up.

  Therefore, as shown in FIG. 11, a circuit in which a diode 68 serving as a protection element between power supplies is provided between the Vdd line 14 and the Vss line 15 is employed. The diode 68 operates so as to keep the potential difference between the Vdd line 14 and the Vss line 15 constant. Even if a protective transistor whose gate electrode is connected to the Vss line 15 is used instead of the diode 68 as the protection element between power supplies, the same effect as the diode 68 can be obtained.

JP 2002-305254 A (FIGS. 57 and 58)

  In the circuit shown in FIG. 11, the response time from the Vss line 15 to the Vdd line 14 via the diode 68 depends on the length and shape of the Vdd line 14 and the Vss line 15 and the setting location of the diode 68. The reverse response to the electrostatic surge of the diode 66 connected to the signal line 13 and the Vdd line 14 may be slower. In this case, current flows in the reverse direction of the diode 66 connected to the signal line 13 and the Vdd line 14, and the destruction of the diode 66 cannot be prevented. Further, if the response time from the Vss line 15 to the Vdd line 14 via the diode 68 is delayed from the response of the path flowing to the Vdd line 14 via the internal circuit 19, the internal circuit 19 may be destroyed. .

  Thus, when the installation location of the diode 68 cannot be selected so that the function as a power supply protection element can be sufficiently exhibited, the low impedance of the parasitic resistance of the Vdd line 14 cannot be maintained, and the ESD strength is insufficient. In order to compensate for the inability to maintain this sufficiently low impedance, the diode has to use a diode size larger than that which maintains the prescribed ESD intensity in order to compensate for the reverse characteristics when ESD is applied. For this reason, it is necessary to increase the capacitance of the diode by increasing the element area of the diode.

  On the other hand, in recent years, the operating frequency of a processing device that controls a semiconductor device and the transfer rate of signals transferred between semiconductor devices have also been increased, and the propagation time has been shortened. When the operating frequency of the signal transmission bus between semiconductor devices is increased, the influence of the impedance of the signal transmission bus, the input / output terminals of the semiconductor device, or the input / output terminals of the processing device increases, and signal transmission that operates at a high frequency is performed. It is necessary to adjust the input / output terminal capacitance of the semiconductor device connected on the bus to a value suitable for the operating frequency.

  If the input / output terminal capacity is too large, it may cause a delay in the propagation time of the control signal and data and lower the operating frequency of the system. On the contrary, if the input / output terminal capacitance is too small, it is likely to be affected by noise, causing malfunction. In addition, an actual semiconductor device may vary in input / output capacities depending on manufacturing conditions. For this reason, a spare capacity is mounted for adjusting the terminal capacity, and the terminal capacity is optimized by changing the connection of the upper wiring in manufacturing the semiconductor device. However, also in this case, an extra element area is required for the arrangement of the spare capacitor.

  As described above, it is difficult to form an ESD protection circuit having a small area and sufficient ESD strength in a semiconductor device due to recent high integration and miniaturization of the semiconductor device, and further increase in operating frequency and transfer rate. It is becoming.

The protection circuit of the present invention includes
A power supply voltage line for supplying a power supply voltage to the internal circuit and a ground potential line for supplying a ground potential to the internal circuit are connected, and a direction from the ground potential line to the power supply voltage line is a forward direction of current. A first diode
A second diode connected to the signal line connected to the internal circuit and the ground potential line, the direction from the ground potential line to the signal line being a forward direction of current;
A third diode connected to the ground potential line and the power supply voltage line, wherein a direction from the ground potential line to the power supply voltage line is a forward direction of current;
A fourth diode connected to the signal line and the power supply voltage line, wherein a direction from the signal line to the power supply voltage line is a forward direction of current;
The first and second diodes share a first diffusion layer connected to the ground potential line;
The third and fourth diodes are configured to share a second diffusion layer made of a different type of conductive impurity with the first diffusion layer connected to the power supply voltage line.

  According to the present invention, the first parasitic bipolar transistor having the first diffusion layer shared by the first and second diodes as a base electrode and the second diffusion layer shared by the third and fourth diodes are provided. Since the second parasitic bipolar transistor serving as the base electrode is configured, not only the first to fourth diodes but also the first or second parasitic bipolar transistor is turned on against a surge flowing from the outside into the signal line. In operation, the surge can be efficiently discharged to the power supply voltage line or the ground potential line.

The protection circuit of the present invention is
A first diffusion layer connected to a ground potential line for supplying a ground potential to the internal circuit, and a power supply voltage line for supplying a power supply voltage to the internal circuit, the first diffusion layer being A first diffusion diode including a second diffusion layer made of a different conductive impurity, wherein a direction from the ground potential line to the power supply voltage line is a forward direction of current;
A first diffusion layer shared with the first diode; a third diffusion layer connected to a signal line connected to the internal circuit; and a third diffusion layer made of conductive impurities of the same type as the second diffusion layer. A second diode comprising,
A fourth diffusion layer made of the same kind of conductive impurities as the second diffusion layer is connected to the power supply voltage line, and a fourth diffusion layer made of the same kind of conductive impurities as the first diffusion layer is connected to the ground potential line. A third diode comprising 5 diffusion layers;
A fourth diode including the fourth diffusion layer shared with the third diode and a sixth diffusion layer connected to the signal line and made of the same kind of conductive impurities as the first diffusion layer; Have
The first diffusion layer is disposed between the second diffusion layer and the third diffusion layer;
The fourth diffusion layer is arranged between the fifth diffusion layer and the sixth diffusion layer.

  According to the present invention, the first parasitic bipolar transistor has the first diffusion layer shared by the first and second diodes as the base electrode, the second diffusion layer as the collector electrode, and the third diffusion layer as the emitter electrode. And a second parasitic bipolar transistor having a fourth diffusion layer shared by the third and fourth diodes as a base electrode, a fifth diffusion layer as a collector electrode, and a sixth diffusion layer as an emitter electrode is formed. Is done. Therefore, not only the first to fourth diodes but also the first or second parasitic bipolar transistor is turned on in response to a surge flowing into the signal line from the outside, and the surge is applied to the power supply voltage line or the ground potential line. It becomes possible to discharge efficiently.

  According to the present invention, since the surge flowing into the input / output terminal can be efficiently discharged to the power supply voltage line or the ground potential line with the configuration in which the area of the protection circuit is suppressed, the ESD strength can be improved. .

It is a figure which shows one structural example of the protection circuit of 1st Embodiment. FIG. 2 is a cross-sectional view illustrating a configuration example of a protection circuit illustrated in FIG. 1. FIG. 2 is a plan view illustrating an example of a pattern layout of the protection circuit illustrated in FIG. 1. It is sectional drawing which shows the example of 1 structure of the protection circuit of 2nd Embodiment. FIG. 5 is a plan view showing an example of a pattern layout of the protection circuit shown in FIG. 4. In the protection circuit of 2nd Embodiment, it is a top view which shows another example of the connection method of a diffused layer and wiring. In the protection circuit of 2nd Embodiment, it is a top view which shows another example of the layout of P-well and N-well. FIG. 3 is a diagram illustrating a configuration example of a protection circuit according to the first embodiment. FIG. 6 is a diagram illustrating a configuration example of a protection circuit according to a second embodiment. It is a figure which shows an example of a related protection circuit. It is a figure which shows another example of the related protection circuit.

(First embodiment)
The configuration of the protection circuit of this embodiment will be described. FIG. 1 is a diagram illustrating a configuration example of a protection circuit according to the present embodiment. FIG. 2 is a cross-sectional view showing a configuration example of the protection circuit shown in FIG.

  As shown in FIG. 1, the semiconductor device includes an internal circuit 19, a signal line 13, a Vdd line 14, and a Vss line 15. The internal circuit 19 to be protected by ESD is connected to the input / output terminal 10 via the signal line 13, connected to the Vdd terminal 11 via the Vdd line 14, and connected to the Vss terminal 12 via the Vss line 15. Yes.

  The signal line 13 is a wiring for inputting a signal from the input / output terminal 10 to the internal circuit 19, or a wiring for outputting a signal from the internal circuit 19 to the input / output terminal 10. The signal line 13 may serve both of them. The Vdd line 14 is a wiring for supplying a power supply voltage to the internal circuit 19, and the Vss line 15 is a wiring for supplying a ground potential to the internal circuit 19.

  The protection circuit according to the present embodiment includes a diode 16 connected between the signal line 13 and the Vdd line 14, a diode 17 connected between the signal line 13 and the Vss line 15, and a Vdd line 14 and a Vss line. 15, and a diode 20 connected between the Vdd line 14 and the Vss line 15. The diode 16 is connected from the signal line 13 to the Vdd line 14 so that the current direction is forward, and the diode 17 is connected from the Vss line 15 to the signal line 13 so that the current direction is forward. Yes. The diode 20 is connected so that the current direction is forward from the Vss line 15 to the Vdd line 14, and the diode 22 is connected so that the current direction is forward from the Vss line 15 to the Vdd line 14. Has been.

  Next, the structure of the protection circuit of this embodiment will be described with reference to FIG.

  The semiconductor substrate 100 is provided with a P-well 36 containing P-type conductive impurities and an N-well 37 containing N-type conductive impurities. Each of the P-well 36 and the N-well 37 is provided in a region from the surface of the semiconductor substrate 100 to a predetermined depth. In the P− well 36, P + diffusion layers 30, 30 a, 30 b and N + diffusion layers 31, 32 are formed near the surface of the semiconductor substrate 100. In the N-well 37, N + diffusion layers 33, 33 a, 33 b and P + diffusion layers 34, 35 are formed near the surface of the semiconductor substrate 100. An element isolation unit 50 is provided between the N + diffusion layer and the P + diffusion layer. The element isolation unit 50 is, for example, STI (Shallow Trench Isolation).

  The notations “N +” and “N−” in the N + diffusion layer and the N− well represent the concentration of the diffused N-type conductive impurity, and the concentration is N +> N−. It means that. The meaning of this notation is the same for the notation of “P +” and “P−”.

  The diode 20 shown in FIG. 1 has a P + diffusion layer 30 and an N + diffusion layer 31. The diode 17 has a P + diffusion layer 30 and an N + diffusion layer 32. The diode 20 and the diode 17 share the P + diffusion layer 30. The diode 22 shown in FIG. 1 includes an N + diffusion layer 33 and a P + diffusion layer 34. The diode 16 has an N + diffusion layer 33 and a P + diffusion layer 35. The diode 22 and the diode 16 share the N + diffusion layer 33.

  As shown in FIG. 2, the P + diffusion layer 30 is connected to the Vss line 15, the N + diffusion layer 31 is connected to the Vdd line 14, and the N + diffusion layer 32 is connected to the signal line 13. The N + diffusion layer 33 is connected to the Vdd line 14, the P + diffusion layer 34 is connected to the Vss line 15, and the P + diffusion layer 35 is connected to the signal line 13.

  In the configuration example shown in FIG. 2, P + diffusion layers 30 a and 30 b are provided in the P− well 36, and each of the P + diffusion layers 30 a and 30 b is connected to the Vss line 15. With this configuration, as shown in FIG. 2, in the P-well 36, the diode including the P + diffusion layer 30a and the N + diffusion layer 31 functions as the diode 20, and the P + diffusion layer 30b and the N + diffusion layer 32 are provided. A diode including the diode functions as the diode 17. Therefore, it is possible to shunt the surge flowing through the diode 20 or the diode 17.

  Further, N + diffusion layers 33 a and 33 b are provided in the N− well 37, and each of the N + diffusion layers 33 a and 33 b is connected to the Vdd line 14. With this configuration, the diode including the N + diffusion layer 33a and the P + diffusion layer 34 functions as the diode 22, and the diode including the N + diffusion layer 33b and the P + diffusion layer 35 functions as the diode 16. Therefore, similarly to the P-well 36, a surge flowing through the diode 22 or the diode 16 can be shunted also in the N-well 37.

  As will be described later, in the configuration example shown in FIG. 2, the P + diffusion layer 30 and the P + diffusion layers 30a and 30b are connected to each other and formed in one pattern. The N + diffusion layer 33 and the N + diffusion layers 33a and 33b are connected to each other and formed in one pattern.

  The signal line 13, the Vdd line 14, and the Vss line 15 are provided on an insulating film (not shown) formed on the semiconductor substrate 100, and each of the N + diffusion layer and the P + diffusion layer described above is provided. Although they are connected via via plugs (not shown), the configuration is not shown in the figure. In this embodiment, the case where the P + diffusion layers 30a and 30b and the N + diffusion layers 33a and 33b are provided as protection circuits will be described. However, the P + diffusion layers 30a and 30b and the N + diffusion layers 33a and 33b are not provided. Also good.

  Next, a configuration example of the pattern layout of the protection circuit of this embodiment will be described. FIG. 3 is a plan view showing an example of a pattern layout of the protection circuit shown in FIG.

  In FIG. 3, a pattern in which the P + diffusion layers 30, 30 a, 30 b are connected to each other is denoted by reference numeral 30, and a pattern in which the N + diffusion layers 33, 33 a, 33 b are connected to each other is denoted by reference numeral 33.

  As shown in FIG. 3, the patterns of the P + diffusion layer 30 shared by the diodes 20 and 17 are the rectangular pattern 30a on the left side of the figure, the rectangular pattern 30b on the right side of the figure, and the rectangular pattern 30c on the center side of the figure. The rectangular pattern 30d is connected to the lower rectangular pattern 30e in the drawing.

  Along the wiring direction of the Vdd line 14, the signal line 13, and the Vss line 15, the rectangular pattern 30 a of the P + diffusion layer 30, the N + diffusion layer 31 of the diode 20, the rectangular pattern 30 c of the P + diffusion layer 30, and the diode 17 The N + diffusion layer 32 and the rectangular pattern 30b of the P + diffusion layer 30 are sequentially arranged in the P-well 36 from the left side to the right side in FIG. That is, P + diffusion layers and N + diffusion layers are alternately arranged from the left side to the right side in FIG. The rectangular pattern 30 c of the P + diffusion layer 30 is disposed between the N + diffusion layer 31 and the N + diffusion layer 32. Each pattern of the N + diffusion layer 31 and the N + diffusion layer 32 is surrounded by the pattern of the P + diffusion layer 30 at a predetermined distance.

  Subsequently, attention is paid to the N-well 37. As shown in FIG. 3, the pattern of the N + diffusion layer 33 shared by the diodes 22 and 16 is a rectangular pattern 33a on the left side of the figure, a rectangular pattern 33b on the right side of the figure, and a rectangular pattern 33c on the right side of the figure. The rectangular pattern 33d is connected to the lower rectangular pattern 33e in the figure.

  Along the wiring direction, the rectangular pattern 33a of the N + diffusion layer 30, the P + diffusion layer 34 of the diode 22, the rectangular pattern 33c of the N + diffusion layer 33, the P + diffusion layer 35 of the diode 16, and the N + diffusion layer 33 Rectangular patterns 33b are arranged in the N-well 37 in order from the left side to the right side in FIG. That is, N + diffusion layers and P + diffusion layers are alternately arranged from the left side to the right side in FIG. The rectangular pattern 33 c of the N + diffusion layer 33 is disposed between the P + diffusion layer 34 and the P + diffusion layer 35. Each pattern of the P + diffusion layer 34 and the P + diffusion layer 35 is surrounded by the pattern of the N + diffusion layer 33 at a predetermined distance.

  Among a plurality of wirings arranged in parallel in the wiring direction on the same well, among the diode groups that connect between the Vdd line 14 and the signal line 13 or between the signal line 13 and the Vss line 15, By changing the connection between at least one or more between the Vdd line 14 and the Vss line 15, one or more diodes 22 can be formed.

  As described above, the rectangular pattern 30 c of the P + diffusion layer 30 is disposed between the N + diffusion layer 31 and the N + diffusion layer 32. Therefore, a parasitic npn-type bipolar transistor is configured by the P + diffusion layer 30, the N + diffusion layer 31, and the N + diffusion layer 32 arranged in the same P− well 36. This parasitic npn-type bipolar transistor is shown in FIG. The P + diffusion layer 30 functions as a base electrode, the N + diffusion layer 31 functions as a collector electrode, and the N + diffusion layer 32 functions as an emitter electrode.

  Also on the N− well 37 side, as described above, the rectangular pattern 33 c of the N + diffusion layer 33 is disposed between the P + diffusion layer 34 and the P + diffusion layer 35. Therefore, a parasitic pnp bipolar transistor is configured by the N + diffusion layer 33, the P + diffusion layer 34, and the P + diffusion layer 35 disposed in the same N− well 37. This parasitic pnp type bipolar transistor is shown in FIG. The N + diffusion layer 33 functions as a base electrode, the P + diffusion layer 34 functions as a collector electrode, and the P + diffusion layer 35 functions as an emitter electrode.

  These parasitic npn-type bipolar transistor 21 and parasitic pnp-type bipolar transistor 23 form new discharge paths between the Vdd line 14 and the signal line 13 and between the signal line 13 and the Vss line 15. Is possible.

  Next, the operation of the protection circuit of this embodiment will be described.

  In the protection circuit shown in FIG. 1, when a positive voltage higher than Vdd is applied to the input / output terminal 10, the diode 16 connected to the Vdd line 14 is connected in the same manner as the diode 66 of the ESD protection circuit shown in FIG. The diode 16 is turned on until a current flows through the Vdd line 14 and the voltage of the signal line 13 becomes lower than Vdd. Here, in the protection circuit of this embodiment, when a positive voltage higher than Vdd is applied to the signal line 13, a negative potential difference is generated between the base electrode and the emitter electrode of the parasitic pnp bipolar transistor 23, and the collector electrode and the emitter Turns on between the electrodes. Then, a current flows from the signal line 13 to the Vss line 15, and the parasitic pnp bipolar transistor 23 flows a current until the voltage of the signal line 13 becomes lower than Vdd. With the discharge path formed by the parasitic pnp bipolar transistor 23, it is possible to perform discharge more efficiently than the ESD protection circuit shown in FIG.

  On the other hand, when a negative voltage lower than Vss is applied to the input / output terminal 10, the diode 17 connected to the Vss line 15 is turned on similarly to the diode 67 of the ESD protection circuit shown in FIG. A current flows from 15, and the diode 17 flows a current until the voltage of the signal line 13 becomes higher than Vss. Here, in the protection circuit of this embodiment, when a negative voltage lower than Vss is applied to the signal line 13, a positive potential difference is generated between the base electrode and the emitter electrode of the parasitic npn-type bipolar transistor 21, and the collector electrode and the emitter Turns on between the electrodes. Then, current flows from the Vdd line 14 to the signal line 13, and the parasitic npn-type bipolar transistor 21 flows current until the voltage of the signal line 13 becomes higher than Vss. With the discharge path formed by the parasitic npn-type bipolar transistor 21, it is possible to perform discharge more efficiently than the ESD protection circuit shown in FIG.

  Further, since the diodes 20 and 22 are provided as power source protection elements between the Vdd line 14 and the Vss line 15, the internal circuit 19 is destroyed when a surge flows to the Vdd line 14 via the internal circuit 19. Can be prevented. The diode 22 is formed adjacent to the same well as the diode 16 connected to the Vdd line 14, and the diode 20 is formed adjacent to the same well as the diode 17 connected to the Vss line 15. Yes. Therefore, the impedance of the Vdd line 14 and the Vss line 15 can be made extremely low, and the ESD withstand voltage is improved.

  Further, the parasitic npn-type bipolar transistor 21 and the parasitic pnp-type bipolar transistor 23 start to operate at a voltage lower than the breakdown start point of the diodes 16, 17, 20, 22. It is possible to prevent element destruction due to a reverse current accompanying the direction breakdown operation.

  In the protection circuit of this embodiment, two diodes are formed in each of the two types of wells so as to share a diffusion layer made of the same type of conductive impurity as the well, thereby using the shared diffusion layer as a base electrode. Two types of parasitic bipolar transistors are configured. Of the two types of parasitic bipolar transistors, one parasitic bipolar transistor is provided between the power supply voltage line and the signal line, and the power supply voltage is applied when a negative voltage lower than the potential of the ground potential line is applied to the signal line. It operates so that current flows from the line to the signal line. The other parasitic bipolar transistor is provided between the ground potential line and the signal line, and operates so that a current flows through the ground potential line when a positive voltage higher than the potential of the power supply voltage line is applied to the signal line. . Therefore, when ESD is applied to the input / output terminals, the surge can be efficiently discharged to the Vdd line and the Vss line as compared with the protection circuit shown in FIG.

  In addition, when the surge flows into the input / output terminal, it is possible to suppress the occurrence of reverse current due to the breakdown of the junction of the diffusion layer for the ESD protection diode connected to the input / output terminal. The element destruction of the diode can be prevented.

  In addition, since the ESD protection diode connected to the input / output terminal and the power supply protection diode are connected with low impedance, the internal circuit 19 can be prevented from being destroyed.

  Furthermore, an increase in the area for forming a newly added element can be suppressed, and the above-described effects can be obtained with a small area.

(Second Embodiment)
The present embodiment has a configuration that makes it possible to discharge the surge that flows in faster than in the first embodiment. In the protection circuit of the present embodiment, a plurality of configurations in which P + diffusion layers are sandwiched between N + diffusion layers are provided in the P-well, and a plurality of configurations in which N + diffusion layers are sandwiched between P + diffusion layers are provided in the N-well. It has been.

  The configuration of the protection circuit of this embodiment will be described. FIG. 4 is a cross-sectional view showing a configuration example of the protection circuit of the present embodiment. FIG. 5 is a plan view showing an example of a pattern layout of the protection circuit shown in FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  4 and 5, along the wiring direction of the Vdd line 14, the signal line 13 and the Vss line 15, a P + diffusion layer 30, an N + diffusion layer 31, a P + diffusion layer 30, an N + diffusion layer 32,. The P + diffusion layers 30 are arranged in the P-well 36 in order from the left side to the right side in the drawing at a predetermined interval. Thus, a plurality of diodes 20 and 17 are formed by alternately arranging the P + diffusion layers and the N + diffusion layers. In addition, since a plurality of configurations in which the P + diffusion layer 30 is disposed between the N + diffusion layer 31 and the N + diffusion layer 32 are provided, a plurality of parasitic npn-type bipolar transistors 21 are also disposed.

  Subsequently, attention is paid to the N-well 37. As shown in FIGS. 4 and 5, the N + diffusion layer 33, the P + diffusion layer 34, the N + diffusion layer 33, the P + diffusion layer 35,..., The N + diffusion layer 33 are arranged at predetermined intervals along the wiring direction. Are arranged in order from the left side to the right side of the figure. In this way, a plurality of diodes 22 and 16 are formed by alternately arranging the N + diffusion layers and the P + diffusion layers. In addition, since a plurality of configurations in which the N + diffusion layer 33 is disposed between the P + diffusion layer 34 and the P + diffusion layer 35 are provided, a plurality of parasitic pnp bipolar transistors 23 are also disposed.

  In FIG. 5, in order to make the respective electrodes of the parasitic npn-type bipolar transistor 21 on the P-well 36 side easy to understand, the P + diffusion layer 30 is provided with “P + (B)” meaning the type of conductive impurity and the base electrode. N + diffusion layer 31 indicates the type of conductive impurity and “N + (C)” meaning the collector electrode, and N + diffusion layer 32 indicates the type of conductive impurity and emitter electrode “N + (E)”. Is shown. Similarly to the P-well 36 side, in order to make the respective electrodes of the parasitic pnp bipolar transistor 23 on the N-well 37 side easier to understand, the N + diffusion layer 33 includes “N +” which means the type of conductive impurity and the base electrode. (B) ", P + diffusion layer 34 indicates the type of conductive impurity and collector electrode" P + (C) ", and P + diffusion layer 35 indicates the type of conductive impurity and emitter electrode. “P + (E)” is shown.

  According to the present embodiment, as shown in FIG. 4 and FIG. 5, a plurality of diodes serving as inter-power supply protection elements are provided, so that a plurality of parasitic bipolar transistors are also provided. Therefore, in both cases where a positive voltage higher than Vdd is applied to the input / output terminal 10 and a negative voltage lower than Vss is applied to the input / output terminal 10, the surge that flows in causes a plurality of parasitic bipolar transistors to flow. Since it flows via, it becomes possible to discharge a surge faster.

  Note that the method of connecting the diffusion layer and the wiring is not limited to the configuration shown in FIG. FIG. 6 is a plan view showing an example in which the connection method between the diffusion layer and the wiring is different from the configuration shown in FIG.

  As shown in FIG. 5, the N + diffusion layers 31 and 32 in the P− well 36 and the P + diffusion layers 34 and 35 in the N− well 37 are arranged along the wiring direction. Therefore, as shown in FIG. 6, the N + diffusion layer 31 may be connected to the signal line 13 and the N + diffusion layer 32 may be connected to the Vdd line 14. Further, the P + diffusion layer 34 may be connected to the signal line 13 and the P + diffusion layer 35 may be connected to the Vss line 15. The connection destination of the diffusion layer can be changed by switching the via plug between the configuration shown in FIG. 5 and the configuration shown in FIG.

  In this way, by switching the via plug, the wiring to which the diffusion layer is connected can be easily changed. Therefore, when the input / output terminal capacitance is too small, the connection destination of the diffusion layer is the signal line 13, and when the input / output terminal capacitance is too large, the connection destination of the diffusion layer is the Vdd line 14 or Vss line 15. By switching the connection destination, it is possible to adjust the capacity of the input / output terminals without arranging extra spare elements that are not used. Note that the connection method shown in FIG. 6 may be applied to the first embodiment.

  Further, the arrangement of the P-well 36 and the N-well 37 is not limited to the layout shown in FIGS. FIG. 7 is a plan view showing another example of the layout of the P-well and the N-well.

  5 and 6, the P-well 36 and the N-well 37 are arranged in series along the wiring direction. However, as shown in FIG. You may arrange | position in parallel with respect to the wiring direction. In this case, wells are arranged in multiple stages in a direction perpendicular to the wiring direction.

  As shown in FIG. 7, the P + diffusion layer 30 in the P-well 36 is connected to the Vss line 15a, the N + diffusion layer 31 is connected to the Vdd line 14a, and the N + diffusion layer 32 is connected to the signal line 13a. . The N + diffusion layer 33 in the N− well 37 is connected to the Vdd line 14b, the P + diffusion layer 34 is connected to the Vss line 15b, and the P + diffusion layer 35 is connected to the signal line 13b. Although not shown in the drawing, the Vdd line 14a and the Vdd line 14b are connected, the signal line 13a and the signal line 13b are connected, and the Vss line 15a and the Vss line 15b are connected.

  In the case of the layout shown in FIG. 7, each of the signal line, the Vdd line, and the Vss line has a wiring width that is twice the length in the direction parallel to the surface of the semiconductor substrate 100 and perpendicular to the wiring direction. Can be widened. Note that the layout shown in FIG. 7 may be applied to the first embodiment.

  In the first and second embodiments, the case where the directions in which the N + diffusion layers and the P + diffusion layers are alternately arranged is the same in the P-well 36 and the N-well 37 has been described. As long as the direction is parallel to the surface of the semiconductor substrate 100, the P-well 36 and the N-well 37 may be different. For example, when these wirings are designed so that the wiring directions of the Vdd line 14, the signal line 13, and the Vss line 15 are bent 90 degrees in the middle from the left-right direction in FIG. The direction in which the N + diffusion layers and the P + diffusion layers are alternately arranged may be different by 90 degrees between the P-well 36 and the N-well 37.

  Further, in the first and second embodiments, the pattern of the diffusion layer is not limited to the strip pattern shown in FIGS. 3 and 5 to 7. For example, the pattern of the N + diffusion layer 31 and the P + diffusion layer 34 may be configured such that a plurality of rectangular patterns smaller than the strip pattern are provided in the strip pattern region shown in FIG. .

  As described above, the connection method of the diffusion layer and the wiring, the arrangement of the well, the pattern of the diffusion layer, and the direction in which the N + diffusion layer and the P + diffusion layer are alternately arranged are arbitrarily selected according to the convenience of the layout. Is possible.

  Examples of the protection circuit according to the first or second embodiment described above will be described below.

  The protection circuit of this embodiment has a configuration in which the amount of current when the parasitic bipolar transistor is on can be adjusted. In this example, differences from the above-described embodiment will be described in detail.

  The configuration of the protection circuit of this embodiment will be described. FIG. 8 is a diagram showing a configuration example of the protection circuit of this embodiment.

  As shown in FIG. 8, a resistance element 40 is provided between the N + diffusion layer 32 serving as the emitter electrode of the parasitic npn-type bipolar transistor 21 and the signal line 13. A resistance element 41 is provided between the P + diffusion layer 35 serving as the emitter electrode of the parasitic pnp bipolar transistor 23 and the signal line 13.

  As a method of adjusting the resistance values of the resistance element 40 and the resistance element 41, there is a method of increasing or decreasing the number of via plugs connecting the emitter electrode and the signal line 13. According to this method, the resistance value can be adjusted without increasing the area of the resistance elements 40 and 41. When higher accuracy is required for the adjustment of the resistance value or when the current density of the resistance elements 40 and 41 is concerned, a conductive material satisfying the accuracy and current density standards may be used for the wiring or via plug. .

  In this embodiment, the amount of current when the parasitic npn bipolar transistor 21 and the parasitic pnp bipolar transistor 23 are on can be adjusted by the resistance value of the resistance element 40. Therefore, when there is a concern about the thermal destruction of the metal wiring due to overcurrent, the thermal destruction of the metal wiring can be prevented.

  Further, mainly in a low power consumption chip or the like, during the normal operation of the internal circuit 19 (the ESD circuit is not applied to the input / output terminal 10 and the voltage applied to the input / output terminal 10 is in the range of Vss to Vdd. When the leakage current from the Vdd line 14 to the signal line 13 or from the signal line 13 to the Vss line 15 due to the parasitic bipolar transistor is concerned, the leakage current can be suppressed. it can.

  The protection circuit of this embodiment has a configuration in which the current amount when the parasitic bipolar transistor is turned on can be adjusted by a method different from that of the first embodiment. In this example, differences from the above-described embodiment will be described in detail.

  The configuration of the protection circuit of this embodiment will be described. FIG. 9 is a diagram showing a configuration example of the protection circuit of this embodiment.

  As shown in FIG. 9, a resistance element 42 is provided between the P + diffusion layer 30 serving as the base electrode of the parasitic npn bipolar transistor 21 and the Vss line 15. A resistance element 43 is provided between the N + diffusion layer 33 serving as the base electrode of the parasitic pnp bipolar transistor 23 and the Vdd line 14. The adjustment method of the resistance elements 42 and 43 can be performed in the same manner as the resistance elements 40 and 41 of the first embodiment, and detailed description thereof is omitted.

  Also in the present embodiment, by controlling the base current of the parasitic bipolar transistor, the amount of current at the time of on can be adjusted, and the same effect as in the first embodiment can be obtained. This embodiment is effective when the resistance values of the resistance elements 40 and 41 described in the first embodiment cannot be adjusted.

13 Signal line 14 Power supply voltage line (Vdd line)
15 Ground potential line (Vss line)
16, 17, 20, 22 Diode 19 Internal circuit 21 Parasitic npn type bipolar transistor 23 Parasitic pnp type bipolar transistor 30, 34, 35 P + diffusion layer 31, 32, 33 N + diffusion layer 36 P-well 37 N-well 40-43 Resistance element

Claims (14)

A power supply voltage line for supplying a power supply voltage to the internal circuit and a ground potential line for supplying a ground potential to the internal circuit are connected, and a direction from the ground potential line to the power supply voltage line is a forward direction of current. A first diode
A second diode connected to the signal line connected to the internal circuit and the ground potential line, the direction from the ground potential line to the signal line being a forward direction of current;
A third diode connected to the ground potential line and the power supply voltage line, wherein a direction from the ground potential line to the power supply voltage line is a forward direction of current;
A fourth diode connected to the signal line and the power supply voltage line, wherein a direction from the signal line to the power supply voltage line is a forward direction of current;
The first and second diodes share a first diffusion layer connected to the ground potential line;
The protection circuit, wherein the third and fourth diodes share a second diffusion layer made of a different kind of conductive impurity with the first diffusion layer connected to the power supply voltage line. The protection circuit according to claim 1,
The first diode is connected to the power supply voltage line, and has a third diffusion layer made of a conductive impurity of the same type as the second diffusion layer,
The second diode is connected to the signal line, and has a fourth diffusion layer made of a conductive impurity of the same type as the second diffusion layer,
The third diode has a fifth diffusion layer connected to the ground potential line and made of a conductive impurity of the same type as the first diffusion layer,
The fourth diode is connected to the signal line, and includes a sixth diffusion layer made of the same type of conductive impurities as the first diffusion layer,
The first diffusion layer is disposed between the third diffusion layer and the fourth diffusion layer;
The protection circuit, wherein the second diffusion layer is disposed between the fifth diffusion layer and the sixth diffusion layer. The protection circuit according to claim 2, wherein
The first, third and fourth diffusion layers are provided in a first well made of the same type of conductive impurities as the first diffusion layer;
The second, fifth and sixth diffusion layers are provided in a second well made of the same type of conductive impurities as the second diffusion layer;
A plurality of configurations in which the first diffusion layer is arranged between the third diffusion layer and the fourth diffusion layer are arranged in a first direction parallel to the surface of the semiconductor substrate in the first well. And
A plurality of configurations in which the second diffusion layer is disposed between the fifth diffusion layer and the sixth diffusion layer in the second well are arranged in a second direction parallel to the surface of the semiconductor substrate. Arranged protection circuit. The protection circuit according to claim 3,
A plurality of the first diffusion layers provided in the first well are connected to each other;
A protection circuit, wherein a plurality of the second diffusion layers provided in the second well are connected to each other. A first diffusion layer connected to a ground potential line for supplying a ground potential to the internal circuit, and a power supply voltage line for supplying a power supply voltage to the internal circuit, the first diffusion layer being A first diffusion diode including a second diffusion layer made of a different conductive impurity, wherein a direction from the ground potential line to the power supply voltage line is a forward direction of current;
A first diffusion layer shared with the first diode; a third diffusion layer connected to a signal line connected to the internal circuit; and a third diffusion layer made of conductive impurities of the same type as the second diffusion layer. A second diode comprising,
A fourth diffusion layer made of the same kind of conductive impurities as the second diffusion layer is connected to the power supply voltage line, and a fourth diffusion layer made of the same kind of conductive impurities as the first diffusion layer is connected to the ground potential line. A third diode comprising 5 diffusion layers;
A fourth diode including the fourth diffusion layer shared with the third diode and a sixth diffusion layer connected to the signal line and made of the same kind of conductive impurities as the first diffusion layer; Have
The first diffusion layer is disposed between the second diffusion layer and the third diffusion layer;
The protection circuit, wherein the fourth diffusion layer is disposed between the fifth diffusion layer and the sixth diffusion layer. The protection circuit according to claim 5, wherein
The first, second and third diffusion layers are provided in a first well made of the same type of conductive impurities as the first diffusion layer;
The fourth, fifth and sixth diffusion layers are provided in a second well made of the same type of conductive impurities as the second diffusion layer;
A plurality of configurations in which the first diffusion layer is arranged between the second diffusion layer and the third diffusion layer are arranged in a first direction parallel to the surface of the semiconductor substrate in the first well. And
A plurality of configurations in which the fourth diffusion layer is disposed between the fifth diffusion layer and the sixth diffusion layer in the second well are arranged in a second direction parallel to the surface of the semiconductor substrate. Arranged protection circuit. The protection circuit according to claim 6, wherein
A plurality of the first diffusion layers provided in the first well are connected to each other;
A protection circuit, wherein a plurality of the fourth diffusion layers provided in the second well are connected to each other. The protection circuit according to claim 3 or 6,
The first direction and the second direction are the same as the wiring directions of the power supply voltage line, the signal line, and the ground potential line,
The protection circuit, wherein the first well and the second well are arranged in series in the wiring direction. The protection circuit according to claim 3 or 6,
The first direction and the second direction are the same as the wiring directions of the power supply voltage line, the signal line, and the ground potential line,
The protection circuit, wherein the first well and the second well are arranged in parallel to the wiring direction. The protection circuit according to any one of claims 2 to 4,
A first resistance element is provided between the fourth diffusion layer and the signal line;
A protection circuit, wherein a second resistance element is provided between the sixth diffusion layer and the signal line. The protection circuit according to any one of claims 2 to 4,
A first resistance element is provided between the first diffusion layer and the ground potential line;
A protection circuit, wherein a second resistance element is provided between the second diffusion layer and the power supply voltage line. The protection circuit according to any one of claims 5 to 7,
A first resistance element is provided between the third diffusion layer and the signal line;
A protection circuit, wherein a second resistance element is provided between the sixth diffusion layer and the signal line. The protection circuit according to any one of claims 5 to 7,
A first resistance element is provided between the first diffusion layer and the ground potential line;
A protection circuit, wherein a second resistance element is provided between the fourth diffusion layer and the power supply voltage line. Internal circuitry,
A power supply voltage line for supplying a power supply voltage to the internal circuit;
A ground potential line for supplying a ground potential to the internal circuit;
A signal line for inputting a signal to the internal circuit or outputting a signal from the internal circuit;
The protection circuit according to any one of claims 1 to 13,
A semiconductor device.

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