JP2011181848A - Esd protection circuit and semiconductor device equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD protection circuit which has an ESD protecting function for respective circuits from a low breakdown voltage circuit to a high breakdown voltage circuit, and is attained with small layout area. <P>SOLUTION: The ESD protection circuit includes an ESD protecting element 13 between a node NL connected to a power supply terminal VCC_l for outputting a low voltage and a ground line, an ESD protecting circuit 12 between a node NM connected to a power supply terminal VCC_m for outputting an intermediate voltage and a node NL, and an ESD protecting circuit 11 between a node NH connected to a power supply terminal VCC_h for outputting a high voltage and the node NM. An element 18 to be protected which has a low breakdown voltage, an element 17 to be protected which has an intermediate breakdown voltage, and an element 16 to be protected which has a high breakdown voltage are connected between the ground line VSS, and the nodes NL, NM and NH. The ESD protecting circuits 11, 12 and 13 perform ESD protection for the element 16 to be protected, the ESD protecting circuits 12 and 13 perform ESD protection for the element 17 to be protected, and the ESD protecting circuits 13 performs ESD protection for the element 18 to be protected. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an ESD protection circuit for protecting against electrostatic discharge (ESD) due to external static electricity, and a semiconductor device including the ESD protection circuit.

  In general, a semiconductor integrated circuit (IC) is vulnerable to a surge voltage generated by ESD and is easily destroyed. Therefore, normally, an ESD protection circuit for protecting the IC from a surge voltage is provided in the IC.

  As an example of a circuit for ESD protection, a circuit using a gate-grounded NMOS (ggNMOS) transistor in which the gate and source of an NMOS transistor are connected to a ground potential (GND) has been proposed. For example, the circuit example shown in FIG. 13 includes a ggNMOS transistor 91 as an electrostatic protection circuit and is connected in parallel with an internal circuit 92 that is a protected circuit.

  Since the ggNMOS transistor 91 has a gate and a source that are short-circuited, the ggNMOS transistor 91 normally shows an off state when a normal signal voltage Vin is applied to the signal line SE. However, when an overvoltage Vsur much larger than Vin is applied to the signal line SE, the pn junction between the drain of the ggNMOS transistor 91 and the substrate is reverse-biased, and breakdown occurs. At this time, impact ionization occurs immediately below the drain, and a large number of holes are generated, thereby increasing the potential of the substrate. When the substrate potential reaches 0.6 V, a parasitic bipolar transistor having a drain as a collector, a source as an emitter, and a semiconductor substrate as a base is activated (snapback operation). With this operation, the overvoltage Vsur applied to the drain can be discharged to the ground line VSS to which the source is connected via the parasitic NPN bipolar transistor. As a result, the voltage of the signal line SE decreases to the sustain voltage Vh defined by the product of the collector-emitter resistance and the collector current. Therefore, a high current derived from the overvoltage Vsur does not flow in the internal circuit 92, and the internal circuit 92 is protected.

  After the parasitic NPN bipolar transistor operates and a current path is formed between the drain and the source, both the current and voltage between the collector and the emitter rise, and the heat generated in the silicon reaches 1420 ° C., which is the melting point of silicon. Then, the NMOS transistor 91 is destroyed.

  An ESD protection element using this snapback phenomenon is very effective as a protection element for a low breakdown voltage circuit, but has the following problems when used as a protection element for a high breakdown voltage circuit.

  When the ESD protection element is used as a protection element for a high voltage circuit, it is necessary to configure the ESD protection element as a high voltage device. When the ESD protection element is configured as a high breakdown voltage element, it is realized by forming the gate electrode of the ggNMOS transistor on a thick oxide film. Usually, the end portion of the gate electrode is disposed on a LOCOS (Local Oxidation of Silicon) oxide film. When an overvoltage Vsur is applied under such a configuration, the electric field concentrates in the portion of the LOCOS oxide film located below the end of the gate electrode, and a large amount of electrons are trapped in the defect layer of the thick oxide film, It will cause local leaks and destruction. As a result, the ESD protection element may be destroyed immediately after the snapback phenomenon occurs.

  Further, even if the ESD protection element is not destroyed immediately after the occurrence of the snapback phenomenon, the impedance between the drain and the source is rapidly lowered by the operation of the parasitic bipolar transistor, and as described above, the voltage applied to the ESD protection element is the overvoltage Vsur. To the sustain voltage Vh.

  Usually, the diffusion structure of a transistor formed as an ESD protection element is the same as that of a transistor used in the protected element. If the rated voltage of the protected element is higher than the rated voltage of the ESD protective element, the ESD protective element is destroyed by the snapback operation. This is because when the rated voltage of the protected element is higher than the rated voltage of the ESD protective element, the sustain voltage Vh is lower than the rated voltage of the protected element. However, on the other hand, a power supply voltage corresponding to the rated voltage of the protected element is supplied from the power supply circuit. For this reason, since a power supply voltage higher than the sustain voltage is continuously supplied to the parasitic bipolar transistor formed by the ESD protection element, an excessive current flows from the power supply circuit to the ESD protection element. As a result, the ESD protection element is destroyed due to heat generation inside the ESD protection element. In order to avoid such a situation, the maintenance voltage Vh must be set higher than the rated voltage of the protected element.

  Some ESD protection elements that do not use the snapback phenomenon use diodes. However, when a diode is used as an ESD protection element, the on-resistance during operation is very large. Therefore, if a sufficient current is applied to protect the internal circuit, the diode will occupy to reduce the on-resistance. The area needs to be increased, and a very large layout area is required.

  In order to solve such problems, the following techniques have been proposed.

The configuration of the ESD protection element disclosed in Patent Document 1 is shown in FIG. The ESD protection circuit 100 shown in FIG. 14 has a high-concentration N-type (N ⁺ -type) sink that extends from below the high-concentration N-type impurity diffusion layer (N ⁺⁺ layer) 107 that forms the collector contact layer to below the field oxide film 108. A feature is that the layer 103 is provided and the horizontal width X is sufficiently secured.

More specifically, the ESD protection circuit 100 forms an N-type epi layer 102 on a P-type substrate 101, and forms an N ⁺ -type sink layer 103 from this surface. Further, on the surface of the N-type epi layer 102, the base layer is separated from the N ⁺ -type sink layer 103 in the horizontal direction, and a low-concentration P-type impurity diffusion layer (P ⁻ layer) 104 and a high-concentration P-type impurity diffusion layer (P ⁺ Layer) 105 is formed. In the P ⁺ layer 105, a high concentration N-type impurity diffusion layer (N ^{+ +} layer) 106 serving as an emitter is formed. Further, an N ⁺⁺ layer 107 for contact is provided on the N ⁺ type sink layer 103, and a field oxide film 108 is provided between the N ⁺⁺ layer 107 and the N ⁺⁺ layer 106.

When an overvoltage is applied to the ESD protection element shown in FIG. 14, breakdown occurs at a breakdown voltage (breakdown voltage) determined by the separation between the P ⁻ layer 104 and the N ⁺ type sink layer 103. The parasitic NPN bipolar transistor starts the transistor operation by the current flowing at this time, and the current flows from the collector to the emitter. More specifically, the current flowing by the transistor operation passes from the collector contact N ⁺⁺ layer 107 through the N ⁺ type sink layer 103 located below the field oxide film 108, through the N type epi layer 102, P ⁻ layer 104, P ⁺ by the path of the layer ^{105, N ++} layer 106, it flows toward the emitter.

As shown in FIG. 14, a part of the N ⁺ -type sink layer 103 is formed so as to be located below the field oxide film 108, and the formation width X is widened, so that the N ⁺ -type sink layer 103 has a built-in resistance. Is formed, and a voltage drop occurs in the region. As a result, the sustain voltage Vh can be increased as compared with the case where the region of the high concentration N-type sink layer 103 is not provided below the field oxide film 108.

  FIG. 15 shows a configuration of an ESD protection element disclosed in Patent Document 2 and a semiconductor device including the ESD protection element. The ESD protection element 110 shown in FIG. 15 is characterized in that, in addition to the ggNMOS transistor 111, a bipolar transistor 112 whose base is opened is provided in series.

  More specifically, the NMOS transistor 117 is connected in parallel with the ESD protection element 110, the gate is connected to the drive circuit 116, the drain is connected to the power supply Vo via the load 119, and the source is connected to the ground line. . In the ESD protection element 110, an NPN bipolar transistor 112 whose base is opened and a ggNMOS transistor 111 are connected in series. The collector of the NPN bipolar transistor 112 is connected to the drain of the NMOS transistor 117, and the emitter is connected to the drain of the ggNMOS transistor 111. The ggNMOS transistor 111 has a gate and a source connected to the ground line. Reference numeral 118 denotes an output terminal.

  When configured in this manner, the withstand voltage of the ESD protection element 110 is defined as the sum of the withstand voltage of the bipolar transistor 112 and the withstand voltage of the ggNMOS transistor 111. In this case, the sustain voltage Vh between both ends of the ESD protection element after breakdown is the sum of the collector-emitter voltage of the parasitic bipolar transistor formed by the ggNMOS transistor 111 and the collector-emitter voltage of the bipolar transistor 112. Become. Therefore, the sustain voltage Vh can be increased as compared with the case where the bipolar transistor 112 is not present.

JP 2007-242923 A JP 2007-227697 A

However, in the case of Patent Document 1, since the parasitic resistance increases by widening the formation width of the N ⁺ -type sink layer 103, a sufficient current for protecting the internal circuit can be supplied when a surge voltage is applied. As a result, there is a concern that the protection capability will decrease. As a countermeasure, it is necessary to increase the size of the protective element itself to reduce the resistance value, which inevitably increases the layout area of the ESD protective element.

  In addition, in the case of Patent Document 2, since an additional bipolar transistor is required as an ESD protection element in addition to a ggNMOS transistor, the layout area is naturally increased as compared with the case where the ESD protection element is realized with only a ggNMOS transistor. The result will be forced.

  In view of the above problems, the present invention provides an ESD protection circuit that has an ESD protection function for each circuit from a low voltage circuit to a high voltage circuit and that can be realized with a small layout area, and a semiconductor device including the same. With the goal.

In order to achieve the above object, an ESD protection circuit of the present invention is an ESD protection circuit provided in a semiconductor device having a plurality of power supply terminals of different power supply voltages,
A first ESD protection element having one end connected to a first node connected to the first power supply terminal and the other end connected to a ground line and electrically separated from the semiconductor substrate;
One end is connected to a second node connected to a second power supply terminal having a higher voltage than the first power supply terminal, and the other end is connected to the first node, and a second ESD protection element electrically isolated from the semiconductor substrate It has the 1st characteristic to have.

In addition to the above-described characteristics, the ESD protection circuit of the present invention is configured such that the plurality of power supply terminals are connected to different nodes, respectively.
Between a set of nodes whose voltage values of the connected power supply terminals differ by one step, one end is connected to the high voltage side node and the other end is connected to the low voltage side node, respectively, and A separate ESD protection element,
A second feature is that the ESD protection element is provided between each set of nodes whose voltage values differ by one level.

  Each of the ESD protection elements can be constituted by a semiconductor element that performs a snapback operation, a diode, or a series circuit including a plurality of one or both of them. As an example of a semiconductor element that performs a snapback operation, a MOS transistor (ggMOS) whose gate and source are short-circuited and a bipolar transistor whose emitter and base are connected can be used.

The semiconductor device of the present invention is
The ESD protection circuit having the first feature, a first protected element having one end connected to the first node and the other end connected to the ground line, one end connected to the second node, and the other end connected to the ground A second protected element connected to the wire,
The second protected element is a higher breakdown voltage element than the first protected element.

The semiconductor device of the present invention is
An ESD protection circuit having the second feature, and protected elements having different breakdown voltages between the nodes and the ground line,
The protected element is a high withstand voltage element as the output voltage from the power supply terminal connected to the node connected to the protected element is higher.

  According to the ESD protection circuit of the present invention, if an overvoltage is applied and a surge current flows through the protection circuit, then the sustain voltage generated between the node to which the overvoltage is applied and the ground line is This is the sum of the sustain voltages at both ends of each ESD protection element formed between the node and the ground line. Therefore, a high voltage can be secured at the node after the overvoltage is applied without increasing the sustain voltage of each ESD protection element. By setting this voltage value to a value higher than the rated voltage of the protected element, it is possible to prevent an overcurrent from being generated from the power supply circuit to the ESD protective element, thereby destroying the element.

  And according to this structure, since it is not necessary to provide the horizontal separation between an emitter and a collector like patent document 1, an expansion of an occupation area is not caused.

  Further, protected elements having different breakdown voltages can be connected to nodes to which the respective ESD protection elements are connected. That is, a low breakdown voltage protected element can be connected to a node connected to a power supply terminal having a low output voltage, and a high breakdown voltage protected element can be connected to a node connected to a power supply terminal having a high output voltage. At this time, the ESD protection element connected to the node connected to the power supply terminal having a low output voltage also functions as an ESD protection element for the protected element having a low breakdown voltage, and a part of the ESD protective element for the protected element having a high breakdown voltage. Also works.

  That is, the withstand voltage of each ESD protection element can be kept low as compared with the case where the ESD protection design is performed in accordance with an element with a high withstand voltage. For example, in the case of Patent Document 2, since each ESD protection element is configured by a series circuit of a ggNMOS transistor and a bipolar transistor, the size of each ESD protection element inevitably increases. However, in the case of the configuration of the present invention, since the protection element for high withstand voltage is also used as the protection element for low withstand voltage, the increase in size is minimized even in the configuration using a plurality of protection elements. It is possible to suppress it.

Conceptual block diagram of a semiconductor device with an ESD protection function of the present invention Conceptual circuit diagram of semiconductor device with ESD protection function of the present invention Schematic cross-sectional structure diagram of the ESD protection circuit of the present invention TLP evaluation measurement data for the ESD protection circuit of the present invention Another conceptual block diagram of a semiconductor device with an ESD protection function of the present invention Another conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention Another schematic cross-sectional structure diagram of the ESD protection element of the present invention Another conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention Another conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention Another conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention Another conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention Another conceptual circuit diagram of a semiconductor device with an ESD protection function of the present invention Circuit example including ESD protection circuit Configuration example of conventional ESD protection circuit Configuration example of conventional ESD protection circuit

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a conceptual block diagram showing the concept of the semiconductor device of the present invention. The semiconductor device 1 shown in FIG. 1 has a plurality of power supply terminals (VCC_h, VCC_m, VCC_l) having different power supply voltages.

  The node NH is connected to a high-voltage power supply terminal VCC_h, and the node NL is connected to a power supply terminal VCC_l having a lower voltage than VCC_h. The node NM is connected to a power supply terminal VCC_m having an intermediate voltage that is lower than VCC_h and higher than VCC_l.

  A semiconductor device 1 shown in FIG. 1 includes, as internal circuits, a protected element 16 that uses a voltage supplied from a power supply terminal VCC_h for high voltage output as a power supply voltage, and a voltage supplied from a power supply terminal VCC_m for intermediate voltage output. Is used as the power supply voltage, and the protected element 18 is used as the power supply voltage using the voltage supplied from the power supply terminal VCC_l for low voltage output. The protected elements 16, 17, and 18 are configured so that a higher voltage is applied in this order as the power supply voltage, and the rated voltage is also higher in this order.

  The semiconductor device 1 of the present invention is characterized in that an ESD protection element is provided between each node to which a different voltage is applied. That is, as shown in FIG. 1, the ESD protection circuit 10 included in the semiconductor device 1 includes a first ESD protection element 11 provided between the high voltage node NH and the intermediate voltage node NM, and a low voltage between the intermediate voltage node NM and the intermediate voltage node NM. A second ESD protection element 12 provided between the voltage nodes NL and a third ESD protection element 13 provided between the low voltage node NL and the ground line VSS are included. These ESD protection elements 11 to 13 are all electrically separated from the semiconductor substrate.

  In the case of the configuration shown in FIG. 1, the low breakdown voltage protected element 18 is protected from ESD by the ESD protection element 13, and the intermediate breakdown voltage protected element 17 is protected from ESD by the series connection of the ESD protection elements 12 and 13. The high breakdown voltage protected element 16 is protected from ESD by the series connection of the ESD protection elements 11, 12, and 13.

  When the surge voltage Vsur_h is applied from the high-voltage power supply terminal VCC_h, a surge current flows through the ESD protection element 11, the ESD protection element 12, and the ESD protection element 13 in this order to the ground line VSS. Accordingly, the voltage between the node NH and the ground line VSS can be instantaneously reduced without applying the surge voltage Vsur_h to the protected element 16 having a high breakdown voltage, and the protected element 16 is protected. . Note that the voltage generated between the ground line VSS and the node NH due to the surge current flows from the surge voltage Vsur_h to the sustain voltage Vh13 of the ESD protection element 13, the sustain voltage Vh12 of the ESD protection element 12, and the ESD protection element 11. Decreases to the sustain voltage Vh1 defined by the sum of the sustain voltages Vh11.

  Similarly, when the surge voltage Vsur_m is applied from the intermediate voltage power supply terminal VCC_m, the surge current flows through the ESD protection element 12 and the ESD protection element 13 in this order to the ground line VSS. As a result, the applied voltage between the node NM and the ground line VSS can be instantaneously reduced without applying the surge voltage Vsur_m to the protected element 17 having the intermediate withstand voltage, and the protected element 17 is protected. The The voltage generated between the ground line VSS and the node NM due to the surge current flowing is defined by the sum of the sustain voltage Vh13 of the ESD protection element 13 and the sustain voltage Vh12 of the ESD protection element 12 from the surge voltage Vsur_m. The voltage drops to the sustain voltage Vh2.

  Similarly, when the surge voltage Vsur_l is applied from the low-voltage power supply terminal VCC_l, a surge current flows through the ESD protection element 13 to the ground line VSS. As a result, the applied voltage between the node NL and the ground line VSS can be instantaneously reduced without applying the surge voltage Vsur_l to the protected element 18 having a low breakdown voltage, and the protected element 18 is protected. The In addition, when the surge current flows, the voltage generated between the ground line VSS and the node NL decreases from the surge voltage Vsur_l to the sustain voltage Vh13 of the ESD protection element 13.

As described above, when the protected element has a high breakdown voltage, it is necessary to increase the sustain voltage after the surge current flows to some extent. Here, as described above, the sustain voltage Vh1 between the node NH to which the high breakdown voltage protected element 16 is connected and the ground line VSS, between the node NM to which the intermediate breakdown voltage protected element 17 is connected and the ground line VSS. Sustain voltage Vh2, sustain voltage Vh3 between node NL to which protected element 18 having a low breakdown voltage is connected and ground line VSS are expressed by the following equation 1, respectively.
(Equation 1)
Vh1 = Vh13 + Vh12 + Vh11
Vh2 = Vh13 + Vh12
Vh3 = Vh13

  The protected element is naturally set to have a higher withstand voltage as the rated voltage is higher. Then, according to Equation 1, the sustain voltage is higher as the protected element has a higher breakdown voltage. Therefore, by selecting and using an ESD protection element in which Vh11, Vh12, and Vh13 have appropriate values, the voltages (sustain voltages) of the nodes NH, NM, and NL are maintained even after the surge current is lost to the ground line VSS. It is possible to set the voltage higher than the rated voltage of the protected elements (16 to 18) connected to each node. This setting prevents overcurrent from flowing from the power supply terminals (VCC_h, VCC_m, VCC_l) to which the power supply voltage is applied to the ESD protection element after the surge current is lost to the ground line VSS. be able to.

  In the case of the configuration of the present invention, the ESD protection element 13 for the low breakdown voltage protected element 18 is also used as a part of the ESD protection element 17 for the intermediate breakdown voltage protected element 17 and the high breakdown voltage protected element 16, The ESD protection element 12 for the protected element 17 is also used as a part of the ESD protection element for the protected element 16 having a high breakdown voltage.

  Therefore, when an overvoltage is applied to the protected element 16 having a high breakdown voltage via the node NH, the breakdown voltage Vt1 between the node NH and the ground line VSS is equal to the breakdown voltage Vt11 of the ESD protection element 11 and the ESD protection element 12. It is defined as the sum of the withstand voltage Vt12 and the withstand voltage Vt13 of the ESD protection element 13. Similarly, when an overvoltage is applied to the protected element 17 having the intermediate breakdown voltage via the node NM, the breakdown voltage Vt2 between the node NM and the ground line VSS is equal to the breakdown voltage Vt12 of the ESD protection element 12 and the ESD protection element 13. Is defined as the sum of the breakdown voltage Vt13. Furthermore, when an overvoltage is applied to the protected element 18 having a low breakdown voltage via the node NL, the breakdown voltage Vt3 between the node NL and the ground line VSS is defined as the breakdown voltage Vt13 of the ESD protection element 13. In summary, this is expressed as the following formula 2.

(Equation 2)
Vt1 = Vt13 + Vt12 + Vt11
Vt2 = Vt13 + Vt12
Vt3 = Vt13

  In other words, according to the configuration of the present invention, the breakdown voltage (breakdown voltage) of the ESD protection element for the protected element 16 having a high breakdown voltage is defined by the sum of the breakdown voltages of the three protection elements (11, 12, 13). Therefore, it is not necessary to design each protection element as a high breakdown voltage element. That is, if the protective element is formed of a ggNMOS transistor, it is not necessary to increase the thickness of the oxide film below the gate electrode of the transistor, so that the possibility of local leakage or destruction when applying a surge voltage is reduced.

  In addition, the size of the ESD protection element can be reduced according to the withstand voltage of the protected element, compared with the case where the ESD protection design is made in accordance with the highest withstand voltage protected element, so that the layout occupation area is reduced as a whole. Contribute to.

  FIG. 2 shows an example of a circuit diagram of the block diagram shown in FIG. FIG. 3 shows a schematic cross-sectional structure diagram of the ESD protection circuit 10 at this time. 2 and 3, the case where ggNMOS transistors (TH, TM, TL) are employed as the ESD protection elements 11, 12, 13 is shown.

  The ESD protection circuit 10 is formed on the P-type semiconductor substrate 21. As for the ESD protection element 11 and the ESD protection element 12, a deep N-type well 22 (42) is provided on the substrate 21, and an N-type well 23 (43) and a P-type well 24 (44) are further formed in the well. ing. As for the ESD protection element 13, an N-type well 53 and a P-type well 54 are formed on the substrate 21.

  The surface region in the P-type well 24 (44, 54) has a high-concentration N-type impurity diffusion region 25 (45, 55) serving as a source and a high-concentration P-type impurity diffusion region 26 (46, 56) for contact. In addition, a high concentration N-type impurity diffusion region 27 (47, 57) serving as a drain is provided so as to straddle the N-type well 23 (43, 53) and the P-type well 24 (44, 54). In addition, a gate oxide film 28 is formed in the active region on the substrate surrounded by the field oxide film 31, and a region sandwiched between the source 25 (45, 55) and the drain 27 (47, 57) among the upper layers. A gate electrode 29 is formed at a position above the.

  The power supply terminal VCC_h for high voltage output is connected to the drain 27. In addition, the intermediate voltage output power supply terminal VCC_m is connected to the drain 47 and to the gate electrode 29, the source 25, and the contact 26 of the high breakdown voltage ESD protection element 11. The low-voltage output power supply terminal VCC_l is connected to the drain 57 and also to the gate electrode 29, the source 45, and the contact 46 of the ESD protection element 12 having an intermediate withstand voltage.

  In FIG. 2, the diode DH illustrated in the ESD protection circuit 10 includes a deep N-type well 22 and a P-type semiconductor substrate 21, and the diode DM includes a deep N-type well 42 and a P-type semiconductor substrate 21. Composed.

  In the case of such a configuration, it is not necessary to provide a large distance in the horizontal direction between the source and the drain as shown in FIG. 14, and therefore it is not necessary to increase the size of the protection element itself in order to reduce the parasitic resistance. Further, as described above, the withstand voltage of the ESD protection circuit 10 with respect to the protected element 16 having a high withstand voltage is the sum of the withstand voltages of the ESD protection elements 11, 12, 13; Therefore, a sufficiently high breakdown voltage can be secured even if the breakdown voltage of each transistor is designed to be low.

  FIG. 4 shows TLP (Transmission Line Pulsing) evaluation actual measurement data for the ESD protection circuit 10 shown in FIG. In FIG. 4, F_l is a curve showing the relationship between the applied voltage and current between the node NL and the ground line VSS when one stage of ESD protection elements is connected. F_m is a curve showing the relationship between applied voltage and current between the node NM and the ground line VSS when two stages of ESD protection elements are connected, that is, F_h is a case where three stages of ESD protection elements are connected, ie, the node NH 5 is a curve showing a relationship between an applied voltage and a current between the ground line VSS and the ground line VSS.

  According to FIG. 4, it can be seen that the ESD protection element when connected in one stage has the lowest breakdown voltage (breakdown voltage), and the breakdown voltage increases as the number of connection stages increases. Further, when a breakdown occurs once and a surge current flows and then the voltage is increased again, it can be seen that flakedown occurs again when the breakdown voltage is reached. Thus, it can be seen that there is no situation where the ESD protection element itself is destroyed after the occurrence of the snapback phenomenon.

  In the above embodiment, the case where three different voltages are applied as the power supply voltage has been described as an example. However, the ESD protection element is realized by the same method in the case of two types or four or more types. be able to.

  FIG. 5 is a conceptual block diagram of the semiconductor device of the present invention in the case where a power supply terminal VCC_h for high voltage output and a power supply terminal VCC_l for low voltage output are provided. 6 is an example in which the block diagram shown in FIG. 5 is expressed by a circuit diagram, and FIG. 7 is a schematic cross-sectional structure diagram of the ESD protection device in the case shown in FIG. 5 to 7 are created in the same manner as FIGS. 1 to 3, and the same portions are denoted by the same reference numerals.

  Also in the semiconductor device 1a shown in FIG. 5, the low breakdown voltage protected element 18 is protected from ESD by the ESD protection element 13, and the high breakdown voltage protected element 16 is the ESD protection element 11 as in the semiconductor device 1 of FIG. , 12, 13 are protected from ESD by a series connection. The sustain voltage Vh1 between the node NH to which the high breakdown voltage protected element 16 is connected and the ground line VSS1, and the sustain voltage Vh3 between the node NL to which the low breakdown voltage protected element 18 is connected and the ground line VSS are related. Is obtained in the same manner as Equation 1 above. Therefore, it is possible to prevent an overcurrent from flowing from the power supply terminals (VCC_h, VCC_l) to which the power supply voltage is applied to the ESD protection element after the surge current is lost to the ground line VSS.

  Further, the breakdown voltage Vt1 between the node NH and the ground line VSS and the breakdown voltage Vt3 between the node NL and the ground line VSS are obtained in the same manner as the above formula 2. Therefore, even in such a configuration, it is not necessary to realize each ESD protection element as a high breakdown voltage element, so that the layout occupation area can be reduced.

  In the above embodiment, a ggNMOS transistor is used as an example of an ESD protection element. Instead, a bipolar transistor or a diode may be used, or a series circuit of these elements may be used. good.

  The ESD protection circuit 10b included in the semiconductor device 1b illustrated in FIG. 8 has a configuration including a resistor R1 in addition to the ggNMOS transistor TM between the nodes NM and NL. In this case, the ESD protection element 12 provided between the nodes NM and NL is realized by a series connection configuration of the ggNMOS transistor TM and the resistor R1. The direction in which the surge current flows when a surge voltage is applied and the mode of voltage change at that time are the same principles as described with reference to FIG. Therefore, in the configuration of FIG. 8, the withstand voltage Vt12 of the ESD protection element 12 is defined as the total value of the withstand voltage of the ggNMOS transistor TM and the voltage across the resistor R1. Similarly, the sustain voltage Vh12 of the ESD protection element 12 is also defined as a value obtained by adding the voltage across the resistor R1 to the sustain voltage of the ggNMOS transistor TM.

  Therefore, if the ESD protection circuit 10b shown in FIG. 8 has the same configuration as that of the ESD protection circuit 10 shown in FIG. 2 except for the resistor R1, the node NM and the ground line are provided by providing the resistor R1 in series. The breakdown voltage Vt2 between the VSS and the sustain voltage Vh2, and the breakdown voltage Vt1 between the node NH and the ground line VSS and the sustain voltage Vh1 can be further increased (see the above formulas 1 and 2).

  The ESD protection circuit 10c included in the semiconductor device 1c illustrated in FIG. 9 includes a diode D1 in addition to the ggNMOS transistor TM between the nodes NM and NL. In the case of this configuration, the withstand voltage Vt12 of the ESD protection element 12 is defined as a total value of the withstand voltage of the ggNMOS transistor TM and the withstand voltage of the diode D1. Similarly, the sustain voltage Vh12 of the ESD protection element 12 is also defined as a value obtained by adding the withstand voltage of the diode D1 to the sustain voltage of the ggNMOS transistor TM.

  The ESD protection circuit 10d included in the semiconductor device 1d illustrated in FIG. 10 includes a bipolar transistor T1 having a base and an emitter connected between the nodes NM and NL in addition to the ggNMOS transistor TM. In this configuration, the withstand voltage Vt12 of the ESD protection element 12 is defined as the total value of the withstand voltage of the ggNMOS transistor TM and the withstand voltage of the bipolar transistor T1. Similarly, the sustain voltage Vh12 of the ESD protection element 12 is defined as a value obtained by adding the sustain voltage of the bipolar transistor T1 to the sustain voltage of the ggNMOS transistor TM.

  The ESD protection circuit 10e included in the semiconductor device 1e illustrated in FIG. 11 has a configuration including a diode as the ESD protection elements 11-13. About the diode comprised between each power supply and GND, it is realizable with the diode formed between the low concentration N type diffused layer of an ESD protection element, and a P-type semiconductor substrate.

  In this case, the withstand voltage Vt1 between the node NH and the ground line VSS is the sum of the junction withstand voltages of the diodes D1 to D3 provided between the nodes NH and NM, between the nodes NM and NL, and between the node NL and the ground line VSS. Defined as a value. Further, the withstand voltage Vt2 between the node NM and the ground line VSS is defined as the total value of the junction withstand voltages of the diodes D2 and D3, and the withstand voltage Vt3 between the node NL and the ground line VSS is defined as the junction withstand voltage of the diode D3.

  When a positive surge voltage is applied to the high voltage power supply VCC_h with reference to the ground line VSS, the ground line passes through the ESD protection element 11 (diode D1), the ESD protection element 12 (diode D2), and the ESD protection element 13 (diode D3). Surge current is lost to VSS. Similarly, when a positive surge voltage is applied to the intermediate voltage power supply VCC_m, a surge current is released to the ground line VSS via the diodes D2 and D3.

  The ESD protection circuit 10f included in the semiconductor device 1f illustrated in FIG. 12 has a configuration including bipolar transistors in which a base and an emitter are connected as the ESD protection elements 11-13.

  In this case, the withstand voltage Vt1 between the node NH and the ground line VSS is the sum of the withstand voltages of the bipolar transistors B1 to B3 provided between the nodes NH and NM, between the nodes NM and NL, and between the node NL and the ground line VSS. Defined as a value. Further, the withstand voltage Vt2 between the node NM and the ground line VSS is defined as the total value of the withstand voltages of the bipolar transistors B2 and B3, and the withstand voltage Vt3 between the node NL and the ground line VSS is defined as the junction withstand voltage of the bipolar transistor B3. .

  When the surge voltage Vsur_h is applied from the high-voltage power supply terminal VCC_h, the ESD protection element 11 (bipolar transistor B1), the ESD protection element 12 (bipolar transistor B2), and the ESD protection element 13 (bipolar transistor B3) pass in this order. A surge current flows to the ground line VSS. Sustain voltage Vh1 between node NH and ground line VSS after the surge current flows is defined by the sum of sustain voltage Vh11 of bipolar transistor B1, sustain voltage Vh12 of bipolar transistor B2, and sustain voltage Vh13 of bipolar transistor B3. .

  Similarly, when the surge voltage Vsur_m is applied from the intermediate voltage power supply terminal VCC_m, the surge current flows to the ground line VSS through the bipolar transistors B2 and B3 in turn, and the subsequent sustain voltage Vh2 is equal to the bipolar transistor B2 Of the sustain voltage Vh12 and the sustain voltage Vh13 of the bipolar transistor B3.

  Further, when the surge voltage Vsur_l is applied from the low voltage power supply terminal VCC_l, the surge current flows through the bipolar transistor B3 to the ground line VSS, and the subsequent sustain voltage Vh3 is the sustain voltage Vh13 of the bipolar transistor B3. It is prescribed by.

  8 to 10, the ESD protection element 12 connected between the nodes NL and NM is configured to be connected in series with a ggNMOS transistor and another element. However, this is only an example. For example, the ESD protection element 11 and 13 may be configured as such.

  In each of the above embodiments, a ggPMOS transistor can be employed instead of the ggNMOS transistor.

  As described above, according to the present invention, an ESD protection element is not provided between each power supply terminal and the ground line VSS, but is provided between power supply terminals that supply different voltages. Therefore, the area of each ESD protection element can be reduced.

1, 1a, 1b, 1c, 1d, 1e, 1f: Semiconductor device of the present invention 10, 10a, 10b, 10c, 10d, 10e, 10f: ESD protection circuit of the present invention 11, 12, 13: ESD protection element 16: High breakdown voltage protected element 17: Intermediate breakdown voltage protected element 18: Low breakdown voltage protected element 21: Semiconductor substrate 22, 42: Deep N well 23, 43, 53: N well 24, 44, 54: P well 25 45, 55: Source 26, 46, 56: Contact 27, 47, 57: Drain 28: Gate oxide film 29: Gate electrode 31: Field oxide film B1, B2, B3: Bipolar transistors NH, NM, NL: Node TH , TM, TL: ggNMOS transistors D1, D2, D3, DH, DM: Diodes VCC_h, VCC_m, VC C_l: Power supply terminal VSS: Ground wire

Claims (8)

An ESD protection circuit provided in a semiconductor device having a plurality of power supply terminals of different power supply voltages,
A first ESD protection element having one end connected to a first node connected to the first power supply terminal and the other end connected to a ground line and electrically separated from the semiconductor substrate;
One end is connected to a second node connected to a second power supply terminal having a higher voltage than the first power supply terminal, and the other end is connected to the first node, and a second ESD protection element electrically isolated from the semiconductor substrate An ESD protection circuit comprising: The plurality of power supply terminals are connected to different nodes, respectively.
Between a set of nodes whose voltage values of the connected power supply terminals differ by one step, one end is connected to the high voltage side node and the other end is connected to the low voltage side node. An ESD protection element separated into
The ESD protection circuit according to claim 1, wherein the ESD protection element is provided between each set of nodes having a voltage value different by one level.   3. The ESD protection circuit according to claim 1, wherein the ESD protection element is a semiconductor circuit that performs a snapback operation, a diode, or a series circuit including a plurality of one or both of them.   4. The ESD protection circuit according to claim 3, wherein at least one of the ESD protection elements is a gate grounded MOS (ggMOS) transistor that performs a snapback operation.   4. The ESD protection circuit according to claim 3, wherein at least one of the ESD protection elements is a bipolar transistor that performs a snapback operation.   The ESD protection circuit according to claim 3, wherein at least one of the ESD protection elements is a diode element. An ESD protection circuit according to claim 1;
A first protected element having one end connected to the first node and the other end connected to the ground line;
A second protected element having one end connected to the second node and the other end connected to the ground line,
The semiconductor device, wherein the second protected element is a higher breakdown voltage element than the first protected element. An ESD protection circuit according to claim 2;
A protected element having a different breakdown voltage is provided between each node and the ground line,
The semiconductor device, wherein the protected element is a high-breakdown-voltage element as the output voltage from the power supply terminal connected to the node connected to the protected element is higher.

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