JP2014154870A - Lsi esd protection circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being downsized by an ESD protection circuit in which the number of elements is reduced or elements are configured in WCSP rewiring.SOLUTION: An LSI EDS protection circuit comprises: an external terminal (solder bump BMP); a first rewiring part MRD01 connected to the external terminal; a plurality of second rewiring parts MRD12 and MRD13 connected to a protected circuit (LSI or the like); and a protection element (MOS transistor) which protects the protected circuit from electrostatic breakdown. The first rewiring part is connected to the second rewiring part via the protection element.

Description

  The present invention relates to an LSI ESD protection circuit and a semiconductor device, and more particularly to a semiconductor device that can be reduced in size by an ESD protection circuit in which the number of elements is reduced or an element is configured for rewiring of WCSP.

  Electrostatic discharge (hereinafter referred to as ESD) is a phenomenon that damages semiconductor devices and semiconductor integrated circuits (hereinafter referred to as LSI). ESD with respect to semiconductor devices and LSIs often occurs when an electrostatically charged conductor or a person approaches or contacts an external terminal of the semiconductor device, and a current caused by ESD flows inside the LSI. This causes fluctuations in transistor characteristics and wiring breakdown.

  In order to protect the semiconductor device from such an ESD current, a protection circuit (hereinafter referred to as an ESD protection circuit) is used in the semiconductor device (for example, Patent Document 1).

Japanese Patent Laid-Open No. 11-68038

  Conventionally, when one external terminal composed of solder bumps is connected to a plurality of transistors in an LSI (hereinafter referred to as a protected circuit) via wiring, the current caused by ESD is which protected It is necessary to provide an ESD protection circuit for each circuit to be protected so as to avoid destruction even when the circuit is reached.

  Therefore, in a WCSP type semiconductor device in which a plurality of ESD protection circuits composed of a relatively large area MOS transistor or the like are installed and the size of the LSI is the size of the semiconductor device as it is, there is a problem that the semiconductor device becomes large there were.

  An object of the present invention is to provide a semiconductor device that can be reduced in size by an ESD protection circuit in which the number of elements is reduced or the elements are configured for WCSP rewiring.

 According to one aspect of the present invention for achieving the above object, an external terminal, a first rewiring unit connected to the external terminal, and a plurality of second rewiring units connected to a protected circuit And an ESD protection circuit for an LSI connected to the second rewiring unit via the protective element, the protective element protecting the protected circuit from electrostatic breakdown. Is provided.

  According to another aspect of the present invention, there is provided a semiconductor device including the above-described LSI ESD protection circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can reduce in size by the ESD protection circuit which reduced the number of elements or comprised the element in the rewiring of WCSP can be provided.

The top view which shows the surface of the side in which the solder bump was formed of the semiconductor device of a WCSP (wafer level chip size package) type | mold. FIG. 2 is a cross-sectional view taken along line II of the WCSP type semiconductor device shown in FIG. 1. The partial perspective view which shows the surface by which the solder bump was formed of the WCSP type semiconductor device which concerns on a comparative example. The schematic circuit diagram which shows the ESD protection circuit which concerns on a comparative example. 1 is a schematic circuit diagram showing an ESD protection circuit in a WCSP type semiconductor device according to a first embodiment. FIG. FIG. 6 is a plan view showing the process from BMP _G through the LSI protection element to connection to the rewiring again according to the first embodiment. II-II sectional view taken on the line of the ESD protection circuit shown in FIG. (A) Protection circuit diagram using NMOS transistor in ESD protection circuit according to first embodiment, (b) Protection circuit diagram using CMOS transistor, (c) Protection circuit diagram using diode. FIG. 3 is an overview showing a surface on which a solder bump BMP of a WCSP type semiconductor device is formed. It is an example of formation of the ESD protection circuit which has a high frequency filter concerning a 2nd embodiment, and is (a) a typical block diagram and (b) an explanatory view showing current direction. FIG. 7 is an overview showing a surface on which solder bumps BMP are formed of a WCSP type semiconductor device according to a second embodiment. The circuit diagram which shows the concept of a filter circuit. The typical block diagram which shows the other structural example of the ESD protection circuit which concerns on 4th Embodiment. FIG. 10 is a schematic configuration diagram illustrating an example of a configuration in which an ESD protection circuit according to a fifth embodiment has branched wiring; It is an ESD protection circuit which concerns on 5th Embodiment, Comprising: The typical block diagram which shows the structural example which provided the protection element while branching wiring. The top view which shows the example of formation of the ESD protection circuit in the QFN package type semiconductor device which concerns on 5th Embodiment.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

  In the present embodiment, a semiconductor integrated circuit formed on a silicon wafer is referred to as LSI (Large Scale Integration), and is expressed as a package encapsulated form (WCSP (WL-CSP (Wafer Level-Chip Size Package)). Others) may be referred to as a semiconductor device.

(Basic structure of WCSP type semiconductor device)
A basic structure of a WCSP type semiconductor device 200 according to the present invention will be described with reference to FIGS.

  The WCSP type semiconductor device 200 performs terminal formation and wiring (to be distinguished from LSI wiring, hereinafter referred to as rewiring) before cutting out each LSI from a silicon wafer on which a large number of LSIs are mounted. Then, the semiconductor device cut out from the wafer.

  The biggest reason for using the WCSP type is minimizing the external size of the semiconductor device (in addition, making it thinner, lighter, high degree of freedom in LSI terminal placement, etc.). It has the feature that it becomes the external size of the apparatus.

  FIG. 1 is a plan view showing a surface of a WCSP type semiconductor device 200 on which a solder bump BMP is formed, and FIG. 2 is a cross-sectional view taken along the line I-I.

  As shown in FIG. 1, the WCSP type semiconductor device 200 has a substantially rectangular shape in plan view, and a plurality of solder bumps BMP are provided at predetermined intervals as external terminals.

  As shown in FIG. 2, the WCSP type semiconductor device 200 includes an LSI 10 and a package unit 100 formed on the surface of the LSI 10.

  The package part 100 includes an interlayer film 12, a rewiring part MRD formed on the interlayer film 12, a solder bump BMP, and a post electrode made of a metal layer connecting the rewiring part MRD and the solder bump BMP. MP is provided.

  Further, a protective layer 14 made of epoxy resin or the like is provided so as to cover the rewiring portion MRD and the post electrode MP.

(Comparative example)
Here, before describing the ESD protection circuit 300 according to the present embodiment, an ESD protection circuit 300A according to a comparative example will be described.

  FIG. 3 is a partial perspective view showing a surface of the WCSP type semiconductor device 200A according to the comparative example on the side where the solder bumps BMP are formed, and FIG. 4 is a schematic circuit diagram showing the ESD protection circuit 300A according to the comparative example. It is.

In FIG. 3, a solder bump BMP _G is an electrode having a GND potential connected to the GND terminal of the LSI 10. If the LSI 10 has three GND terminals, the MRD ₀₁ , MRD ₀₂ , MRD ₀₃ and the contact holes CH ₀₁ , It is connected to the GND terminals GND ₀₁ , GND ₀₂ , and GND ₀₃ of the LSI 10 via CH ₀₂ and CH ₀₃ .

More specifically, as shown in FIG. 4, the GND terminals GND ₀₁ , GND ₀₂ , and GND ₀₃ of the LSI 10 through the contact holes CH ₀₁ , CH ₀₂ , and CH ₀₃ are connected to the wirings GWL ₀₁ , GWL ₀₂ , and GWL of the LSI 10. ₀₃ is connected, and protective elements PRT ₀₁ , PRT ₀₂ , PRT ₀₃ are connected to the wirings, respectively.

Further, the wirings GWL ₀₁ , GWL ₀₂ , GWL ₀₃ of the LSI 10 are connected to the protected circuit after passing through the protection elements PRT ₀₁ , PRT ₀₂ , PRT ₀₃ .

  The protection element in FIG. 4 is represented by an NMOS transistor, but other types of protection elements may of course be used.

3 and 4, the GND terminals GND ₀₁ , GND ₀₂ , and GND ₀₃ of the LSI 10 are expressed as CH ₀₁ (GND ₀₁ ) because they overlap with the contact holes.

According to the comparative example, when the current due to ESD enters from the solder bump BMP _G , each protection element PRT ₀₁ , PRT ₀₂ , PRT ₀₃ responds to breakdown or diode, and the current due to ESD does not reach the protected circuit. Therefore, it is possible to prevent the characteristic variation and destruction of the protected circuit.

(Problems of the comparative example)
However, as described above, in the ESD protection circuit 300A according to the comparative example, it is necessary to provide the protection elements PRT ₀₁ , PRT ₀₂ , and PRT ₀₃ in each of the wirings GWL ₀₁ , GWL ₀₂ , and GWL ₀₃ of the LSI 10, and the large area As a result of arranging a plurality of protective elements, the external size of the LSI is increased, that is, the semiconductor device 200A is increased in size.

[First Embodiment]
The ESD protection circuit 300 according to the first embodiment will be described with reference to FIGS.

  FIG. 5 is a schematic circuit diagram showing the ESD protection circuit 300 according to the first embodiment.

The first embodiment is connected with the solder bumps BMP _G as external terminals, the first redistribution unit MRD01 connected to BMP _G through the post electrodes MP, the _{MRD 01} via the contact hole _{CH 01} LSI wiring GWL ₀₁ and protective element PRT ₀₁ connected to GWL ₀₁ , and GWL ₀₁ is also connected to a separately provided contact hole CH ₁₁ . The contact hole _{CH 11} is connected to the second and third rewiring portion _MRD 12, _{MRD 13,} respectively, connected through a contact hole CH02 LSI wiring GWL02, the LSI wiring _{GWL 03} via the contact hole _{CH 03} Has been.

In this embodiment, when current due to ESD enters the solder bump BMP _G , PRT ₀₁ responds to breakdown or diode, and the protected circuit connected to GWL ₀₂ and GWL ₀₃ located after PRT ₀₁ is protected by ESD. Since the current does not reach, it is possible to prevent the characteristic fluctuation or destruction of the protected circuit.

More specifically, when the solder bump BMP _G is connected to the plurality of terminals only by the rewiring MRD, the current due to the ESD reaches almost all of the plurality of terminals at the same time. In the present embodiment, the contact hole, LSI Through the wiring, the contact hole again, and the rewiring again, the impedance is increased and the path through which the current flowing through the skin of the rewiring enters other terminals at high speed is blocked.

Then, according to the first embodiment, as compared with ESD protection circuit according to the comparative example, the protective element PRT _02, it is possible to reduce the PRT _03, with less area to form a protection element, a semiconductor This can contribute to downsizing of the apparatus 200.

FIG. 6 is a plan view showing the process from BMP _G through the LSI protection element to connection to the rewiring again according to the first embodiment, and FIG. 7 is a cross-sectional view taken along the line II-II in FIG. FIG.

As shown in FIGS. 6 and 7, the solder bumps BMP _G as an external terminal is connected to the first redistribution unit _{MRD 01} via the post electrodes MP, the first redistribution unit _{MRD 01} is a contact hole _{CH 01} via is connected to the terminal _{GND 01} of the LSI, top metal TOP in LSI (M2), the electrode TH, metal layer M3, the source region 16 of the protection element _{PRT 01} formed on the substrate 10A via the electrode 2C and the like ( S).

On the other hand, the second and third redistribution parts MRD ₁₂ and MRD ₁₃ are connected to the terminal GND ₁₁ of the LSI through the contact hole CH11 and formed on the substrate 10A through the electrodes TH, 2C, etc. in the LSI. It is connected to the source region 16 (S) of the protection element PRT ₀₁ .

Further, the drain region 18 (D) of the protection element PRT ₀₁ is connected to the wiring having the VDD potential through the electrode 2C and the like.

  With the configuration described above, the ESD protection circuit 300 according to the first embodiment can be realized.

  In the description of the ESD protection circuit 300 according to the first embodiment, since GND has been described as an example, the protection element has been described using an NMOS transistor as in the schematic circuit 300A of FIG. In the case of a signal line, a CMOS circuit 300B shown in FIG. 8B or a circuit 300C using a diode or the like shown in FIG. These protection circuits play a similar role in the sense of preventing current from entering the protected circuit due to ESD.

[Second Embodiment]
With reference to FIG. 9 and FIG. 10, an ESD protection circuit 300D having the high-frequency filter 301 according to the second embodiment will be described.

  FIG. 9 is a schematic view showing a surface on which the solder bump BMP of the WCSP type semiconductor device 200 is formed. The inductor component due to the meandering of the rewiring MRD constitutes the high frequency filter 301.

  10A and 10B are explanatory diagrams of the present embodiment in more detail. FIG. 10A is a configuration diagram, and FIG. 10B is an explanatory diagram showing a magnetic flux direction. The protection element connected to the LSI wiring described in the first embodiment is not shown in the description of this embodiment.

In FIG. 10 (a), the contact hole CH _31, in particular connected the protected circuit to be protected from the high-frequency noise.

The operation of the high frequency filter 301 will be described in more detail with reference to FIG. When a high-frequency current I flows through the meandering rewiring portion MRD ₂₁ constituting the high-frequency filter 301, the portion surrounded by the U-shape at the left end of FIG. When a magnetic flux is generated and the generated magnetic flux penetrates the adjacent U shape as indicated by an arrow, an induced current I _{INDUCE is} generated in the direction to cancel the magnetic field, but I _INDUCE is in the opposite direction to the flowing current I Current flows through each other, causing the currents to cancel each other.

 By such an operation and effect as the high-frequency filter 301, it is possible to prevent high-frequency noise including ESD from reaching the protected circuit, and to prevent characteristic variation and destruction of the protected circuit.

  According to the second embodiment, since the high frequency filter 301 is provided in the rewiring section, the protected circuit can be protected from high frequency noise including ESD without increasing the area of the semiconductor device.

[Third Embodiment]
With reference to FIGS. 11 and 12, an ESD protection circuit 300E having an RC low-pass filter 302 according to the third embodiment will be described.

  FIG. 11 is a schematic view showing a surface of the WCSP type semiconductor device 200 on which the solder bumps BMP are formed. The resistance and the capacitance due to the routing of the rewiring MRD constitute the low-pass filter 302.

  FIG. 12 is a circuit diagram showing the concept of the filter circuit, and shows resistance and capacitance.

  The configuration according to the third embodiment is obtained by replacing the high-frequency filter 301 according to the second embodiment with a low-pass filter 302.

  In the example shown in FIG. 11, the redistribution part MRD constituting the filter extends along the periphery of the LSI 10.

Thereby, even if noise including ESD enters through the solder bumps BMP _G , the protected circuit such as an LSI connected to the solder bumps BMP _i by the filter 302 constituted by the rewiring unit MRD. Can be protected.

[Fourth Embodiment]
The ESD protection circuits 300F to 300H according to the fourth embodiment will be described with reference to FIGS.

  FIG. 13 is a schematic configuration diagram showing another configuration example of the ESD protection circuit according to the present embodiment.

In this configuration example, the first redistribution MRD01 connected to the solder bumps BMP _G is connected to the contact hole _{CH 02} via the contact hole _{CH 01} and top metal TOP.

Further, a MOS transistor is formed as a protection element PRT between the contact holes CH ₀₁ and CH ₀₂ .

Further, second redistribution lines MRD ₀₂ and MRD ₀₃ constituting a filter are extended through contact holes CH ₀₂ and CH ₀₃ . Rewiring _{MRD 03} is connected to the protected circuit such as an LSI (not shown) through a contact hole CH _4.

Similarly, a protected circuit such as an LSI is connected through the contact holes CH ₀₂ and CH ₀₃ .

According to the ESD protection circuit 300F having such a configuration, for example, when a surge current or the like enters through the solder bump BMP _G , the surge current is re-wired MRD ₀₂ and MRD ₀₃ by the action of the protection element PRT. It is possible to avoid a situation in which various integrated circuits (LSIs) as protected circuits are destroyed by a surge current without flowing into the side.

Further, even when noise including ESD enters through the solder bumps BMP _G , the noise is cut by the low-pass filter 303 constituted by the rewirings MRD _{01 to} MRD ₀₃ , and the contact holes CH ₀₃ and It is possible to protect a protected circuit such as an LSI connected via the CH ₀₄ .

  FIG. 14 is a schematic configuration diagram illustrating a configuration example of the ESD protection circuit 300 </ b> G according to the present embodiment, in which wirings are branched.

The ESD protection circuit 300G shown in FIG. 14, the rewiring _{MRD 01} is connected to the solder bumps BMP _G is connected to the contact hole CH02 via the contact hole _{CH 01} and top metal TOP.

Further, a MOS transistor is formed as a protection element PRT between the contact holes CH ₀₁ and CH ₀₂ .

Redistribution lines MRD ₀₃ , MRD ₀₇ , and MRD ₀₈ are branched and extended with the contact hole CH ₀₂ as a branch point. Note that various integrated circuits (LSIs) serving as protected circuits are connected to the contact holes CH ₀₇ , CH ₀₈ , and CH ₀₃ of each connection destination.

Further, the contact holes _{CH 03} rewiring _{MRD 03} is connected rewiring MRD04 is extended, the contact holes _{CH 04} of the destination as a branch point, redistribution _MRD 05, _{MRD 06} is extended branches ing. Note that various integrated circuits (LSIs) serving as protected circuits are connected to the contact holes CH ₀₃ , CH ₀₄ , CH ₀₅ , and CH ₀₆ at each connection destination.

According to the ESD protection circuit 300G having such a configuration, various integrated circuits as protected circuits connected to the redistribution lines MRD _{03 to} MRD ₀₆ branched downstream from the protection element PRT by the action of one protection element PRT. All of the circuit (LSI) can be protected from surge current or the like.

That is, for example, when a surge current enters through the solder bump BMP _G , the surge current does not flow into any of the redistribution lines MRD _{03 to} MRD ₀₆ due to the action of the protection element (MOS transistor) PRT. Thus, it is possible to avoid a situation in which various integrated circuits (LSIs) as protected circuits are destroyed by a surge current.

As described above, since a plurality of protected circuits (LSIs) can be protected by one protection element PRT, it is not necessary to separately provide protection elements on the redistribution lines MRD _{03 to} MRD ₀₆ side, and the protection elements are formed. The semiconductor device can be reduced in size by reducing the area.

  FIG. 15 is a schematic configuration diagram showing an example of a configuration of the ESD protection circuit 300H according to the present embodiment, in which a wiring is branched and a protection element is provided.

The ESD protection circuit 300H shown in FIG. 15, a plurality of wiring portions _MRD 02 _{~MRD 04} is adapted to be connected via the protective element PTS1, PTS2, PTL1 corresponding to the breakdown voltage of the protected circuit (LSI) .

More specifically, as shown in FIG. 15, the wiring portion _MRD 01 _{~MRD 03} which is connected to the solder bumps BMP _G protection element PTS1, PTS2, PTL1 and the contact holes _CH 01 the protected circuit through _{to CH 03} ( LSI).

Then, the protective element PTS1, PTS2, PTL1 is a contact hole _CH 01 _{to CH} protected _{circuit 03} are connected through the size of the MOS transistor according to the breakdown voltage of the (LSI) or the like.

  That is, in the example shown in FIG. 15, the protection elements PTS1 and PTS2 are MOS transistors or the like that are smaller than the protection element PTL1, and a protection circuit (LSI) having a relatively high breakdown voltage is provided on the protection elements PTS1 and PTS2 side. A protected circuit (LSI) having a relatively low breakdown voltage is connected to the protective element PTL1 side.

  As a result, it is not necessary to provide a uselessly large protective element (such as a MOS transistor), and the semiconductor device can be reduced in size.

Further, the first redistribution unit _{MRD 04} which is connected to the solder bumps BMP _G is connected to the contact hole _{CH 04} via the relatively large protective element (MOS transistor) PTL2.

The protection element (MOS transistor) PTL2 is connected to the contact hole _{CH 05,} the contact holes _{CH 05} is the second redistribution unit _MRD 05 _{~MRD 07} as a branching point is extended branches.

Transistors TL3, TL4, and TS3 are connected to the second redistribution parts MRD _{05 to} MRD ₀₇ as protected elements. Here, the breakdown voltage of the transistor TS3 as the protected element is lower than those of the transistors TL3 and TL4.

  The size of the protection element (MOS transistor) PTL2 corresponds to the withstand voltage of the transistor TS3 as a protected element.

  This eliminates the need for the protective element (MOS transistor) PTL2 to be a uselessly large protective element (MOS transistor or the like), thereby reducing the size of the semiconductor device.

In FIGS. 13 to 15 described above, the high frequency filter described in the second embodiment can be applied to any redistribution portion of MRD _{01 to} MRD ₀₈ .

[Fifth Embodiment]
With reference to FIG. 16, an ESD protection circuit 300I in the QFN package type semiconductor device 200B according to the fifth embodiment will be described.

 Note that QFN = quad flat no lead is a type of QFP = quad flat package, and is characterized by lead wire omission (No-Lead).

  FIG. 16 is a plan view showing a formation example of the ESD protection circuit 300I in the QFN package type semiconductor device 200B according to the present embodiment.

  First, the QFN package type semiconductor device 200B is a kind of QFP = quad flat package, which is a resin-sealed package in which leads are omitted and an electrode pad is formed, and an LSI enclosed in the package. is there. Since the leads are omitted, the mounting area can be reduced and the weight can be reduced.

  As shown in FIG. 16, the QFN package type semiconductor device 200 </ b> B according to the present embodiment includes an LSI 51 and a resin package 100 that surrounds and seals the LSI 51. The external terminal PL is formed, the external terminal PL51 and the terminal TE51 of the LSI 51 are connected by a bonding wire WL51 such as an Au wire, and the protective element PRT51 is connected to the terminal TE51.

  In addition, the terminal TE52 is also connected to the PRT 51, and the terminals TE52, TE53, and TE54 are connected by a bonding wire WL53 and a bonding wire WL54, respectively.

  Further, a protected circuit is connected to each of the terminals TE52, TE53, and TE54.

  In this embodiment, when a current due to ESD enters the external terminal PL51, the protective element PRT51 responds to breakdown or diode, and the protected circuit connected to the terminals TE53 and TE54 located downstream from the protective element PRT51 is protected by ESD. Since the current does not reach, it is possible to prevent the characteristic fluctuation or destruction of the protected circuit.

  According to the fifth embodiment, since it is not necessary to separately provide a protective element for the terminals TE53 and TE54, the area for forming the protective element can be reduced and the LSI can be miniaturized.

  Further, according to the fifth embodiment, the number of external terminals of the LSI can be reduced.

[Other embodiments]
As described above, the embodiments have been described. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are illustrative and do not limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments not described herein.

  The ESD protection circuit of the present invention can be applied to a WCSP type semiconductor device, a QNF package type semiconductor device, or the like.

BMP, BMP _G , BMP _i ... Solder bumps M1 to M3 ... Metal layer MP ... Post electrode MRD ₀₁ ... First rewiring (rewiring portion)
MRD _{02 to} MRD ₁₃ ... Second rewiring (rewiring portion)
PL ... external terminal PRT, PTL1,2, PTS1,2 ... protection element TE51~53 ... terminal TOP ... Top metal CH ₀₁ ~CH _{31 ...} contact hole _{GND 01 ~GND 03, GND 11 ...} GND terminal GWL ₀₁ ~GWL ₀₃ ... Wiring WL51-WL53 ... Bonding wire 10 ... LSI
DESCRIPTION OF SYMBOLS 10A ... Board | substrate 12 ... Interlayer film 14 ... Protective layer 2C, TH ... Electrode 16 (S) ... Source region 18 (D) ... Drain region 24, 25 ... Columnar electrode 100 ... Package part 200, 200A, 200B ... Semiconductor device 300 ( 300A to 300I) ESD protection circuit 301 High frequency filter 302 Low pass filter

Claims (15)

An external terminal,
A first rewiring unit connected to the external terminal;
A plurality of second rewiring units connected to the protected circuit;
A protection element for protecting the protected circuit from electrostatic breakdown,
The LSI ESD protection circuit, wherein the first rewiring unit is connected to the second rewiring unit through the protection element.   2. The LSI ESD protection circuit according to claim 1, wherein the protection element is formed of a MOS transistor.   3. The LSI ESD protection circuit according to claim 1, wherein the external terminal is constituted by a solder bump.   4. The device according to claim 1, wherein the first rewiring unit and the plurality of second rewiring units are configured by wiring mounted on a wafer level chip size package. 5. 2. An LSI ESD protection circuit according to item 1.   4. The LSI ESD protection circuit according to claim 1, wherein the first redistribution unit and the plurality of second redistribution units are formed of bonding wires. 5.   6. The LSI ESD protection circuit according to claim 1, wherein the plurality of second redistribution parts are branched through a branch part. 7.   7. The LSI ESD protection circuit according to claim 1, wherein at least a part of the plurality of second redistribution units is configured by a high frequency filter. 8.   8. The LSI ESD protection circuit according to claim 7, wherein the high-frequency filter includes an inductor component formed by meandering the second rewiring portion.   9. The LSI ESD protection circuit according to claim 1, wherein at least a part of the plurality of second rewiring units is configured by a filter unit. 10.   10. The LSI ESD protection circuit according to claim 9, wherein the filter unit includes a resistance component and a capacitance component formed by extending the second rewiring unit in a predetermined shape. 11.   11. The LSI according to claim 1, wherein the plurality of second redistribution units are branched through another protection element corresponding to a withstand voltage of the protected circuit. ESD protection circuit.   The plurality of second redistribution parts are connected to the protected circuit via other protective elements corresponding to the withstand voltage of the protected circuit. 2. An ESD protection circuit for an LSI according to 1.   A semiconductor device comprising the LSI ESD protection circuit according to claim 1.   14. The semiconductor device according to claim 13, which is mounted on a wafer level chip size package.   The semiconductor device according to claim 13, wherein the semiconductor device is mounted in a quad-for-non-lead package.

Images