WO2011021411A1 - Esd protection device - Google Patents

Esd protection device Download PDF

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Publication number
WO2011021411A1
WO2011021411A1 PCT/JP2010/057859 JP2010057859W WO2011021411A1 WO 2011021411 A1 WO2011021411 A1 WO 2011021411A1 JP 2010057859 W JP2010057859 W JP 2010057859W WO 2011021411 A1 WO2011021411 A1 WO 2011021411A1
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Prior art keywords
esd protection
protection device
esd
conductive pattern
signal line
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PCT/JP2010/057859
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French (fr)
Japanese (ja)
Inventor
山田浩輔
野間隆嗣
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株式会社村田製作所
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Priority to TW099127412A priority Critical patent/TW201138052A/en
Publication of WO2011021411A1 publication Critical patent/WO2011021411A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0107—Non-linear filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/17—Structural details of sub-circuits of frequency selective networks
    • H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1766—Parallel LC in series path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • This invention relates to an electrostatic protection device (ESD protection device) for protecting a semiconductor IC or the like from static electricity.
  • ESD protection device electrostatic protection device
  • ESD Electro Static Discharge
  • Such an ESD protection device includes a ⁇ -type ESD protection circuit 10P ′ as shown in FIG. 12A and a T-type ESD protection circuit 10T ′ as shown in FIG.
  • FIG. 12 is an equivalent circuit diagram showing an example of a conventional ESD protection circuit.
  • FIGS. 12A and 12C are circuit diagrams of the respective ESD protection circuits.
  • FIGS. 12B and 12D are ESD diagrams. It is an equivalent circuit diagram in the state where an element is OFF.
  • 12A and 12B show a ⁇ -type ESD protection circuit
  • FIGS. 12C and 12D show a T-type ESD protection circuit.
  • the ⁇ -type ESD protection circuit 10P ′ shown in FIG. 12A includes a resistor R and two ESD elements ESD1 and ESD2.
  • the resistor R is inserted in a signal line between the input port Pi and the output port Po.
  • Each of the two ESD elements ESD1, ESD2 has one end connected to both ends of the resistor R and the other end connected to the ground.
  • This ⁇ -type ESD protection circuit is also described in Patent Document 1.
  • the T-type ESD protection circuit 10T ′ shown in FIG. 12C includes two resistors R connected in series and an ESD element ESD. Two resistors R connected in series are inserted in a signal line between the input port Pi and the output port Po.
  • the ESD element ESD has one end connected to the connection point of the two resistors R and the other end connected to the ground.
  • the ⁇ -type ESD protection circuit 10P ′ as shown in FIG. 12A and the T-type ESD protection circuit 10T ′ as shown in FIG. 12C function as the capacitor Cv when the ESD element is OFF.
  • the ⁇ -type ESD protection circuit 10P ′ shown in FIG. 12A functions as a CR-C type low pulse filter shown in FIG. 12B
  • the circuit 10T ′ functions as an RCR type low pulse filter shown in FIG.
  • such a low-pass filter including the ⁇ -type ESD protection circuit 10P ′ and the T-type ESD protection circuit 10T ′ has a characteristic that the amount of attenuation increases monotonously at the high band end of the pass band. Therefore, for example, when high-frequency noise exists at a frequency with a small attenuation at the high end of the pass band, the high-frequency noise cannot be attenuated.
  • An object of the present invention is to realize an ESD protection device that can reliably perform ESD protection while sufficiently securing an attenuation amount of a desired frequency.
  • An ESD protection device includes a resistor inserted in a signal line, two ESD elements for connecting both ends of the resistor and the ground, and a resistor connected in series on the signal line.
  • An LC parallel resonator is
  • a resistor and two ESD elements constitute a ⁇ -type ESD protection circuit having an ESD protection function and a low-pass filter function.
  • the attenuation pole at the time of functioning as a low-pass filter is formed by LC parallel resonator.
  • the resonance frequency of the LC parallel resonator is set to the frequency of the high frequency noise to be removed, an attenuation pole is formed at the frequency, and the high frequency noise is greatly attenuated.
  • the line capacitance does not change, so that there is almost no influence on the transmission characteristics other than the formation of the attenuation pole.
  • the LC parallel resonator of the ESD protection device of the present invention is connected between one end of the resistor in the signal line and the ESD element connected to the one end.
  • the LC parallel resonator is arranged in the middle of two connection points where the two ESD elements are respectively connected to the signal line. Thereby, even if static electricity is superimposed from any direction of the signal line, it is discharged to the ground by the ESD element, and static electricity is not surged to the LC parallel resonator. Thereby, destruction of the capacitor of the LC parallel resonator can be prevented together with the normal ESD protection function.
  • the inductor of the LC parallel resonator is formed with a spiral electrode described later, the resistance component of the inductor increases and current flows easily through the capacitor. Therefore, using this structure can prevent electrostatic breakdown of the capacitor. It is valid.
  • the ESD protection device of the present invention connects two resistors inserted in a signal line and connected in series with each other, and a connection point between the two resistors connected in series and the ground.
  • An ESD element, and an LC parallel resonator connected in series to a signal line between one of the resistors and the connection point.
  • a T-type ESD protection circuit having an ESD protection function and a low-pass filter function is configured by two resistors and an ESD element.
  • the attenuation pole at the time of functioning as a low-pass filter is formed by LC parallel resonator.
  • the resonance frequency of the LC parallel resonator is set to the frequency of the high frequency noise to be removed, an attenuation pole is formed at the frequency, and the high frequency noise is greatly attenuated.
  • the line capacitance does not change, so that there is almost no influence on the transmission characteristics other than the formation of the attenuation pole.
  • the inductor constituting the LC parallel resonator of the ESD protection device of the present invention comprises a conductive pattern formed on a silicon substrate on which a signal line is formed.
  • This configuration shows a specific method for forming an inductor of an LC parallel resonator, and can be formed integrally with a signal line by being formed on a silicon substrate. Further, by using the silicon substrate, it is possible to collectively form the capacitor of the LC parallel resonance circuit, the resistor R and the ESD element of the ESD protection device.
  • the inductor of the ESD protection device includes a conductive pattern of a redistribution layer separated from a conductive pattern of a silicon substrate, a conductive pattern on the redistribution layer, and a silicon substrate. And a via hole that conducts the conductive pattern.
  • the inductor is formed of the conductive pattern on the surface of the silicon substrate and the conductive pattern of the rewiring layer formed at a position spaced apart from the conductive pattern on the surface of the silicon substrate. And since these are electrically connected by a via hole, an inductor is formed by the electrode over a plurality of layers. As a result, it is possible to make the electrode length of the inductor longer than that of the single layer structure, and a high inductance can be realized. As a result, the Q value of the LC parallel resonator can be increased, and a steeper attenuation pole can be realized.
  • the inductor of the ESD protection device of the present invention further includes a conductive pattern of at least one redistribution layer and a via hole that connects the conductive patterns of each redistribution layer.
  • a higher inductance can be realized by further increasing the conductive pattern of the rewiring layer and connecting the conductive pattern on the silicon substrate and the conductive pattern of each rewiring layer.
  • the Q value of the LC parallel resonator can be further increased, and a steeper attenuation pole can be realized.
  • the conductive pattern of the rewiring layer of the ESD protection device of the present invention has a thicker electrode than the conductive pattern on the silicon substrate.
  • the conductive pattern of the rewiring layer of the ESD protection device of the present invention is formed of a material having higher conductivity than the conductive pattern on the silicon substrate.
  • the conductive pattern of the rewiring layer is used to increase the inductance of the inductor by increasing the electrode length of the inductor, but the rewiring layer has a high conductivity to further suppress an increase in resistance value. Can do. Thereby, the Q value of the LC parallel resonator can be made steeper, and a steeper attenuation pole can be realized.
  • the conductive pattern on the silicon substrate of the ESD protection device of the present invention comprises a spiral electrode.
  • This configuration shows a case where a spiral electrode is used as an example of a conductive pattern inductor formation pattern.
  • the inductance can be made higher than that of the meander electrode having the same area.
  • the Q value of the LC parallel resonator can be increased, and a steeper attenuation pole can be realized.
  • the conductive pattern on the silicon substrate of the ESD protection device of the present invention and the conductive pattern of the redistribution layer have substantially the same shape and the same direction in the same region in a plan view of the silicon substrate. It consists of a spiral electrode wound around.
  • the ESD protection device of the present invention further includes a capacitor having one end connected to the signal line between the resistor and the LC parallel resonator and the other end connected to the ground.
  • the ESD protection device is composed of a plurality of resonance circuits, it is possible to make the attenuation pole have a steeper characteristic.
  • the capacitor includes a third ESD element different from the two ESD elements.
  • This configuration shows a specific example of capacitor formation.
  • the resistor includes two partial resistors, and the two partial resistors are respectively connected to the two ESD elements from one end of the third ESD element. Individually connected on the signal line.
  • the ESD that flows into the third ESD element can be lowered by the partial resistor, and the destruction of the third ESD element can be prevented.
  • the capacitor is separated from the conductive pattern formed on the silicon substrate on which the signal line is formed and the conductive pattern formed on the silicon substrate. And a conductive pattern of the rewiring layer.
  • This configuration shows a specific structure when the capacitor is not formed by an ESD element.
  • the conductive pattern formed on the silicon substrate forming the capacitor also serves as the conductive pattern constituting the inductor of the LC parallel resonator.
  • connection electrodes such as via holes for connecting the electrode pattern constituting the inductor of the LC parallel resonator on the Si substrate to the rewiring layer and the outside can be omitted, and the structure can be simplified.
  • an ESD protection device that forms an attenuation pole at the frequency of the high-frequency noise to be removed, can sufficiently attenuate the high-frequency noise, and can reliably perform ESD protection.
  • FIG. 4 is a circuit diagram of a ⁇ -type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. It is a passage characteristic figure of the ESD protection device concerning this embodiment, and the conventional ESD protection device.
  • FIG. 4 is a circuit diagram of a T-type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. It is side surface sectional drawing for demonstrating the structure of the ESD protection device of this embodiment. It is the external appearance perspective view which shows the structure of the inductor Lr typically, and its exploded perspective view.
  • FIG. 4 is a circuit diagram of a ⁇ -type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. It is a passage characteristic figure of the ESD protection device concerning this embodiment, and the conventional ESD protection device.
  • FIG. 4 is a circuit diagram of
  • FIG. 6 is a plan view and a side sectional view of the second spiral electrode 21B of the redistribution layer constituting the inductor Lr, and a plan view and a side sectional view of the first spiral electrode 21A formed on the surface of the Si substrate 20A.
  • It is a passage characteristic diagram which shows the influence on the passage characteristic according to the number of spiral electrodes.
  • It is a disassembled perspective view which shows typically the other structure of the inductor Lr.
  • It is the circuit diagram of the ESD protection device which consists of another structure of this invention, and an equivalent circuit diagram in the state where an ESD element is OFF.
  • It is a circuit diagram of the ESD protection device which consists of other composition of the present invention.
  • FIG. 6 is a circuit diagram of a conventional ESD protection circuit and an equivalent circuit diagram when an ESD element is in an OFF state.
  • FIG. 1A is a circuit diagram of the ⁇ -type ESD protection circuit 10P, and FIG. A circuit diagram is shown.
  • a resistor R is connected between a predetermined position of the signal line, that is, the input port Pi and the output port Po of the signal line in FIG.
  • One end of the resistor R is connected to one end of the ESD element ESD1, and the other end of the ESD element ESD1 is connected to the ground.
  • One end of the ESD element ESD2 is connected to the other end of the resistor R via the LC parallel resonant circuit 1, and the other end of the ESD element ESD2 is connected to the ground.
  • the LC parallel resonator 1 includes a parallel circuit of an inductor Lr and a capacitor Cr, and is connected in series with a resistor R on a signal line. At this time, the LC parallel resonant circuit 1 is connected so as to be inserted between the end of the resistor R on the ESD element ESD2 side and the connection point where the ESD element ESD2 is connected to the signal line.
  • the ⁇ -type ESD protection circuit 10P In the ⁇ -type ESD protection circuit 10P having such a circuit configuration, unless static electricity is superimposed on the signal line, the ESD elements ESD1 and ESD2 are turned off, and the ESD elements ESD1 and ESD2 each function as a capacitor Cv. Therefore, when the ESD elements ESD1 and ESD2 are in the OFF state, as shown in FIG. 1B, the ⁇ -type ESD protection circuit 10P includes the resistor R and the LC parallel resonant circuit 1 connected in series on the signal line. Both ends of the series circuit are connected to the ground by the capacitor Cv. As a result, the ⁇ -type ESD protection circuit 10P functions as a CR-LC-R type low-pass filter.
  • FIG. 2 shows the pass characteristics of the ⁇ -type ESD protection circuit 10P of this embodiment and the conventional ⁇ -type ESD protection circuit 10P ′ shown in FIG. 12, and the T-type ESD protection circuit 10T of this embodiment shown in FIG. It is a figure which shows the passage characteristic of the conventional T type ESD protection circuit 10T 'shown in FIG.
  • the conventional ⁇ -type ESD protection circuit 10P ′ functions as a C—R—C type low-pass filter, as shown by a thick broken line in FIG. Characteristic that the passing amount decreases).
  • the ⁇ -type ESD protection circuit 10P according to the present embodiment includes the LC parallel resonance circuit 1, and thus can provide an attenuation pole on the high band side of the pass band. Therefore, by setting the frequency of the attenuation pole to the desired high frequency noise frequency, the high frequency noise can be significantly attenuated. Then, the LC parallel resonant circuit 1 is connected in series to the signal line as in this embodiment, thereby forming the attenuation pole without changing the line capacitance, that is, the capacitance between the signal line and the ground. be able to. Thereby, generation
  • the ESD element ESD1 when static electricity is superimposed on the signal line from the input port Pi, the ESD element ESD1 first shifts to the ON state and is discharged through the ESD element ESD1.
  • the ESD element ESD2 when static electricity is superimposed on the signal line from the output port Po, the ESD element ESD2 first shifts to the ON state and is discharged through the ESD element ESD2.
  • the ⁇ -type ESD protection circuit 10P functions as an ESD protection circuit.
  • the LC parallel resonant circuit 1 is arranged between the connection points of the two ESD elements ESD1 and ESD2 to the signal line, so that static electricity from the input port Pi is also output to the output port. Since static electricity from Po is also discharged by the ESD elements ESD1 and ESD2, static electricity is not superimposed on the LC parallel resonant circuit 1. Therefore, the capacitor Cr of the LC parallel resonant circuit 1 can also be protected from static electricity.
  • the inductor Lr of the LC parallel resonant circuit 1 is formed of a spiral electrode, the electrode length becomes long to obtain a large inductance, and the resistance component of the inductor Lr increases. In this case, when static electricity is surged into the LC parallel resonant circuit 1, a large current flows through the capacitor, and the capacitor is easily destroyed. Therefore, the above-described configuration is more effective for the destruction of the capacitor when the spiral electrode is used.
  • the LC parallel resonant circuit 1 is not limited to the configuration in which the two ESD elements ESD1 and ESD2 are arranged between the connection points to the signal line, but on the input port Pi side from the ESD element ESD1 in the signal line or in the signal line. You may arrange
  • FIG. 3A is a circuit diagram of the T-type ESD protection circuit 10T
  • FIG. 3B is an equivalent circuit diagram of the ESD element ESD in the T-type ESD protection circuit 10T in an OFF state. Indicates.
  • two resistors R and the LC parallel resonance circuit 1 are connected in series between predetermined positions of the signal line, that is, between the input port Pi and the output port Po of the signal line.
  • the resistor R, the LC parallel resonant circuit 1, and the resistor R are connected in this order from the input port Pi side to the output port Po side.
  • the one end of the ESD element ESD is connected to the connection point between the resistor R on the input port Pi side and the LC resonance circuit 1, and the other end of the ESD element ESD is connected to the ground.
  • the T-type ESD protection circuit 10T In the T-type ESD protection circuit 10T having such a circuit configuration, unless static electricity is superimposed on the signal line, the ESD element ESD is turned off and functions as the capacitor Cv. Therefore, when the ESD element ESD is in the OFF state, as shown in FIG. 3B, the T-type ESD protection circuit 10T includes two resistors R and the LC parallel resonant circuit 1 connected in series on the signal line. A connection point between one resistor R of the series circuit and the LC parallel resonance circuit 1 is connected to the ground by a capacitor Cv. Thus, the T-type ESD protection circuit 10T functions as an RCLC-R-type low-pass filter.
  • the T-type ESD protection circuit 10T ′ functions as an RCR type low-pass filter, the attenuation increases monotonously on the high band side of the passband as shown by the thin broken line in FIG. Characteristic (characteristic that the passing amount decreases).
  • the T-type ESD protection circuit 10T according to the present embodiment includes the LC parallel resonance circuit 1, and thus can provide an attenuation pole on the high band side of the pass band. Therefore, similarly to the above-described ⁇ -type ESD protection circuit 10P, the high frequency noise can be greatly attenuated by setting the frequency of the attenuation pole to a desired frequency of the high frequency noise.
  • the LC parallel resonant circuit 1 is connected in series to the signal line as in this embodiment, thereby forming the attenuation pole without changing the line capacitance, that is, the capacitance between the signal line and the ground. be able to. Thereby, generation
  • the ESD element ESD changes to the ON state, and current flows from the signal line to the ground, so that the static electricity is discharged to the ground.
  • the T-type ESD protection circuit 10T functions as an ESD protection circuit.
  • connection relationship between the two resistors R, the ESD element ESD, and the LC parallel resonance circuit 1 shown in FIG. 3 is an example.
  • two resistors R are provided on the signal line.
  • the LC parallel resonance circuit 1 is further connected in series on the signal line, and the predetermined position between the two resistors R in the signal line is connected to the ground via the ESD element ESD. I just need it.
  • the ESD protection can be surely functioned and also function as a low-pass filter having an attenuation pole at a desired frequency. it can. That is, it is possible to realize an ESD protection device that allows a signal having a desired frequency to pass therethrough with low loss, reliably removes desired high-frequency noise, and performs ESD protection.
  • FIG. 4 is a side sectional view for explaining a schematic structure of the ESD protection device of the present embodiment.
  • FIG. 4 shows circuit portions of the ESD element ESD1, the resistor R, and the inductor Lr of the LC parallel resonance circuit of the ⁇ -type ESD protection circuit 10P described above.
  • the ESD protection device 10 of this embodiment is made of a so-called CSP (Chip Size Package) and includes a Si substrate 20A doped with p-type impurities.
  • a predetermined position of one surface (the lower surface in FIG. 4) of the p-type Si substrate 20 is n-type doped in a predetermined area range at a predetermined depth from the one surface.
  • a P well layer is formed so as to surround a specific pair of n type doping layer n + (two n type doping layers n + near the left end in FIG. 4) in the p type Si substrate 20A.
  • the P well layer is a layer in which the p-type impurity concentration is increased with respect to the Si substrate 20A.
  • the boundary between the p-type region (P well layer) and the n-type region can function as a diode or a capacitor, or the n-type region can function as a resistor.
  • the P well layer is not necessarily formed, but it is desirable to form it.
  • the contact layer 200 and the conductive pattern 201 are sequentially formed on the surface of the partially n-type doped p-type Si substrate 20A from the surface side.
  • the conductive pattern 201 is realized by vapor deposition of a metal material such as Al (aluminum).
  • the contact layer 200 and the conductive pattern 201 are patterned so as to realize a desired circuit configuration.
  • the contact layer 200 and the conductive pattern 201 in the region where the ESD element ESD1 is formed are patterned on the surfaces of two n-type doping layers n + formed at a predetermined interval. Thereby, in this region, it is possible to realize a circuit configuration in which two diodes are connected in series in a state in which the forward directions do not match, and the ESD element ESD1 is realized.
  • one pn junction is realized by one n-type doping layer n + and the P well, and another pn junction is realized by the other n-type doping layer n + and the P well. Is done.
  • the structure is equivalent to a circuit in which two diodes are connected so that the forward directions are opposite to each other. Therefore, a diode having a predetermined threshold voltage positive and negative can be realized, and can function as an ESD protection circuit.
  • the diode if the threshold voltage Vt is set higher than the voltage during normal operation, the diode is normally turned off (not turned on), and when static electricity exceeding the threshold voltage Vt is superimposed, the diode Becomes an ON state and functions as an ESD protection circuit that releases energy to the ground.
  • the contact layer 200 and the conductive pattern 201 in the region where the resistor R is formed are patterned in two predetermined area ranges on both ends of the n-type doping layer n +.
  • the resistor R using the resistance component of the n-type doping layer n + is realized.
  • the resistor R is realized by using the n-type doping layer n +, but the p-type doping layer p + surrounded by the N well is formed on the Si substrate 20A, and the p The resistor R may be formed of the type doping layer p +.
  • the contact layer 200 and the conductive pattern 201 in the region where the inductor Lr is formed are patterned in a spiral shape having a predetermined number of turns and a predetermined electrode width. Thereby, the first spiral electrode 21A formed on the Si substrate 20A is realized.
  • the surface of the contact layer 200, the conductive pattern 201, and the Si substrate 20A on which the pattern is not formed is covered with the insulating passivation layer 20Bp except for the region where the UBM 40 is formed. It has been broken. And UBM40 is formed in the position which this passivation layer 20Bp opened.
  • a rewiring layer made of a conductive pattern 202 having a predetermined pattern is formed so as to be connected to the UBM 40.
  • the UBM 40 functions as a via hole that electrically connects the conductive pattern 201 on the surface of the Si substrate 20A and the conductive pattern 202 constituting the rewiring layer.
  • the conductive pattern 202 of the rewiring layer has an electrode pattern that bridges the UBM 40 and the solder bump 50 that is an external connection bump as a CSP, and an electrode pattern that forms the second spiral electrode 21B.
  • the electrode pattern that bridges the UBM 40 and the solder bump 50 is formed so as to extend in a predetermined pattern from the position where the UBM 40 is formed to the position where the solder bump 50 is formed, as shown in the vicinity of the left end of FIG.
  • the electrode pattern that forms the second spiral electrode 21B has the same winding direction as the electrode pattern that forms the first spiral electrode 21A on the surface of the Si substrate 20A when the ESD protection device 10, that is, the Si substrate 20A is viewed in plan.
  • the first spiral electrode 21A and the second spiral electrode 21B are connected by a via hole made of UBM40. Thereby, an inductor Lr composed of the first spiral electrode 21A and the second spiral electrode 21B is realized.
  • an insulating protective layer 20Bi is formed so as to cover the conductive pattern 202 and the passivation layer 20Bp of the rewiring layer except for the solder bump formation position.
  • This protective layer 20Bi is formed of polyimide, for example.
  • the ESD protection device 10 of this embodiment can be realized by CSP by appropriately patterning the conductive pattern 201 on the surface of the Si substrate 20A, the conductive pattern 202 of the rewiring layer, the UBM 40, and the solder bump 50. .
  • the inductor Lr of the LC parallel resonant circuit 1 includes a first spiral electrode 21A composed of a conductive pattern 201 formed in a wound shape on a Si substrate 20A, and a distance from the first spiral electrode 21A.
  • the second spiral electrode 21 ⁇ / b> B made of the conductive pattern 202 that is also formed in a wound shape is provided at the position.
  • the outer peripheral end of the first spiral electrode 21A is connected to a lead-out electrode 31 made of the conductive pattern 201 that is also formed on the Si substrate 20A.
  • the first spiral electrode 21A is wound counterclockwise so that the diameter gradually decreases from the outer peripheral end to the inner peripheral end and in a plan view as shown in FIGS. 6 (C) and 6 (D). It is formed to turn.
  • the inner peripheral end of the first spiral electrode 21A is connected to the inner peripheral end of the second spiral electrode 21B by a via hole 41 made of UBM 40.
  • the second spiral electrode 21B has a shape having substantially the same electrode width as that of the first spiral electrode 21A, and gradually increases in diameter from the inner peripheral end to the outer peripheral end. ), The electrode is formed to be wound counterclockwise in a plan view. As shown in FIGS. 5 and 6B, the outer peripheral end of the second spiral electrode 21B is connected to the lead-out electrode 32 made of the conductive pattern 201 on the Si substrate 20A by a conductive via hole.
  • the first spiral electrode 21A and the second spiral electrode 21B are formed as a spiral electrode having a two-layer structure in which they are connected so that their winding directions coincide with each other. Thereby, the directions of the magnetic fields generated by the first spiral electrode 21A and the second spiral electrode 21B coincide. And since the electrode surfaces of the first spiral electrode 21A and the second spiral electrode 21B are close to each other, these magnetic fields are coupled, strong magnetic coupling is obtained, and a large mutual inductance can be generated. As a result, the inductance of the inductor Lr composed of the first spiral electrode 21A and the second spiral electrode 21B can be increased.
  • the Q value of resonance of the LC parallel resonant circuit 1 using the inductor Lr can be increased, and the attenuation pole when the ESD protection device functions as a low-pass filter can be a steep characteristic pole. Therefore, desired high frequency noise can be effectively removed.
  • the resistance value of the second spiral electrode 21B can be further lowered, and the resistance component can be further increased while improving the inductance of the inductor Lr than when the entire inductor Lr is formed of the first spiral electrode 21A. Can be suppressed. Also by this, the Q value of the LC parallel resonant circuit 1 including the inductor Lr can be improved, and a steeper attenuation pole can be formed.
  • FIG. 7 is a pass characteristic diagram showing the influence on the pass characteristic according to the number of spiral electrodes.
  • the thick solid line indicates the pass characteristic of the ⁇ -type ESD protection circuit 10P when the inductor Lr is configured by the first spiral electrode 21A on the Si substrate 20A
  • the thin solid line indicates the first spiral electrode 21A on the Si substrate 21A.
  • a thick broken line indicates a passing characteristic of the ⁇ -type ESD protection circuit 10P when the inductor Lr is configured by the first spiral electrode 21A on the Si substrate 20A and the second spiral electrode 21B of the rewiring layer
  • the thin broken line indicates the Si substrate 20A.
  • the pass characteristics of the T-type ESD protection circuit 10T when the inductor Lr is composed of the upper first spiral electrode 21A and the second spiral electrode 21B of the rewiring layer are shown.
  • the attenuation pole can be obtained only by forming the first spiral electrode 21A on the Si substrate 20A. Further, by using the above-described two-layer structure of the first spiral electrode 21A and the second spiral electrode 21B, the attenuation amount of the attenuation pole can be further increased and steep characteristics can be obtained.
  • FIG. 8 is an exploded perspective view schematically showing another structure of the inductor Lr.
  • the first spiral electrode 21A and the second spiral electrode 21B are the same as those shown in FIGS. 5 and 6, and will not be described.
  • the third spiral electrode 21C has substantially the same electrode width as that of the first spiral electrode 21A and the second spiral electrode 21B, and substantially the same area.
  • the outer peripheral end of the third spiral electrode 21C is connected to the outer peripheral end of the second spiral electrode 21B by a via hole 41 '.
  • the third spiral electrode 21C is formed to be wound counterclockwise in a plan view so that the diameter gradually decreases from the outer peripheral end to the inner peripheral end. That is, the third spiral electrode 21C is formed in the same winding direction as the first spiral electrode 21A and the second spiral electrode 21B.
  • the length of the electrode as the inductor Lr can be further extended to increase the inductance, and the mutual relationship between the first spiral electrode 21A, the second spiral electrode 21B, and the third spiral electrode 21C can be increased.
  • the inductance By the inductance, the inductance as the inductor Lr can be further increased.
  • the Q value of the LC parallel resonance circuit 1 can be further increased, and a steeper attenuation pole can be formed.
  • the number of spiral electrodes of the rewiring layer to be formed is not limited to one and two as described above, but may be three or more according to product specifications. At this time, as described above, the winding direction of each spiral electrode coincides, that is, the directions of the generated magnetic fields are the same, and the magnetic fields are strengthened to increase the inductance, The Q value of the LC parallel resonant circuit can be increased.
  • an ESD protection device that functions as a low-pass filter having an attenuation pole at a desired frequency when the ESD protection function is not activated. That is, an ESD protection device that attenuates desired high-frequency noise while discharging a signal (communication signal) in a frequency band to be passed with low loss, and discharges the static electricity to the ground when the static electricity is superimposed on the signal line. Can be realized. At this time, by realizing the ESD protection device by CSP, such a multifunctional and high-performance ESD protection device can be formed in a small size.
  • FIG. 9A is a circuit diagram of an ESD protection circuit 11P having the configuration of the present invention
  • FIG. 9B is an equivalent circuit diagram when the ESD elements ESD1, ESD2, and ESD3 of the ESD protection circuit 11P are in an OFF state. .
  • the connection point between the resistor R and the LC resonance circuit 1 is further connected to the ground by the ESD element ESD3 with respect to the ESD protection circuit 10P shown in FIG. It has a configuration.
  • three low-pass filters can be configured in the ESD protection circuit 11P. Specifically, a first filter 1A composed of ESD elements ESD1, ESD3 and a resistor R, a second filter 1B composed of ESD elements ESD2, ESD3 and an inductor Lr and a capacitor Cr of the LC resonance circuit 1, The ESD elements ESD1, ESD2, the resistor R, and the third filter 1C including the inductor Lr and the capacitor Cr of the LC resonance circuit 1 are configured.
  • the first filter 1A has a configuration in which both ends of the resistor R are connected to the ground by ESD elements ESD1 and ESD3, respectively.
  • This circuit is a C—R—C ⁇ -type filter when the ESD elements ESD1 and ESD3 are OFF.
  • the second filter 1B has a configuration in which both ends of the parallel circuit of the inductor Lr and the capacitor Cr are connected to the ground by ESD2 and ESD3, respectively.
  • This circuit is a C-LC-C ⁇ -type filter when the ESD elements ESD2 and ESD3 are OFF.
  • the third filter 1C has a configuration in which both ends of a circuit in which a resistor R and a parallel circuit of an inductor Lr and a capacitor Cr are connected in series are connected to the ground by ESD elements ESD1 and ESD2, respectively.
  • This circuit is a CR-LC-C ⁇ -type filter when the ESD elements ESD1 and ESD2 are OFF.
  • FIG. 10 is a diagram showing pass characteristics of an ESD protection device including the circuits of FIGS. As described above, by using the configuration of FIG. 9, an ESD protection device having a superior high-frequency attenuation characteristic can be formed.
  • FIG. 11 is a circuit diagram of an ESD protection device having still another configuration according to the present invention.
  • a resistor Rb is connected between one end of the ESD element ESD3 and the LC resonance circuit 1.
  • a resistor Rb is connected between one end of the ESD element ESD3 and one end of the ESD element ESD2.
  • the resistance value of the resistor Ra connected between the ESD element ESD1 and the ESD element ESD3 is appropriately adjusted by inserting the resistor Rb. For example, if the resistor R in FIG. 1 has a resistance value of 100 ⁇ , the resistor Ra may be set to 90 ⁇ and the resistor Rb to 10 ⁇ .
  • the ESD element ESD3 may be simply constituted by a capacitor.
  • the capacitor may be formed by an electrode pattern on the surface of the Si substrate and an electrode pattern on the rewiring layer.
  • a capacitor for adjusting the attenuation pole can be formed with a simple configuration.
  • the inductor Lr formed on the Si substrate is formed by using the electrode pattern of the inductor Lr formed on the Si substrate as one counter electrode of the capacitor and forming the other counter electrode on the rewiring layer. There is no need to form a connection electrode (such as a conductive via hole) for connecting to the rewiring layer.
  • an ESD protection device can be realized with a simpler configuration.
  • a meander electrode can also be used as the inductor Lr of the LC parallel resonant circuit.
  • the inductor Lr of the LC parallel resonant circuit is formed using the rewiring layer.
  • the inductor Lr may be formed only by the conductive pattern on the Si substrate.
  • the two spiral electrodes do not necessarily have to be formed in the same shape, the same region, and the same direction. .
  • the ESD element is realized by a series circuit of diodes.
  • a Si substrate if a Si substrate is used, a Zener diode or FET may be used, or a varistor may be used.
  • achieves an ESD protection device by CSP using Si substrate was shown, the above-mentioned ESD protection circuit is comprised from the resin-type laminated substrate, the pattern electrode formed in the said laminated substrate, and mounting components. May be.

Abstract

Disclosed is an ESD protection device which can reliably perform ESD protection, while sufficiently ensuring an attenuation at a desired frequency. The ESD protection device is provided with a configuration wherein a resistor (R) and an LC parallel resonance circuit (1) are connected in series on a signal line. Both the ends of the series circuit of the resistor (R) and the LC parallel resonance circuit (1) are connected to the ground by means of ESD elements (ESD1, ESD2). In such circuit configuration, when a signal line has a surge of static electricity, the ESD elements (ESD1, ESD2) are in the ON-state, and static electricity is discharged to the ground. When the ESD elements (ESD1, ESD2) are in the OFF-state, the ESD protection device functions as a lowpass filter, which is composed of a π-type C-R-LC-C connection and has an attenuation pole with respect to the desired frequency.

Description

ＥＳＤ保護デバイスESD protection device
　この発明は、半導体ＩＣ等を静電気から保護する静電気保護デバイス（ＥＳＤ保護デバイス）に関するものである。 This invention relates to an electrostatic protection device (ESD protection device) for protecting a semiconductor IC or the like from static electricity.
　現在、携帯端末等には、半導体集積ＩＣ等の各種電子デバイスが搭載されている。そして、このような端末では、電子デバイスを静電気から保護する静電気保護デバイス（ＥＳＤ（Ｅｌｅｃｔｒｏ　Ｓｔａｓｔｉｃ　Ｄｉｓｃｈａｒｇｅ）デバイス）が、搭載されている。 Currently, various electronic devices such as semiconductor integrated ICs are mounted on portable terminals and the like. In such a terminal, an electrostatic protection device (ESD (Electro Static Discharge) device) that protects the electronic device from static electricity is mounted.
　このようなＥＳＤ保護デバイスとしては、図１２（Ａ）に示すようなπ型ＥＳＤ保護回路１０Ｐ’や、図１２（Ｃ）に示すようなＴ型ＥＳＤ保護回路１０Ｔ’を備える。図１２は、従来のＥＳＤ保護回路の例を示す等価回路図であり、図１２（Ａ），（Ｃ）は各ＥＳＤ保護回路の回路図であり、図１２（Ｂ），（Ｄ）はＥＳＤ素子がＯＦＦ状態での等価回路図である。また、図１２（Ａ），（Ｂ）はπ型ＥＳＤ保護回路を示し、図１２（Ｃ），（Ｄ）はＴ型ＥＳＤ保護回路を示す。 Such an ESD protection device includes a π-type ESD protection circuit 10P ′ as shown in FIG. 12A and a T-type ESD protection circuit 10T ′ as shown in FIG. FIG. 12 is an equivalent circuit diagram showing an example of a conventional ESD protection circuit. FIGS. 12A and 12C are circuit diagrams of the respective ESD protection circuits. FIGS. 12B and 12D are ESD diagrams. It is an equivalent circuit diagram in the state where an element is OFF. 12A and 12B show a π-type ESD protection circuit, and FIGS. 12C and 12D show a T-type ESD protection circuit.
　図１２（Ａ）に示すπ型ＥＳＤ保護回路１０Ｐ’は、抵抗器Ｒと、２個のＥＳＤ素子ＥＳＤ１，ＥＳＤ２とを備える。抵抗器Ｒは、入力ポートＰｉと出力ポートＰｏとの間の信号ラインに挿入されている。２個のＥＳＤ素子ＥＳＤ１，ＥＳＤ２は、それぞれ、当該抵抗器Ｒの両端に一方端が接続され、他方端がグランドに接続されている。このπ型ＥＳＤ保護回路は、特許文献１にも記載されている。 The π-type ESD protection circuit 10P ′ shown in FIG. 12A includes a resistor R and two ESD elements ESD1 and ESD2. The resistor R is inserted in a signal line between the input port Pi and the output port Po. Each of the two ESD elements ESD1, ESD2 has one end connected to both ends of the resistor R and the other end connected to the ground. This π-type ESD protection circuit is also described in Patent Document 1.
　また、図１２（Ｃ）に示すＴ型ＥＳＤ保護回路１０Ｔ’は、直列接続された２個の抵抗器Ｒと、ＥＳＤ素子ＥＳＤとを備える。直列接続された２個の抵抗器Ｒは、入力ポートＰｉと出力ポートＰｏとの間の信号ラインに挿入されている。ＥＳＤ素子ＥＳＤは、当該２個の抵抗器Ｒの接続点に一方端が接続され、他方端がグランドに接続されている。 The T-type ESD protection circuit 10T ′ shown in FIG. 12C includes two resistors R connected in series and an ESD element ESD. Two resistors R connected in series are inserted in a signal line between the input port Pi and the output port Po. The ESD element ESD has one end connected to the connection point of the two resistors R and the other end connected to the ground.
特開２００５－３５４０１４号公報JP 2005-354014 A
　ところで、図１２（Ａ）に示すようなπ型ＥＳＤ保護回路１０Ｐ’や、図１２（Ｃ）に示すようなＴ型ＥＳＤ保護回路１０Ｔ’は、ＥＳＤ素子がＯＦＦ状態の時、キャパシタＣｖとして機能する。したがって、図１２（Ａ）に示すπ型ＥＳＤ保護回路１０Ｐ’は、図１２（Ｂ）に示すＣ－Ｒ－Ｃ型のローパルスフィルタとして機能し、図１２（Ｃ）に示すＴ型ＥＳＤ保護回路１０Ｔ’は、図１２（Ｄ）に示すＲ－Ｃ－Ｒ型のローパルスフィルタとして機能する。 By the way, the π-type ESD protection circuit 10P ′ as shown in FIG. 12A and the T-type ESD protection circuit 10T ′ as shown in FIG. 12C function as the capacitor Cv when the ESD element is OFF. To do. Accordingly, the π-type ESD protection circuit 10P ′ shown in FIG. 12A functions as a CR-C type low pulse filter shown in FIG. 12B, and the T-type ESD protection shown in FIG. The circuit 10T ′ functions as an RCR type low pulse filter shown in FIG.
　しかしながら、このようなπ型ＥＳＤ保護回路１０Ｐ’やＴ型ＥＳＤ保護回路１０Ｔ’からなるローパスフィルタは、通過帯域の高域端では、単調に減衰量が増加する特性となる。したがって、例えば、この通過帯域の高域端で減衰量が少ない周波数に、高周波ノイズが存在した場合、当該高周波ノイズを減衰させることができない。 However, such a low-pass filter including the π-type ESD protection circuit 10P ′ and the T-type ESD protection circuit 10T ′ has a characteristic that the amount of attenuation increases monotonously at the high band end of the pass band. Therefore, for example, when high-frequency noise exists at a frequency with a small attenuation at the high end of the pass band, the high-frequency noise cannot be attenuated.
　本発明の目的は、所望の周波数の減衰量を十分に確保しながら、確実にＥＳＤ保護を行えるＥＳＤ保護デバイスを実現することにある。 An object of the present invention is to realize an ESD protection device that can reliably perform ESD protection while sufficiently securing an attenuation amount of a desired frequency.
　（１）この発明のＥＳＤ保護デバイスは、信号ラインに挿入された抵抗器と、該抵抗器の両端とグランドとをそれぞれに接続する２個のＥＳＤ素子と、信号ライン上において抵抗器に直列接続されたＬＣ並列共振器と、を備える。 (1) An ESD protection device according to the present invention includes a resistor inserted in a signal line, two ESD elements for connecting both ends of the resistor and the ground, and a resistor connected in series on the signal line. An LC parallel resonator.
　この構成では、抵抗器と２個のＥＳＤ素子とによりＥＳＤ保護機能とローパスフィルタ機能とを有するπ型ＥＳＤ保護回路が構成される。そして、ＬＣ並列共振器によりローパスフィルタとして機能する際の減衰極が形成される。ここで、ＬＣ並列共振器の共振周波数を、除去したい高周波ノイズの周波数に設定すれば、当該周波数に減衰極が形成され、高周波ノイズが大幅に減衰される。また、ＬＣ並列共振器を信号ラインへ挿入しても、ライン容量は変化しないので、減衰極を形成する以外の伝送特性に殆ど影響を与えない。 In this configuration, a resistor and two ESD elements constitute a π-type ESD protection circuit having an ESD protection function and a low-pass filter function. And the attenuation pole at the time of functioning as a low-pass filter is formed by LC parallel resonator. Here, if the resonance frequency of the LC parallel resonator is set to the frequency of the high frequency noise to be removed, an attenuation pole is formed at the frequency, and the high frequency noise is greatly attenuated. Further, even if the LC parallel resonator is inserted into the signal line, the line capacitance does not change, so that there is almost no influence on the transmission characteristics other than the formation of the attenuation pole.
　（２）また、この発明のＥＳＤ保護デバイスのＬＣ並列共振器は、信号ラインにおける抵抗器の一方端と該一方端に接続するＥＳＤ素子との間に接続されている。 (2) Further, the LC parallel resonator of the ESD protection device of the present invention is connected between one end of the resistor in the signal line and the ESD element connected to the one end.
　この構成では、ＬＣ並列共振器が、２個のＥＳＤ素子がそれぞれ信号ラインへの接続する２個の接続点の中間に配置される。これにより、信号ラインのいずれの方向から、静電気が重畳されても、ＥＳＤ素子によりグランドへ放電され、ＬＣ並列共振器へは静電気がサージされない。これにより、通常のＥＳＤ保護機能とともに、ＬＣ並列共振器のキャパシタの破壊を防止できる。特に、ＬＣ並列共振器のインダクタを、後述のスパイラル電極で形成する場合、インダクタの抵抗成分が大きくなり、キャパシタに電流が流れやすいので、当該構造を用いれば、キャパシタの静電気破壊の防止に、より有効である。 In this configuration, the LC parallel resonator is arranged in the middle of two connection points where the two ESD elements are respectively connected to the signal line. Thereby, even if static electricity is superimposed from any direction of the signal line, it is discharged to the ground by the ESD element, and static electricity is not surged to the LC parallel resonator. Thereby, destruction of the capacitor of the LC parallel resonator can be prevented together with the normal ESD protection function. In particular, when the inductor of the LC parallel resonator is formed with a spiral electrode described later, the resistance component of the inductor increases and current flows easily through the capacitor. Therefore, using this structure can prevent electrostatic breakdown of the capacitor. It is valid.
　（３）また、この発明のＥＳＤ保護デバイスは、信号ラインに挿入され、互いに直列接続された２個の抵抗器と、該直列接続された２個の抵抗器の接続点とグランドとを接続するＥＳＤ素子と、抵抗器のいずれか一方と接続点との間の信号ラインに直列接続されたＬＣ並列共振器と、を備える。 (3) Further, the ESD protection device of the present invention connects two resistors inserted in a signal line and connected in series with each other, and a connection point between the two resistors connected in series and the ground. An ESD element, and an LC parallel resonator connected in series to a signal line between one of the resistors and the connection point.
　この構成では、２個の抵抗器とＥＳＤ素子とによりＥＳＤ保護機能とローパスフィルタ機能とを有するＴ型ＥＳＤ保護回路が構成される。そして、ＬＣ並列共振器によりローパスフィルタとして機能する際の減衰極が形成される。ここで、ＬＣ並列共振器の共振周波数を、除去したい高周波ノイズの周波数に設定すれば、当該周波数に減衰極が形成され、高周波ノイズが大幅に減衰される。また、ＬＣ並列共振器を信号ラインへ挿入しても、ライン容量は変化しないので、減衰極を形成する以外の伝送特性に殆ど影響を与えない。 In this configuration, a T-type ESD protection circuit having an ESD protection function and a low-pass filter function is configured by two resistors and an ESD element. And the attenuation pole at the time of functioning as a low-pass filter is formed by LC parallel resonator. Here, if the resonance frequency of the LC parallel resonator is set to the frequency of the high frequency noise to be removed, an attenuation pole is formed at the frequency, and the high frequency noise is greatly attenuated. Further, even if the LC parallel resonator is inserted into the signal line, the line capacitance does not change, so that there is almost no influence on the transmission characteristics other than the formation of the attenuation pole.
　（４）また、この発明のＥＳＤ保護デバイスのＬＣ並列共振器を構成するインダクタは、信号ラインが形成されるシリコン基板上に形成された導電性パターンからなる。 (4) Further, the inductor constituting the LC parallel resonator of the ESD protection device of the present invention comprises a conductive pattern formed on a silicon substrate on which a signal line is formed.
　この構成では、ＬＣ並列共振器のインダクタの具体的形成方法を示すものであり、シリコン基板上に形成することで、信号ラインと一体で形成することができる。また、シリコン基板を用いることで、ＬＣ並列共振回路のキャパシタや、ＥＳＤ保護デバイスの抵抗器ＲやＥＳＤ素子を集約的に形成することができる。 This configuration shows a specific method for forming an inductor of an LC parallel resonator, and can be formed integrally with a signal line by being formed on a silicon substrate. Further, by using the silicon substrate, it is possible to collectively form the capacitor of the LC parallel resonance circuit, the resistor R and the ESD element of the ESD protection device.
　（５）また、この発明のＥＳＤ保護デバイスのインダクタは、シリコン基板の導電性パターンに対して離間された再配線層の導電性パターンと、該再配線層上の導電性パターンとシリコン基板上の導電性パターンとを導通するビアホールと、をさらに備える。 (5) The inductor of the ESD protection device according to the present invention includes a conductive pattern of a redistribution layer separated from a conductive pattern of a silicon substrate, a conductive pattern on the redistribution layer, and a silicon substrate. And a via hole that conducts the conductive pattern.
　この構成では、インダクタがシリコン基板表面の導電性パターンと、当該シリコン基板表面の導電性パターンから所定間隔離間された位置に形成された再配線層の導電性パターンとから形成される。そして、これらがビアホールにより電気的に接続されるので、複数層に亘る電極によりインダクタが形成される。これにより、一層構造よりもインダクタの電極長を長く取ることが可能になり、高いインダクタンスを実現できる。この結果、ＬＣ並列共振器のＱ値を高めることができ、より急峻な減衰極を実現できる。 In this configuration, the inductor is formed of the conductive pattern on the surface of the silicon substrate and the conductive pattern of the rewiring layer formed at a position spaced apart from the conductive pattern on the surface of the silicon substrate. And since these are electrically connected by a via hole, an inductor is formed by the electrode over a plurality of layers. As a result, it is possible to make the electrode length of the inductor longer than that of the single layer structure, and a high inductance can be realized. As a result, the Q value of the LC parallel resonator can be increased, and a steeper attenuation pole can be realized.
　（６）また、この発明のＥＳＤ保護デバイスのインダクタは、さらなる少なくとも１つの再配線層の導電性パターンと、各再配線層の導電性パターン同士を接続するビアホールとを、さらに備える。 (6) Further, the inductor of the ESD protection device of the present invention further includes a conductive pattern of at least one redistribution layer and a via hole that connects the conductive patterns of each redistribution layer.
　この構成では、さらに再配線層の導電性パターンを増やし、シリコン基板上の導電性パターンおよび各再配線層の導電性パターンを接続することで、より高いインダクタンスを実現できる。これにより、ＬＣ並列共振器のＱ値をさらに高めることができ、より一層、急峻な減衰極を実現できる。 In this configuration, a higher inductance can be realized by further increasing the conductive pattern of the rewiring layer and connecting the conductive pattern on the silicon substrate and the conductive pattern of each rewiring layer. Thereby, the Q value of the LC parallel resonator can be further increased, and a steeper attenuation pole can be realized.
　（７）また、この発明のＥＳＤ保護デバイスの再配線層の導電性パターンは、シリコン基板上の導電性パターンよりも電極厚みが厚い。 (7) Further, the conductive pattern of the rewiring layer of the ESD protection device of the present invention has a thicker electrode than the conductive pattern on the silicon substrate.
　この構成では、再配線層の導電性パターンを用いることでインダクタの電極長を長くしてインダクタンスを向上させながらも、再配線層の厚みが厚いことで抵抗値の増加を抑制することができる。これにより、ＬＣ並列共振器のＱ値をさらに急峻にすることができ、より一層、急峻な減衰極を実現できる。 In this configuration, it is possible to suppress an increase in resistance value by increasing the thickness of the rewiring layer while using a conductive pattern of the rewiring layer to increase the inductor length and improve the inductance. Thereby, the Q value of the LC parallel resonator can be made steeper, and a steeper attenuation pole can be realized.
　（８）また、この発明のＥＳＤ保護デバイスの再配線層の導電性パターンは、シリコン基板上の導電性パターンよりも導電率が高い材料で形成されている。 (8) Further, the conductive pattern of the rewiring layer of the ESD protection device of the present invention is formed of a material having higher conductivity than the conductive pattern on the silicon substrate.
　この構成では、再配線層の導電性パターンを用いることでインダクタの電極長を長くしてインダクタンスを向上させながらも、再配線層の導電率が高いことで、さらに抵抗値の増加を抑制することができる。これにより、ＬＣ並列共振器のＱ値をさらに急峻にすることができ、より一層、急峻な減衰極を実現できる。 In this configuration, the conductive pattern of the rewiring layer is used to increase the inductance of the inductor by increasing the electrode length of the inductor, but the rewiring layer has a high conductivity to further suppress an increase in resistance value. Can do. Thereby, the Q value of the LC parallel resonator can be made steeper, and a steeper attenuation pole can be realized.
　（９）また、この発明のＥＳＤ保護デバイスのシリコン基板上の導電性パターンは、スパイラル電極からなる。 (9) Further, the conductive pattern on the silicon substrate of the ESD protection device of the present invention comprises a spiral electrode.
　この構成では、導電性パターンのインダクタの形成パターンの一例として、スパイラル電極を用いる場合を示すものである。このようなスパイラル電極を用いることで、同じ面積からなるミアンダ電極よりもインダクタンスを高くすることができる。これにより、ＬＣ並列共振器のＱ値を高めることができ、より急峻な減衰極を実現できる。 This configuration shows a case where a spiral electrode is used as an example of a conductive pattern inductor formation pattern. By using such a spiral electrode, the inductance can be made higher than that of the meander electrode having the same area. Thereby, the Q value of the LC parallel resonator can be increased, and a steeper attenuation pole can be realized.
　（１０）また、この発明のＥＳＤ保護デバイスのシリコン基板上の導電性パターンと再配線層の導電性パターンは、略同一形状で、且つ、同一領域で、シリコン基板を平面視した状態で同一方向に巻回するスパイラル電極からなる。 (10) Further, the conductive pattern on the silicon substrate of the ESD protection device of the present invention and the conductive pattern of the redistribution layer have substantially the same shape and the same direction in the same region in a plan view of the silicon substrate. It consists of a spiral electrode wound around.
　この構成では、各層に形成されるスパイラル電極が全て同方向に巻回して接続されることで、シリコン基板上のみにスパイラル電極を形成するよりも、巻数の多いインダクタを実現できる。これにより、インダクタンスを高くすることができる。さらに、各層のスパイラル電極の巻回面、すなわち各導電性パターン同士が近接し、各スパイラル電極同士が磁気結合することで、相互インダクタンスが発生して、さらにインダクタンスを高くすることができる。この結果、ＬＣ並列共振器のＱ値をさらに高めることができ、より一層、急峻な減衰極を実現できる。 In this configuration, all the spiral electrodes formed in each layer are wound and connected in the same direction, so that an inductor having a larger number of turns can be realized than when the spiral electrode is formed only on the silicon substrate. Thereby, an inductance can be made high. Furthermore, the winding surfaces of the spiral electrodes of each layer, that is, the conductive patterns are close to each other and the spiral electrodes are magnetically coupled to each other, thereby generating mutual inductance and further increasing the inductance. As a result, the Q value of the LC parallel resonator can be further increased, and a steeper attenuation pole can be realized.
　（１１）また、この発明のＥＳＤ保護デバイスでは、抵抗器とＬＣ並列共振器との間の信号ラインに一方端が接続し、他方端がグランドへ接続するキャパシタをさらに備える。 (11) Further, the ESD protection device of the present invention further includes a capacitor having one end connected to the signal line between the resistor and the LC parallel resonator and the other end connected to the ground.
　この構成では、ＥＳＤ保護デバイスが複数の共振回路で構成されるので、減衰極をより急峻な特性にすることが可能になる。 In this configuration, since the ESD protection device is composed of a plurality of resonance circuits, it is possible to make the attenuation pole have a steeper characteristic.
　（１２）また、この発明のＥＳＤ保護デバイスでは、キャパシタは、２個のＥＳＤ素子とは異なる第３のＥＳＤ素子からなる。 (12) Further, in the ESD protection device of the present invention, the capacitor includes a third ESD element different from the two ESD elements.
　この構成では、キャパシタの具体的形成例を示している。 This configuration shows a specific example of capacitor formation.
　（１３）また、この発明のＥＳＤ保護デバイスでは抵抗器は２個の部分抵抗器からなり、該２個の部分抵抗器は第３のＥＳＤ素子の一方端から２個のＥＳＤ素子に向かうそれぞれの信号ライン上に個別に接続されている。 (13) Further, in the ESD protection device of the present invention, the resistor includes two partial resistors, and the two partial resistors are respectively connected to the two ESD elements from one end of the third ESD element. Individually connected on the signal line.
　この構成では、部分抵抗器により、第３のＥＳＤ素子へ流入するＥＳＤを低くでき、当該第３のＥＳＤ素子の破壊を防止できる。 In this configuration, the ESD that flows into the third ESD element can be lowered by the partial resistor, and the destruction of the third ESD element can be prevented.
　（１４）また、この発明のＥＳＤ保護デバイスでは、キャパシタは、信号ラインが形成されるシリコン基板上に形成された導電性パターンと、シリコン基板上に形成された導電性パターンに対して離間された再配線層の導電性パターンと、から構成される。 (14) In the ESD protection device of the present invention, the capacitor is separated from the conductive pattern formed on the silicon substrate on which the signal line is formed and the conductive pattern formed on the silicon substrate. And a conductive pattern of the rewiring layer.
　この構成では、キャパシタをＥＳＤ素子で形成しない場合の具体的構造を示している。 This configuration shows a specific structure when the capacitor is not formed by an ESD element.
　（１５）また、この発明のＥＳＤ保護デバイスでは、キャパシタを形成するシリコン基板上に形成された導電性パターンは、ＬＣ並列共振器のインダクタを構成する導電性パターンを兼ねる。 (15) In the ESD protection device of the present invention, the conductive pattern formed on the silicon substrate forming the capacitor also serves as the conductive pattern constituting the inductor of the LC parallel resonator.
　この構成も、キャパシタの具体的構造を示している。このような構造とすれば、Ｓｉ基板上のＬＣ並列共振器のインダクタを構成する電極パターンを再配線層や外部へ接続するためのビアホール等の接続電極を省略でき、構造的に簡素化できる。 This configuration also shows the specific structure of the capacitor. With such a structure, connection electrodes such as via holes for connecting the electrode pattern constituting the inductor of the LC parallel resonator on the Si substrate to the rewiring layer and the outside can be omitted, and the structure can be simplified.
　この発明によれば、除去したい高周波ノイズの周波数に減衰極を形成し、当該高周波ノイズを十分に減衰でき、且つ確実にＥＳＤ保護を行えるＥＳＤ保護デバイスを実現することができる。 According to the present invention, it is possible to realize an ESD protection device that forms an attenuation pole at the frequency of the high-frequency noise to be removed, can sufficiently attenuate the high-frequency noise, and can reliably perform ESD protection.
本実施形態に係るＥＳＤ保護デバイスのπ型ＥＳＤ保護回路の回路図およびＥＳＤ素子がＯＦＦ状態での等価回路図である。FIG. 4 is a circuit diagram of a π-type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. 本実施形態に係るＥＳＤ保護デバイスおよび従来のＥＳＤ保護デバイスの通過特性図である。It is a passage characteristic figure of the ESD protection device concerning this embodiment, and the conventional ESD protection device. 本実施形態に係るＥＳＤ保護デバイスのＴ型ＥＳＤ保護回路の回路図およびＥＳＤ素子がＯＦＦ状態での等価回路図である。FIG. 4 is a circuit diagram of a T-type ESD protection circuit of the ESD protection device according to the present embodiment and an equivalent circuit diagram when an ESD element is in an OFF state. 本実施形態のＥＳＤ保護デバイスの構造を説明するための側面断面図である。It is side surface sectional drawing for demonstrating the structure of the ESD protection device of this embodiment. インダクタＬｒの構造を模式的に示す外観斜視図、および、その分解斜視図である。It is the external appearance perspective view which shows the structure of the inductor Lr typically, and its exploded perspective view. インダクタＬｒを構成する再配線層の第２スパイラル電極２１Ｂの平面図およびその側面断面図と、Ｓｉ基板２０Ａ表面に形成された第１スパイラル電極２１Ａの平面図およびその側面断面図である。FIG. 6 is a plan view and a side sectional view of the second spiral electrode 21B of the redistribution layer constituting the inductor Lr, and a plan view and a side sectional view of the first spiral electrode 21A formed on the surface of the Si substrate 20A. スパイラル電極の個数に応じた通過特性への影響を示す通過特性図である。It is a passage characteristic diagram which shows the influence on the passage characteristic according to the number of spiral electrodes. インダクタＬｒの他の構造を模式的に示す分解斜視図である。It is a disassembled perspective view which shows typically the other structure of the inductor Lr. 本発明のその他の構成からなるＥＳＤ保護デバイスの回路図およびＥＳＤ素子がＯＦＦ状態での等価回路図である。It is the circuit diagram of the ESD protection device which consists of another structure of this invention, and an equivalent circuit diagram in the state where an ESD element is OFF. 図９の回路からなるＥＳＤ保護デバイスの通過特性を表す図である。It is a figure showing the passage characteristic of the ESD protection device which consists of a circuit of FIG. 本発明のさらにその他の構成からなるＥＳＤ保護デバイスの回路図である。It is a circuit diagram of the ESD protection device which consists of other composition of the present invention. 従来のＥＳＤ保護回路の回路図、およびＥＳＤ素子がＯＦＦ状態での等価回路図である。FIG. 6 is a circuit diagram of a conventional ESD protection circuit and an equivalent circuit diagram when an ESD element is in an OFF state.
　本発明の実施形態に係るＥＳＤ保護デバイスについて、図を参照して説明する。なお、以下の回路説明では、入力ポートＰｉおよび出力ポートＰｏは説明の便宜上記載するものであり、これらが無い場合すなわち信号ラインのみの場合であっても、本実施形態の回路構成を適用することができる。
（１）π型ＥＳＤ保護回路１０Ｐの場合
　図１（Ａ）はπ型ＥＳＤ保護回路１０Ｐの回路図、図１（Ｂ）はπ型ＥＳＤ保護回路１０ＰにおけるＥＳＤ素子ＥＳＤ１，ＥＳＤ２がＯＦＦ状態の等価回路図を示す。 An ESD protection device according to an embodiment of the present invention will be described with reference to the drawings. In the following circuit description, the input port Pi and the output port Po are described for convenience of description, and the circuit configuration of the present embodiment is applied even when there is no input port, that is, only a signal line. Can do.
(1) In the case of the π-type ESD protection circuit 10P FIG. 1A is a circuit diagram of the π-type ESD protection circuit 10P, and FIG. A circuit diagram is shown.
　π型ＥＳＤ保護回路１０Ｐは、信号ラインの所定位置、図１（Ａ）であれば信号ラインの入力ポートＰｉと出力ポートＰｏとの間に抵抗器Ｒが接続されている。抵抗器Ｒの一方端には、ＥＳＤ素子ＥＳＤ１の一方端が接続され、当該ＥＳＤ素子ＥＳＤ１の他方端はグランドに接続されている。抵抗器Ｒの他方端には、ＬＣ並列共振回路１を介してＥＳＤ素子ＥＳＤ２の一方端が接続され、当該ＥＳＤ素子ＥＳＤ２の他方端はグランドに接続されている。 In the π-type ESD protection circuit 10P, a resistor R is connected between a predetermined position of the signal line, that is, the input port Pi and the output port Po of the signal line in FIG. One end of the resistor R is connected to one end of the ESD element ESD1, and the other end of the ESD element ESD1 is connected to the ground. One end of the ESD element ESD2 is connected to the other end of the resistor R via the LC parallel resonant circuit 1, and the other end of the ESD element ESD2 is connected to the ground.
　ＬＣ並列共振器１は、インダクタＬｒとキャパシタＣｒとの並列回路からなり、信号ライン上において抵抗器Ｒと直列接続されている。この際、ＬＣ並列共振回路１は、抵抗器ＲのＥＳＤ素子ＥＳＤ２側の端部と、ＥＳＤ素子ＥＳＤ２が信号ラインに接続する接続点との間に挿入されるように接続されている。 The LC parallel resonator 1 includes a parallel circuit of an inductor Lr and a capacitor Cr, and is connected in series with a resistor R on a signal line. At this time, the LC parallel resonant circuit 1 is connected so as to be inserted between the end of the resistor R on the ESD element ESD2 side and the connection point where the ESD element ESD2 is connected to the signal line.
　このような回路構成からなるπ型ＥＳＤ保護回路１０Ｐでは、信号ラインに静電気が重畳しなければ、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２はＯＦＦ状態となり、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２は、それぞれキャパシタＣｖとして機能する。したがって、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２がＯＦＦ状態では、π型ＥＳＤ保護回路１０Ｐは、図１（Ｂ）に示すように、抵抗器ＲとＬＣ並列共振回路１とが信号ライン上で直列接続され、当該直列回路の両端が、キャパシタＣｖでそれぞれグランドへ接続される構造となる。これにより、π型ＥＳＤ保護回路１０Ｐは、Ｃ－Ｒ－ＬＣ－Ｒ型のローパスフィルタとして機能する。 In the π-type ESD protection circuit 10P having such a circuit configuration, unless static electricity is superimposed on the signal line, the ESD elements ESD1 and ESD2 are turned off, and the ESD elements ESD1 and ESD2 each function as a capacitor Cv. Therefore, when the ESD elements ESD1 and ESD2 are in the OFF state, as shown in FIG. 1B, the π-type ESD protection circuit 10P includes the resistor R and the LC parallel resonant circuit 1 connected in series on the signal line. Both ends of the series circuit are connected to the ground by the capacitor Cv. As a result, the π-type ESD protection circuit 10P functions as a CR-LC-R type low-pass filter.
　図２は、本実施形態のπ型ＥＳＤ保護回路１０Ｐおよび図１２に示した従来のπ型ＥＳＤ保護回路１０Ｐ’の通過特性と、後述の図３に示す本実施形態のＴ型ＥＳＤ保護回路１０Ｔおよび図１２に示した従来のＴ型ＥＳＤ保護回路１０Ｔ’の通過特性とを示す図である。 2 shows the pass characteristics of the π-type ESD protection circuit 10P of this embodiment and the conventional π-type ESD protection circuit 10P ′ shown in FIG. 12, and the T-type ESD protection circuit 10T of this embodiment shown in FIG. It is a figure which shows the passage characteristic of the conventional T type ESD protection circuit 10T 'shown in FIG.
　従来のπ型ＥＳＤ保護回路１０Ｐ’はＣ－Ｒ－Ｃ型のローパスフィルタとして機能するので、図２の太破線に示すように、通過帯域の高域側で単調に減衰量が増加する特性（通過量が低下する特性）となる。しかしながら、本実施形態のπ型ＥＳＤ保護回路１０Ｐは、ＬＣ並列共振回路１を有することで、通過帯域の高域側に減衰極を設けることができる。したがって、当該減衰極の周波数を、所望とする高周波ノイズの周波数に設定することで、当該高周波ノイズを大幅に減衰させることができる。そして、本実施形態のようにＬＣ並列共振回路１を、信号ラインに直列接続する構成を備えることで、ライン容量すなわち信号ラインとグランドとの間の容量を変化させることなく、減衰極を形成することができる。これにより、当該π型ＥＳＤ保護回路１０Ｐを伝送する信号の歪みの発生を抑制できる。 Since the conventional π-type ESD protection circuit 10P ′ functions as a C—R—C type low-pass filter, as shown by a thick broken line in FIG. Characteristic that the passing amount decreases). However, the π-type ESD protection circuit 10P according to the present embodiment includes the LC parallel resonance circuit 1, and thus can provide an attenuation pole on the high band side of the pass band. Therefore, by setting the frequency of the attenuation pole to the desired high frequency noise frequency, the high frequency noise can be significantly attenuated. Then, the LC parallel resonant circuit 1 is connected in series to the signal line as in this embodiment, thereby forming the attenuation pole without changing the line capacitance, that is, the capacitance between the signal line and the ground. be able to. Thereby, generation | occurrence | production of the distortion of the signal which transmits the said (pi) -type ESD protection circuit 10P can be suppressed.
　一方、入力ポートＰｉもしくは出力ポートＰｏから信号ラインに静電気が重畳されると、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２がＯＮ状態に遷移し、信号ラインからグランドへ電流を流すことで、静電気がグランドへ放電される。 On the other hand, when static electricity is superimposed on the signal line from the input port Pi or the output port Po, the ESD elements ESD1 and ESD2 are turned on, and current flows from the signal line to the ground, so that the static electricity is discharged to the ground. .
　具体的には、入力ポートＰｉから静電気が信号ラインに重畳されると、ＥＳＤ素子ＥＳＤ１が先にＯＮ状態に遷移して、当該ＥＳＤ素子ＥＳＤ１を介して放電される。一方、出力ポートＰｏから静電気が信号ラインに重畳されると、ＥＳＤ素子ＥＳＤ２が先にＯＮ状態に遷移して、当該ＥＳＤ素子ＥＳＤ２を介して放電される。これにより、当該π型ＥＳＤ保護回路１０Ｐは、ＥＳＤ保護回路として機能する。 Specifically, when static electricity is superimposed on the signal line from the input port Pi, the ESD element ESD1 first shifts to the ON state and is discharged through the ESD element ESD1. On the other hand, when static electricity is superimposed on the signal line from the output port Po, the ESD element ESD2 first shifts to the ON state and is discharged through the ESD element ESD2. Thereby, the π-type ESD protection circuit 10P functions as an ESD protection circuit.
　そして、図１（Ａ）に示すように、ＬＣ並列共振回路１を、２個のＥＳＤ素子ＥＳＤ１，ＥＳＤ２の信号ラインへの接続点間に配置することで、入力ポートＰｉからの静電気も出力ポートＰｏからの静電気も、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２で放電されるので、ＬＣ並列共振回路１には静電気が重畳されない。したがって、ＬＣ並列共振回路１のキャパシタＣｒも静電気から保護することができる。特に、後述するように、ＬＣ並列共振回路１のインダクタＬｒをスパイラル電極で形成する場合、大きなインダクタンスを得るために電極長が長くなり、当該インダクタＬｒの抵抗成分が増加する。この場合、ＬＣ並列共振回路１へ静電気がサージされると、キャパシタに大電流が流れて、キャパシタが破壊されやすい。したがって、上述の構成とすることで、スパイラル電極を用いた場合におけるキャパシタの破壊に対して、より有効である。 As shown in FIG. 1A, the LC parallel resonant circuit 1 is arranged between the connection points of the two ESD elements ESD1 and ESD2 to the signal line, so that static electricity from the input port Pi is also output to the output port. Since static electricity from Po is also discharged by the ESD elements ESD1 and ESD2, static electricity is not superimposed on the LC parallel resonant circuit 1. Therefore, the capacitor Cr of the LC parallel resonant circuit 1 can also be protected from static electricity. In particular, as will be described later, when the inductor Lr of the LC parallel resonant circuit 1 is formed of a spiral electrode, the electrode length becomes long to obtain a large inductance, and the resistance component of the inductor Lr increases. In this case, when static electricity is surged into the LC parallel resonant circuit 1, a large current flows through the capacitor, and the capacitor is easily destroyed. Therefore, the above-described configuration is more effective for the destruction of the capacitor when the spiral electrode is used.
　なお、ＬＣ並列共振回路１は、２個のＥＳＤ素子ＥＳＤ１，ＥＳＤ２の信号ラインへの接続点間に配置する構成に限らず、信号ラインにおけるＥＳＤ素子ＥＳＤ１よりも入力ポートＰｉ側や、信号ラインにおけるＥＳＤ素子ＥＳＤ２よりも出力ポートＰｏ側に配置してもよい。この場合、入力ポートＰｉ側にＬＣ並列共振回路１を配置すれば出力ポートＰｏからの静電気によるＬＣ並列共振回路１のキャパシタＣｒの破壊を防止でき、出力ポートＰｏ側にＬＣ並列共振回路１を配置すれば入力ポートＰｉからの静電気によるＬＣ並列共振回路１のキャパシタＣｒの破壊を防止できる。 The LC parallel resonant circuit 1 is not limited to the configuration in which the two ESD elements ESD1 and ESD2 are arranged between the connection points to the signal line, but on the input port Pi side from the ESD element ESD1 in the signal line or in the signal line. You may arrange | position to the output port Po side rather than ESD element ESD2. In this case, if the LC parallel resonance circuit 1 is arranged on the input port Pi side, the destruction of the capacitor Cr of the LC parallel resonance circuit 1 due to static electricity from the output port Po can be prevented, and the LC parallel resonance circuit 1 is arranged on the output port Po side. This can prevent destruction of the capacitor Cr of the LC parallel resonant circuit 1 due to static electricity from the input port Pi.
　（２）Ｔ型ＥＳＤ保護回路１０Ｔの場合
　図３（Ａ）はＴ型ＥＳＤ保護回路１０Ｔの回路図、図３（Ｂ）はＴ型ＥＳＤ保護回路１０ＴにおけるＥＳＤ素子ＥＳＤがＯＦＦ状態の等価回路図を示す。 (2) Case of T-type ESD Protection Circuit 10T FIG. 3A is a circuit diagram of the T-type ESD protection circuit 10T, and FIG. 3B is an equivalent circuit diagram of the ESD element ESD in the T-type ESD protection circuit 10T in an OFF state. Indicates.
　Ｔ型ＥＳＤ保護回路１０Ｔは、信号ラインの所定位置、すなわち信号ラインの入力ポートＰｉと出力ポートＰｏとの間に、２個の抵抗器ＲとＬＣ並列共振回路１とが直列接続されている。例えば、図３（Ａ）の場合であれば、入力ポートＰｉ側から出力ポートＰｏ側へ抵抗器Ｒ、ＬＣ並列共振回路１、抵抗器Ｒの順に接続されている。 In the T-type ESD protection circuit 10T, two resistors R and the LC parallel resonance circuit 1 are connected in series between predetermined positions of the signal line, that is, between the input port Pi and the output port Po of the signal line. For example, in the case of FIG. 3A, the resistor R, the LC parallel resonant circuit 1, and the resistor R are connected in this order from the input port Pi side to the output port Po side.
　入力ポートＰｉ側の抵抗器ＲとＬＣ共振回路１との接続点には、ＥＳＤ素子ＥＳＤの一方端が接続されており、当該ＥＳＤ素子ＥＳＤの他方端はグランドに接続されている。 The one end of the ESD element ESD is connected to the connection point between the resistor R on the input port Pi side and the LC resonance circuit 1, and the other end of the ESD element ESD is connected to the ground.
　このような回路構成からなるＴ型ＥＳＤ保護回路１０Ｔでは、信号ラインに静電気が重畳しなければ、ＥＳＤ素子ＥＳＤはＯＦＦ状態となり、キャパシタＣｖとして機能する。したがって、ＥＳＤ素子ＥＳＤがＯＦＦ状態では、Ｔ型ＥＳＤ保護回路１０Ｔは、図３（Ｂ）に示すように、２個の抵抗器ＲとＬＣ並列共振回路１とが信号ライン上で直列接続され、当該直列回路の一方の抵抗器ＲとＬＣ並列共振回路１との接続点が、キャパシタＣｖでグランドへ接続される構造となる。これにより、Ｔ型ＥＳＤ保護回路１０Ｔは、Ｒ－Ｃ－ＬＣ－Ｒ型のローパスフィルタとして機能する。 In the T-type ESD protection circuit 10T having such a circuit configuration, unless static electricity is superimposed on the signal line, the ESD element ESD is turned off and functions as the capacitor Cv. Therefore, when the ESD element ESD is in the OFF state, as shown in FIG. 3B, the T-type ESD protection circuit 10T includes two resistors R and the LC parallel resonant circuit 1 connected in series on the signal line. A connection point between one resistor R of the series circuit and the LC parallel resonance circuit 1 is connected to the ground by a capacitor Cv. Thus, the T-type ESD protection circuit 10T functions as an RCLC-R-type low-pass filter.
　ここで、従来のＴ型ＥＳＤ保護回路１０Ｔ’はＲ－Ｃ－Ｒ型のローパスフィルタとして機能するので、図２の細破線に示すように、通過帯域の高域側で単調に減衰量が増加する特性（通過量が低下する特性）となる。しかしながら、本実施形態のＴ型ＥＳＤ保護回路１０Ｔは、ＬＣ並列共振回路１を有することで、通過帯域の高域側に減衰極を設けることができる。したがって、上述のπ型ＥＳＤ保護回路１０Ｐと同様に、当該減衰極の周波数を、所望とする高周波ノイズの周波数に設定することで、当該高周波ノイズを大幅に減衰させることができる。そして、本実施形態のようにＬＣ並列共振回路１を、信号ラインに直列接続する構成を備えることで、ライン容量すなわち信号ラインとグランドとの間の容量を変化させることなく、減衰極を形成することができる。これにより、当該Ｔ型ＥＳＤ保護回路１０Ｔを伝送する信号の歪みの発生を抑制できる。 Here, since the conventional T-type ESD protection circuit 10T ′ functions as an RCR type low-pass filter, the attenuation increases monotonously on the high band side of the passband as shown by the thin broken line in FIG. Characteristic (characteristic that the passing amount decreases). However, the T-type ESD protection circuit 10T according to the present embodiment includes the LC parallel resonance circuit 1, and thus can provide an attenuation pole on the high band side of the pass band. Therefore, similarly to the above-described π-type ESD protection circuit 10P, the high frequency noise can be greatly attenuated by setting the frequency of the attenuation pole to a desired frequency of the high frequency noise. Then, the LC parallel resonant circuit 1 is connected in series to the signal line as in this embodiment, thereby forming the attenuation pole without changing the line capacitance, that is, the capacitance between the signal line and the ground. be able to. Thereby, generation | occurrence | production of the distortion of the signal which transmits the said T type ESD protection circuit 10T can be suppressed.
　一方、入力ポートＰｉもしくは出力ポートＰｏから信号ラインに静電気が重畳されると、ＥＳＤ素子ＥＳＤがＯＮ状態に遷移し、信号ラインからグランドへ電流を流すことで、静電気がグランドへ放電される。これにより、当該Ｔ型ＥＳＤ保護回路１０Ｔは、ＥＳＤ保護回路として機能する。 On the other hand, when static electricity is superimposed on the signal line from the input port Pi or the output port Po, the ESD element ESD changes to the ON state, and current flows from the signal line to the ground, so that the static electricity is discharged to the ground. Thereby, the T-type ESD protection circuit 10T functions as an ESD protection circuit.
　なお、図３に示した２個の抵抗器ＲとＥＳＤ素子ＥＳＤとＬＣ並列共振回路１との接続関係は一例であり、基本的な構成としては、信号ライン上に２個の抵抗器Ｒが直列接続され、当該信号ライン上にさらにＬＣ並列共振回路１が直列接続される構成を備え、信号ラインにおける２つの抵抗器Ｒ間の所定位置がＥＳＤ素子ＥＳＤを介してグランドへ接続される構成であればよい。 The connection relationship between the two resistors R, the ESD element ESD, and the LC parallel resonance circuit 1 shown in FIG. 3 is an example. As a basic configuration, two resistors R are provided on the signal line. The LC parallel resonance circuit 1 is further connected in series on the signal line, and the predetermined position between the two resistors R in the signal line is connected to the ground via the ESD element ESD. I just need it.
　このように、ＬＣ並列共振回路をＥＳＤ保護回路の信号ラインに挿入する回路構成を用いることで、ＥＳＤ保護を確実に機能させるとともに、所望の周波数に減衰極を有するローパスフィルタとしても機能させることができる。すなわち、通過させたい周波数の信号を低損失で通過させ、所望とする高周波ノイズを確実に除去し、且つＥＳＤ保護を行えるＥＳＤ保護デバイスを実現することができる。 Thus, by using the circuit configuration in which the LC parallel resonant circuit is inserted into the signal line of the ESD protection circuit, the ESD protection can be surely functioned and also function as a low-pass filter having an attenuation pole at a desired frequency. it can. That is, it is possible to realize an ESD protection device that allows a signal having a desired frequency to pass therethrough with low loss, reliably removes desired high-frequency noise, and performs ESD protection.
　次に、このようなＥＳＤ保護デバイスの構造について図を参照して説明する。
　図４は、本実施形態のＥＳＤ保護デバイスの概略構造を説明する為の側面断面図である。なお、図４では、上述のπ型ＥＳＤ保護回路１０ＰのＥＳＤ素子ＥＳＤ１、抵抗器Ｒ、およびＬＣ並列共振回路のインダクタＬｒの回路部分を示している。 Next, the structure of such an ESD protection device will be described with reference to the drawings.
FIG. 4 is a side sectional view for explaining a schematic structure of the ESD protection device of the present embodiment. FIG. 4 shows circuit portions of the ESD element ESD1, the resistor R, and the inductor Lr of the LC parallel resonance circuit of the π-type ESD protection circuit 10P described above.
　また、以下ではｐ型のＳｉ基板２０Ａを用いた場合を例に説明するが、ｎ型のＳｉ基板であっても以下の構造を適用することができる。 In the following, a case where a p-type Si substrate 20A is used will be described as an example, but the following structure can be applied even to an n-type Si substrate.
　本実施形態のＥＳＤ保護デバイス１０は、所謂ＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）からなり、ｐ型に不純物添加されたＳｉ基板２０Ａを備える。当該ｐ型のＳｉ基板２０の一方面（図４の下面）の所定位置は、当該一方面から所定深さで所定の面積範囲がｎ型ドーピングされている。また、ｐ型のＳｉ基板２０Ａにおける特定の対となるｎ型ドーピング層ｎ＋（図４の左端付近の２個のｎ型ドーピング層ｎ＋）を囲むように、Ｐウェル層が形成されている。Ｐウェル層とは、Ｓｉ基板２０Ａの対してｐ型の不純物濃度を高くした層である。この構造により、ｐ型領域（Ｐウェル層）とｎ型領域との境界を、ダイオードやキャパシタとして機能させたり、ｎ型領域を抵抗器として機能させることができる。なお、Ｐウェル層は必ずしも形成しなければならないわけではないが、形成することが望ましい。 The ESD protection device 10 of this embodiment is made of a so-called CSP (Chip Size Package) and includes a Si substrate 20A doped with p-type impurities. A predetermined position of one surface (the lower surface in FIG. 4) of the p-type Si substrate 20 is n-type doped in a predetermined area range at a predetermined depth from the one surface. Further, a P well layer is formed so as to surround a specific pair of n type doping layer n + (two n type doping layers n + near the left end in FIG. 4) in the p type Si substrate 20A. The P well layer is a layer in which the p-type impurity concentration is increased with respect to the Si substrate 20A. With this structure, the boundary between the p-type region (P well layer) and the n-type region can function as a diode or a capacitor, or the n-type region can function as a resistor. The P well layer is not necessarily formed, but it is desirable to form it.
　このような部分的にｎ型ドーピングされたｐ型のＳｉ基板２０Ａの表面には、当該表面側からコンタクト層２００および導電性パターン２０１が順に形成されている。導電性パターン２０１は、例えばＡｌ（アルミニウム）等の金属材料の蒸着などによって実現される。 The contact layer 200 and the conductive pattern 201 are sequentially formed on the surface of the partially n-type doped p-type Si substrate 20A from the surface side. The conductive pattern 201 is realized by vapor deposition of a metal material such as Al (aluminum).
　これらコンタクト層２００および導電性パターン２０１は、所望とする回路構成を実現するようにパターン形成されている。 The contact layer 200 and the conductive pattern 201 are patterned so as to realize a desired circuit configuration.
　例えば、ＥＳＤ素子ＥＳＤ１を形成する領域のコンタクト層２００および導電性パターン２０１は、所定間隔で形成された２個のｎ型ドーピング層ｎ＋の各表面にパターン形成されている。これにより、この領域では、２個のダイオードを、順方向が不一致の状態で直列接続した回路構成を実現でき、ＥＳＤ素子ＥＳＤ１が実現される。 For example, the contact layer 200 and the conductive pattern 201 in the region where the ESD element ESD1 is formed are patterned on the surfaces of two n-type doping layers n + formed at a predetermined interval. Thereby, in this region, it is possible to realize a circuit configuration in which two diodes are connected in series in a state in which the forward directions do not match, and the ESD element ESD1 is realized.
　より具体的には、一方のｎ型ドーピング層ｎ＋とＰウェルとで、１個のｐｎ接合が実現され、他方のｎ型ドーピング層ｎ＋と当該Ｐウェルとで、もう１個のｐｎ接合が実現される。この際、２個のｎ型ドーピング層ｎ＋の間にＰウェルが介在する構造となるので、順方向が互いに逆となるように２つのダイオードが接続された回路と等価な構成となる。したがって、正と負に所定の閾値電圧を有するダイオードを実現でき、ＥＳＤ保護回路として機能させることができる。すなわち、閾値電圧Ｖｔを通常動作時の電圧よりも高く設定しておけば、通常時にはダイオードがＯＦＦ状態となり（ＯＮ状態にならず）、閾値電圧Ｖｔを超えるような静電気が重畳されると、ダイオードがＯＮ状態となり、グランドへエネルギーを放出するＥＳＤ保護回路として機能する。 More specifically, one pn junction is realized by one n-type doping layer n + and the P well, and another pn junction is realized by the other n-type doping layer n + and the P well. Is done. At this time, since the P-well is interposed between the two n-type doping layers n +, the structure is equivalent to a circuit in which two diodes are connected so that the forward directions are opposite to each other. Therefore, a diode having a predetermined threshold voltage positive and negative can be realized, and can function as an ESD protection circuit. That is, if the threshold voltage Vt is set higher than the voltage during normal operation, the diode is normally turned off (not turned on), and when static electricity exceeding the threshold voltage Vt is superimposed, the diode Becomes an ON state and functions as an ESD protection circuit that releases energy to the ground.
　また、抵抗器Ｒを形成する領域のコンタクト層２００および導電性パターン２０１は、ｎ型ドーピング層ｎ＋の離間した両端の２つの所定面積範囲にパターン形成されている。これにより、ｎ型ドーピング層ｎ＋の抵抗成分を利用した抵抗器Ｒが実現される。なお、本実施形態の説明では、ｎ型ドーピング層ｎ＋を用いて抵抗器Ｒを実現しているが、Ｓｉ基板２０Ａに対してＮウェルで囲まれたｐ型ドーピング層ｐ＋を形成し、当該ｐ型ドーピング層ｐ＋で、抵抗器Ｒを形成してもよい。 In addition, the contact layer 200 and the conductive pattern 201 in the region where the resistor R is formed are patterned in two predetermined area ranges on both ends of the n-type doping layer n +. Thereby, the resistor R using the resistance component of the n-type doping layer n + is realized. In the description of the present embodiment, the resistor R is realized by using the n-type doping layer n +, but the p-type doping layer p + surrounded by the N well is formed on the Si substrate 20A, and the p The resistor R may be formed of the type doping layer p +.
　また、さらに、インダクタＬｒを形成する領域のコンタクト層２００および導電性パターン２０１は、所定の巻回数でかつ所定の電極幅からなるスパイラル形状にパターン形成されている。これにより、Ｓｉ基板２０Ａ上に形成された第１スパイラル電極２１Ａが実現される。 Further, the contact layer 200 and the conductive pattern 201 in the region where the inductor Lr is formed are patterned in a spiral shape having a predetermined number of turns and a predetermined electrode width. Thereby, the first spiral electrode 21A formed on the Si substrate 20A is realized.
　このように所定パターンで形成されたコンタクト層２００、導電パターン２０１、および当該パターンが形成されていないＳｉ基板２０Ａの表面は、ＵＢＭ４０の形成領域を除いて、絶縁性のパッシべーション層２０Ｂｐで覆われている。そして、このパッシべーション層２０Ｂｐが開口した位置にＵＢＭ４０が形成されている。 The surface of the contact layer 200, the conductive pattern 201, and the Si substrate 20A on which the pattern is not formed is covered with the insulating passivation layer 20Bp except for the region where the UBM 40 is formed. It has been broken. And UBM40 is formed in the position which this passivation layer 20Bp opened.
　さらに、当該ＵＢＭ４０に接続するように所定パターンの導電性パターン２０２からなる再配線層が形成されている。これにより、ＵＢＭ４０は、Ｓｉ基板２０Ａ表面の導電性パターン２０１と、再配線層を構成する導電性パターン２０２とを電気的に接続するビアホールとして機能する。 Further, a rewiring layer made of a conductive pattern 202 having a predetermined pattern is formed so as to be connected to the UBM 40. Thereby, the UBM 40 functions as a via hole that electrically connects the conductive pattern 201 on the surface of the Si substrate 20A and the conductive pattern 202 constituting the rewiring layer.
　再配線層の導電性パターン２０２は、ＵＢＭ４０とＣＳＰとしての外部接続バンプである半田バンプ５０とを橋渡しする電極パターンと、第２スパイラル電極２１Ｂを形成する電極パターンとを有する。ここで、ＵＢＭ４０と半田バンプ５０とを橋渡しする電極パターンは、図４の左端付近に示すように、ＵＢＭ４０の形成位置から半田バンプ５０の形成位置まで所定パターンで延びるように形成されている。一方、第２スパイラル電極２１Ｂを形成する電極パターンは、当該ＥＳＤ保護デバイス１０すなわちＳｉ基板２０Ａを平面視して、Ｓｉ基板２０Ａ表面の第１スパイラル電極２１Ａを形成する電極パターンと同じ巻回方向で且つ略同じ形状からなり、重なり合う領域に形成されている。そして、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとは、ＵＢＭ４０からなるビアホールにより接続されている。これにより、第１スパイラル電極２１Ａと第２スパイラル電極２１ＢとからなるインダクタＬｒが実現される。 The conductive pattern 202 of the rewiring layer has an electrode pattern that bridges the UBM 40 and the solder bump 50 that is an external connection bump as a CSP, and an electrode pattern that forms the second spiral electrode 21B. Here, the electrode pattern that bridges the UBM 40 and the solder bump 50 is formed so as to extend in a predetermined pattern from the position where the UBM 40 is formed to the position where the solder bump 50 is formed, as shown in the vicinity of the left end of FIG. On the other hand, the electrode pattern that forms the second spiral electrode 21B has the same winding direction as the electrode pattern that forms the first spiral electrode 21A on the surface of the Si substrate 20A when the ESD protection device 10, that is, the Si substrate 20A is viewed in plan. Moreover, they have substantially the same shape and are formed in overlapping regions. The first spiral electrode 21A and the second spiral electrode 21B are connected by a via hole made of UBM40. Thereby, an inductor Lr composed of the first spiral electrode 21A and the second spiral electrode 21B is realized.
　このような再配線層の導電性パターン２０２は、Ｓｉ基板２０Ａ上の導電性パターン２０１よりも厚いＣｕ電極等の金属電極により形成される。これにより、第２スパイラル電極２１Ｂの抵抗成分を低くすることができる。 The conductive pattern 202 of the rewiring layer is formed of a metal electrode such as a Cu electrode that is thicker than the conductive pattern 201 on the Si substrate 20A. Thereby, the resistance component of the second spiral electrode 21B can be lowered.
　さらに、半田バンプ形成位置を除いて、再配線層の導電性パターン２０２およびパッシべーション層２０Ｂｐを覆うように、絶縁性の保護層２０Ｂｉが形成されている。この保護層２０Ｂｉは例えばポリイミドにより形成される。 Further, an insulating protective layer 20Bi is formed so as to cover the conductive pattern 202 and the passivation layer 20Bp of the rewiring layer except for the solder bump formation position. This protective layer 20Bi is formed of polyimide, for example.
　以上のように、ＥＳＤ素子ＥＳＤ１、抵抗器Ｒ、ＬＣ並列共振回路１のインダクタＬｒを形成し、さらに、ＥＳＤ素子ＥＳＤ２とＬＣ並列共振回路１のキャパシタＣｒとをＥＳＤ素子ＥＳＤ１と同様の構造で形成し、Ｓｉ基板２０Ａ表面の導電性パターン２０１、再配線層の導電性パターン２０２やＵＢＭ４０、半田バンプ５０を適宜パターン形成することで、本実施形態のＥＳＤ保護デバイス１０をＣＳＰにより実現することができる。 As described above, the ESD element ESD1, the resistor R, and the inductor Lr of the LC parallel resonant circuit 1 are formed, and the ESD element ESD2 and the capacitor Cr of the LC parallel resonant circuit 1 are formed in the same structure as the ESD element ESD1. Then, the ESD protection device 10 of this embodiment can be realized by CSP by appropriately patterning the conductive pattern 201 on the surface of the Si substrate 20A, the conductive pattern 202 of the rewiring layer, the UBM 40, and the solder bump 50. .
　次に、ＬＣ並列共振回路１のインダクタＬｒの構造について、図を参照して、より詳細に説明する。図５（Ａ）はインダクタＬｒの構造を模式的に示す外観斜視図であり、図５（Ｂ）はその分解斜視図である。また、図６（Ａ）は再配線層の第２スパイラル電極２１Ｂの平面図であり、図６（Ｂ）はその側面断面図である。また、図６（Ｃ）はＳｉ基板２０Ａ表面に形成された第１スパイラル電極２１Ａの平面図であり、図６（Ｄ）その側面断面図である。なお、図５、図６における絶縁性材料層２０Ｂは、上述の図４で示すパッシべーション層２０Ｂｐや保護層２０Ｂｉに相当するものであり、構造の説明を明確にするために基板状で表記している。 Next, the structure of the inductor Lr of the LC parallel resonant circuit 1 will be described in more detail with reference to the drawings. FIG. 5A is an external perspective view schematically showing the structure of the inductor Lr, and FIG. 5B is an exploded perspective view thereof. 6A is a plan view of the second spiral electrode 21B of the rewiring layer, and FIG. 6B is a side sectional view thereof. FIG. 6C is a plan view of the first spiral electrode 21A formed on the surface of the Si substrate 20A, and FIG. 6D is a side sectional view thereof. Note that the insulating material layer 20B in FIGS. 5 and 6 corresponds to the passivation layer 20Bp and the protective layer 20Bi shown in FIG. 4 described above, and is shown in the form of a substrate in order to clarify the structure. is doing.
　図５に示すように、ＬＣ並列共振回路１のインダクタＬｒは、Ｓｉ基板２０Ａ上に巻回形状で形成された導電性パターン２０１からなる第１スパイラル電極２１Ａと、当該第１スパイラル電極２１Ａから離間された位置に、同じく巻回形状で形成された導電性パターン２０２からなる第２スパイラル電極２１Ｂと、を備える。 As shown in FIG. 5, the inductor Lr of the LC parallel resonant circuit 1 includes a first spiral electrode 21A composed of a conductive pattern 201 formed in a wound shape on a Si substrate 20A, and a distance from the first spiral electrode 21A. The second spiral electrode 21 </ b> B made of the conductive pattern 202 that is also formed in a wound shape is provided at the position.
　この際、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとは、平面視した状態で略同じ領域に形成されている。また、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂのそれぞれの中央開口領域も略一致するように形成されている。 At this time, the first spiral electrode 21A and the second spiral electrode 21B are formed in substantially the same region in a plan view. The central opening regions of the first spiral electrode 21A and the second spiral electrode 21B are also formed so as to substantially coincide with each other.
　第１スパイラル電極２１Ａの外周端は、同じくＳｉ基板２０Ａ上に形成された導電性パターン２０１からなる引き回し電極３１に接続している。第１スパイラル電極２１Ａは、この外周端から内周端に亘り、徐々に径が短くなるように、且つ図６（Ｃ），（Ｄ）に示すように平面視した状態で反時計回りに巻回するように形成されている。第１スパイラル電極２１Ａの内周端は、図６（Ｂ）に示すように、ＵＢＭ４０からなるビアホール４１によって、第２スパイラル電極２１Ｂの内周端に接続している。 The outer peripheral end of the first spiral electrode 21A is connected to a lead-out electrode 31 made of the conductive pattern 201 that is also formed on the Si substrate 20A. The first spiral electrode 21A is wound counterclockwise so that the diameter gradually decreases from the outer peripheral end to the inner peripheral end and in a plan view as shown in FIGS. 6 (C) and 6 (D). It is formed to turn. As shown in FIG. 6B, the inner peripheral end of the first spiral electrode 21A is connected to the inner peripheral end of the second spiral electrode 21B by a via hole 41 made of UBM 40.
　第２スパイラル電極２１Ｂは、第１スパイラル電極２１Ａと略同じ電極幅を有する形状からなり、内周端から外周端に亘り、徐々に径が大きくなるように、且つ図６（Ａ），（Ｂ）に示すように平面視した状態で反時計回りに電極が巻回するように形成されている。第２スパイラル電極２１Ｂの外周端は、図５，図６（Ｂ）に示すように、導電性のビアホール４２により、Ｓｉ基板２０Ａ上の導電性パターン２０１からなる引き回し電極３２に接続している。 The second spiral electrode 21B has a shape having substantially the same electrode width as that of the first spiral electrode 21A, and gradually increases in diameter from the inner peripheral end to the outer peripheral end. ), The electrode is formed to be wound counterclockwise in a plan view. As shown in FIGS. 5 and 6B, the outer peripheral end of the second spiral electrode 21B is connected to the lead-out electrode 32 made of the conductive pattern 201 on the Si substrate 20A by a conductive via hole.
　このような構造とすることで、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとは、これらが接続されてなる二層構造のスパイラル電極として、巻回方向が一致するように形成される。これにより、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとで発生する磁界の向きが一致する。そして、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとの電極面同士が近接していることで、これらの磁界が結合し、強い磁気結合が得られ、大きな相互インダクタンスを生じることができる。この結果、第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとから構成されるインダクタＬｒのインダクタンスを大きく取ることができる。したがって、当該インダクタＬｒを用いたＬＣ並列共振回路１の共振のＱ値を高くでき、ＥＳＤ保護デバイスがローパスフィルタとして機能する際の減衰極を、急峻な特性の極にすることができる。よって、所望とする高周波ノイズを、効果的に除去することができる。 With such a structure, the first spiral electrode 21A and the second spiral electrode 21B are formed as a spiral electrode having a two-layer structure in which they are connected so that their winding directions coincide with each other. Thereby, the directions of the magnetic fields generated by the first spiral electrode 21A and the second spiral electrode 21B coincide. And since the electrode surfaces of the first spiral electrode 21A and the second spiral electrode 21B are close to each other, these magnetic fields are coupled, strong magnetic coupling is obtained, and a large mutual inductance can be generated. As a result, the inductance of the inductor Lr composed of the first spiral electrode 21A and the second spiral electrode 21B can be increased. Therefore, the Q value of resonance of the LC parallel resonant circuit 1 using the inductor Lr can be increased, and the attenuation pole when the ESD protection device functions as a low-pass filter can be a steep characteristic pole. Therefore, desired high frequency noise can be effectively removed.
　さらに、第２スパイラル電極２１Ｂは、再配線層の導電性パターン２０２を用いている。ここで、再配線層の導電性パターン２０２は、上述のようにＣｕ等から形成されている。Ｃｕは、Ｓｉ基板２０Ａ上に蒸着形成したＡｌより導電率が高いので、第２スパイラル電極２１Ｂの抵抗値を下げることができ、インダクタＬｒの全体を第１スパイラル電極２１Ａで形成するよりも、インダクタＬｒのインダクタンスを向上しながらも、抵抗成分の上昇を抑えることができる。また、再配線層の導電性パターン２０２は、Ｓｉ基板２０Ａ上に蒸着形成したＡｌ等からなる導電性パターン２０１と比較して、電極を厚く形成することができる。これにより、第２スパイラル電極２１Ｂの抵抗値をさらに下げることができ、インダクタＬｒの全体を第１スパイラル電極２１Ａで形成するよりも、インダクタＬｒのインダクタンスを向上しながらも、抵抗成分の上昇をより抑えることができる。これによっても、インダクタＬｒを備えるＬＣ並列共振回路１のＱ値を向上させることができ、より急峻な減衰極を形成することができる。 Furthermore, the second spiral electrode 21B uses the conductive pattern 202 of the rewiring layer. Here, the conductive pattern 202 of the rewiring layer is formed of Cu or the like as described above. Since Cu has a higher conductivity than Al deposited on the Si substrate 20A, the resistance value of the second spiral electrode 21B can be lowered, and the inductor Lr is formed by the first spiral electrode 21A rather than the entire inductor Lr. While increasing the inductance of Lr, it is possible to suppress an increase in resistance component. Further, the conductive pattern 202 of the rewiring layer can be formed thicker than the conductive pattern 201 made of Al or the like deposited on the Si substrate 20A. As a result, the resistance value of the second spiral electrode 21B can be further lowered, and the resistance component can be further increased while improving the inductance of the inductor Lr than when the entire inductor Lr is formed of the first spiral electrode 21A. Can be suppressed. Also by this, the Q value of the LC parallel resonant circuit 1 including the inductor Lr can be improved, and a steeper attenuation pole can be formed.
　図７はスパイラル電極の個数に応じた通過特性への影響を示す通過特性図である。図７において、太実線はＳｉ基板２０Ａ上の第１スパイラル電極２１ＡでインダクタＬｒを構成した場合のπ型ＥＳＤ保護回路１０Ｐの通過特性を示し、細実線はＳｉ基板２１Ａ上の第１スパイラル電極２１ＡでインダクタＬｒを構成した場合のＴ型ＥＳＤ保護回路１０Ｔの通過特性を示す。太破線はＳｉ基板２０Ａ上の第１スパイラル電極２１Ａと再配線層の第２スパイラル電極２１ＢとでインダクタＬｒを構成した場合のπ型ＥＳＤ保護回路１０Ｐの通過特性を示し、細破線はＳｉ基板２０Ａ上の第１スパイラル電極２１Ａと再配線層の第２スパイラル電極２１ＢとでインダクタＬｒを構成した場合のＴ型ＥＳＤ保護回路１０Ｔの通過特性を示す。 FIG. 7 is a pass characteristic diagram showing the influence on the pass characteristic according to the number of spiral electrodes. In FIG. 7, the thick solid line indicates the pass characteristic of the π-type ESD protection circuit 10P when the inductor Lr is configured by the first spiral electrode 21A on the Si substrate 20A, and the thin solid line indicates the first spiral electrode 21A on the Si substrate 21A. The pass characteristics of the T-type ESD protection circuit 10T when the inductor Lr is configured as shown in FIG. A thick broken line indicates a passing characteristic of the π-type ESD protection circuit 10P when the inductor Lr is configured by the first spiral electrode 21A on the Si substrate 20A and the second spiral electrode 21B of the rewiring layer, and the thin broken line indicates the Si substrate 20A. The pass characteristics of the T-type ESD protection circuit 10T when the inductor Lr is composed of the upper first spiral electrode 21A and the second spiral electrode 21B of the rewiring layer are shown.
　図７に示すように、Ｓｉ基板２０Ａ上に第１スパイラル電極２１Ａを形成しただけでも、減衰極を得られる。そして、さらに、上述の第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとの二層構造を用いることにより、さらに減衰極の減衰量を大きくし、急峻な特性にすることができる。 As shown in FIG. 7, the attenuation pole can be obtained only by forming the first spiral electrode 21A on the Si substrate 20A. Further, by using the above-described two-layer structure of the first spiral electrode 21A and the second spiral electrode 21B, the attenuation amount of the attenuation pole can be further increased and steep characteristics can be obtained.
　なお、図５、図６では、再配線層による第２スパイラル電極２１Ｂを１個設けた例を示したが、図８に示すように、再配線層をさらに増加させ、第２スパイラル電極２１Ｂに対してＳｉ基板２０Ａと反対側に、さらに第３スパイラル電極２１Ｃを形成してもよい。図８は、インダクタＬｒの他の構造を模式的に示す分解斜視図である。 5 and 6 show an example in which one second spiral electrode 21B is provided by a rewiring layer. However, as shown in FIG. 8, the number of rewiring layers is further increased, and the second spiral electrode 21B is formed on the second spiral electrode 21B. On the other hand, a third spiral electrode 21C may be further formed on the side opposite to the Si substrate 20A. FIG. 8 is an exploded perspective view schematically showing another structure of the inductor Lr.
　第１スパイラル電極２１Ａと第２スパイラル電極２１Ｂとは、上述の図５、図６に示した構成と同じであり、説明は省略する。 The first spiral electrode 21A and the second spiral electrode 21B are the same as those shown in FIGS. 5 and 6, and will not be described.
　第３スパイラル電極２１Ｃは、第１スパイラル電極２１Ａや第２スパイラル電極２１Ｂと略同じ電極幅で、略一致する領域に略同じ面積で形成されている。第３スパイラル電極２１Ｃの外周端は、第２スパイラル電極２１Ｂの外周端とビアホール４１’により接続している。第３スパイラル電極２１Ｃは、当該外周端から内周端に亘り、徐々に径が短くなるように、平面視した状態で反時計回りに巻回するように形成されている。すなわち、第３スパイラル電極２１Ｃは、第１スパイラル電極２１Ａおよび第２スパイラル電極２１Ｂと同じ巻回方向で形成されている。 The third spiral electrode 21C has substantially the same electrode width as that of the first spiral electrode 21A and the second spiral electrode 21B, and substantially the same area. The outer peripheral end of the third spiral electrode 21C is connected to the outer peripheral end of the second spiral electrode 21B by a via hole 41 '. The third spiral electrode 21C is formed to be wound counterclockwise in a plan view so that the diameter gradually decreases from the outer peripheral end to the inner peripheral end. That is, the third spiral electrode 21C is formed in the same winding direction as the first spiral electrode 21A and the second spiral electrode 21B.
　このような形状とすることで、インダクタＬｒとしての電極長をさらに伸延させて、インダクタンスを大きくすることができるとともに、第１スパイラル電極２１Ａ、第２スパイラル電極２１Ｂおよび第３スパイラル電極２１Ｃ間の相互インダクタンスにより、さらにインダクタＬｒとしてのインダクタンスを大きくすることができる。これにより、ＬＣ並列共振回路１のＱ値をさらに高くし、より急峻な減衰極を形成することができる。なお、形成する再配線層のスパイラル電極の数は、上述の１個および２個に限らず、製品仕様に応じて、３個以上にしてもよい。この際、上述のように、各スパイラル電極の巻回方向が一致するように、すなわちそれぞれの発生する磁界の向きが同じになり、各磁界が強め合うようにすることで、インダクタンスを大きくし、ＬＣ並列共振回路のＱ値を高めることができる。 With such a shape, the length of the electrode as the inductor Lr can be further extended to increase the inductance, and the mutual relationship between the first spiral electrode 21A, the second spiral electrode 21B, and the third spiral electrode 21C can be increased. By the inductance, the inductance as the inductor Lr can be further increased. Thereby, the Q value of the LC parallel resonance circuit 1 can be further increased, and a steeper attenuation pole can be formed. The number of spiral electrodes of the rewiring layer to be formed is not limited to one and two as described above, but may be three or more according to product specifications. At this time, as described above, the winding direction of each spiral electrode coincides, that is, the directions of the generated magnetic fields are the same, and the magnetic fields are strengthened to increase the inductance, The Q value of the LC parallel resonant circuit can be increased.
　以上のように、本実施形態の回路構成および構造を用いることで、ＥＳＤ保護機能が作動していない状態では所望の周波数に減衰極を有するローパスフィルタとして機能するＥＳＤ保護デバイスを実現することができる。すなわち、通過させたい周波数帯域の信号（通信信号）を低損失で伝搬させながら、所望の高周波ノイズを減衰させ、且つ静電気が信号ラインに重畳された場合に当該静電気をグランドへ放電させるＥＳＤ保護デバイスを実現することができる。この際、当該ＥＳＤ保護デバイスをＣＳＰにより実現することで、このような多機能で高性能なＥＳＤ保護デバイスを小型に形成することができる。 As described above, by using the circuit configuration and structure of the present embodiment, it is possible to realize an ESD protection device that functions as a low-pass filter having an attenuation pole at a desired frequency when the ESD protection function is not activated. . That is, an ESD protection device that attenuates desired high-frequency noise while discharging a signal (communication signal) in a frequency band to be passed with low loss, and discharges the static electricity to the ground when the static electricity is superimposed on the signal line. Can be realized. At this time, by realizing the ESD protection device by CSP, such a multifunctional and high-performance ESD protection device can be formed in a small size.
　なお、上述の説明では、Ｃ－Ｒ－ＬＣ－Ｒ型のローパスフィルタとして機能するπ型ＥＳＤ保護回路１０Ｐを例に説明した。しかしながら、次に示すような構成のＥＳＤ保護回路１１Ｐであってもよい。図９（Ａ）は本発明の構成からなるＥＳＤ保護回路１１Ｐの回路図であり、図９（Ｂ）はＥＳＤ保護回路１１ＰのＥＳＤ素子ＥＳＤ１，ＥＳＤ２，ＥＳＤ３がＯＦＦ状態での等価回路図である。 In the above description, the π-type ESD protection circuit 10P functioning as a CR-LC-R type low-pass filter has been described as an example. However, the ESD protection circuit 11P having the following configuration may be used. FIG. 9A is a circuit diagram of an ESD protection circuit 11P having the configuration of the present invention, and FIG. 9B is an equivalent circuit diagram when the ESD elements ESD1, ESD2, and ESD3 of the ESD protection circuit 11P are in an OFF state. .
　図９に示すＥＳＤ保護回路１１Ｐは、図１（Ａ）に示したＥＳＤ保護回路１０Ｐに対して、さらに、抵抗器ＲとＬＣ共振回路１との接続点がＥＳＤ素子ＥＳＤ３によりグランドに接続された構成を有する。このような構成とすることで、ＥＳＤ保護回路１１Ｐに、三個のローパスフィルタを構成することができる。具体的には、ＥＳＤ素子ＥＳＤ１，ＥＳＤ３および抵抗器Ｒから構成される第１フィルタ１Ａと、ＥＳＤ素子ＥＳＤ２，ＥＳＤ３およびＬＣ共振回路１のインダクタＬｒおよびキャパシタＣｒから構成される第２フィルタ１Ｂと、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２、抵抗器ＲおよびＬＣ共振回路１のインダクタＬｒおよびキャパシタＣｒから構成される第３フィルタ１Ｃとが構成される。 In the ESD protection circuit 11P shown in FIG. 9, the connection point between the resistor R and the LC resonance circuit 1 is further connected to the ground by the ESD element ESD3 with respect to the ESD protection circuit 10P shown in FIG. It has a configuration. With this configuration, three low-pass filters can be configured in the ESD protection circuit 11P. Specifically, a first filter 1A composed of ESD elements ESD1, ESD3 and a resistor R, a second filter 1B composed of ESD elements ESD2, ESD3 and an inductor Lr and a capacitor Cr of the LC resonance circuit 1, The ESD elements ESD1, ESD2, the resistor R, and the third filter 1C including the inductor Lr and the capacitor Cr of the LC resonance circuit 1 are configured.
　第１フィルタ１Ａは、抵抗器Ｒの両端がＥＳＤ素子ＥＳＤ１，ＥＳＤ３でそれぞれグランドへ接続された構成からなる。この回路は、ＥＳＤ素子ＥＳＤ１，ＥＳＤ３がＯＦＦ状態で、Ｃ－Ｒ－Ｃのπ型フィルタとなる。 The first filter 1A has a configuration in which both ends of the resistor R are connected to the ground by ESD elements ESD1 and ESD3, respectively. This circuit is a C—R—C π-type filter when the ESD elements ESD1 and ESD3 are OFF.
　第２フィルタ１Ｂは、インダクタＬｒとキャパシタＣｒの並列回路の両端がＥＳＤ２，ＥＳＤ３でそれぞれグランドへ接続された構成からなる。この回路は、ＥＳＤ素子ＥＳＤ２，ＥＳＤ３がＯＦＦ状態で、Ｃ－ＬＣ－Ｃのπ型フィルタとなる。 The second filter 1B has a configuration in which both ends of the parallel circuit of the inductor Lr and the capacitor Cr are connected to the ground by ESD2 and ESD3, respectively. This circuit is a C-LC-C π-type filter when the ESD elements ESD2 and ESD3 are OFF.
　第３フィルタ１Ｃは、抵抗器Ｒと、インダクタＬｒおよびキャパシタＣｒの並列回路とが直列接続された回路の両端が、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２でそれぞれグランドへ接続された構成からなる。この回路は、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２がＯＦＦ状態で、Ｃ－Ｒ－ＬＣ－Ｃのπ型フィルタとなる。 The third filter 1C has a configuration in which both ends of a circuit in which a resistor R and a parallel circuit of an inductor Lr and a capacitor Cr are connected in series are connected to the ground by ESD elements ESD1 and ESD2, respectively. This circuit is a CR-LC-C π-type filter when the ESD elements ESD1 and ESD2 are OFF.
　このように複数のローパスフィルタが含まれる構造とし、各素子の素子値を適宜設定することで、図１０に示すようにローパスの高域側に、さらに急峻な減衰極を形成することができる。図１０は、図１，図９の回路からなるＥＳＤ保護デバイスの通過特性を表す図である。このように、図９の構成を用いれば、より優れた高域の減衰特性を有するＥＳＤ保護デバイスを形成することができる。 As described above, by adopting a structure including a plurality of low-pass filters and appropriately setting the element value of each element, a steep attenuation pole can be formed on the high-pass side of the low-pass as shown in FIG. FIG. 10 is a diagram showing pass characteristics of an ESD protection device including the circuits of FIGS. As described above, by using the configuration of FIG. 9, an ESD protection device having a superior high-frequency attenuation characteristic can be formed.
　また、上述の図９の構成に対して、図１１に示すように、入力ポートＰｉ、出力ポートＰｏ間に直列接続される抵抗の構成を変化させてもよい。図１１は本発明のさらにその他の構成からなるＥＳＤ保護デバイスの回路図である。 Further, as shown in FIG. 11, the configuration of the resistor connected in series between the input port Pi and the output port Po may be changed from the configuration of FIG. 9 described above. FIG. 11 is a circuit diagram of an ESD protection device having still another configuration according to the present invention.
　図１１（Ａ）に示すＥＳＤ保護回路１２Ｐでは、ＥＳＤ素子ＥＳＤ３の一方端とＬＣ共振回路１との間に抵抗器Ｒｂが接続されている。図１１（Ｂ）に示すＥＳＤ保護回路１３Ｐでは、ＥＳＤ素子ＥＳＤ３の一方端とＥＳＤ素子ＥＳＤ２の一方端との間に抵抗器Ｒｂが接続されている。これらの場合、抵抗器Ｒｂを挿入することで、ＥＳＤ素子ＥＳＤ１とＥＳＤ素子ＥＳＤ３との間に接続された抵抗器Ｒａの抵抗値は適宜調整する。例えば、図１の抵抗器Ｒが抵抗値１００Ωであれば、抵抗器Ｒａを９０Ω、抵抗器Ｒｂを１０Ωに設定するとよい。 In the ESD protection circuit 12P shown in FIG. 11A, a resistor Rb is connected between one end of the ESD element ESD3 and the LC resonance circuit 1. In the ESD protection circuit 13P shown in FIG. 11B, a resistor Rb is connected between one end of the ESD element ESD3 and one end of the ESD element ESD2. In these cases, the resistance value of the resistor Ra connected between the ESD element ESD1 and the ESD element ESD3 is appropriately adjusted by inserting the resistor Rb. For example, if the resistor R in FIG. 1 has a resistance value of 100Ω, the resistor Ra may be set to 90Ω and the resistor Rb to 10Ω.
　このように、ＥＳＤ素子ＥＳＤ３の一方端（信号ライン側）に対して入力ポートＰｉ側、出力ポートＰｏ側にそれぞれ抵抗器Ｒａ，Ｒｂを挿入することで、入力ポートＰｉ、出力ポートＰｏのいずれのポートからのＥＳＤが入力されても、ＥＳＤ素子ＥＳＤ３に到達する前に、抵抗器Ｒａ，Ｒｂで或程度減衰される。したがって、減衰極の調整用として接続されたＥＳＤ素子ＥＳＤ３のキャパシタンスが小さい場合であっても、当該ＥＳＤ素子ＥＳＤ３の破壊を防ぐことができる。逆に言えば、他のＥＳＤ素子ＥＳＤ１，ＥＳＤ２とは異なる構成で減衰極の調整用のキャパシタを形成せず、ＥＳＤ素子ＥＳＤ１，ＥＳＤ２と同じような構成でＥＳＤ素子ＥＳＤ３を形成しても、当該ＥＳＤ素子ＥＳＤ３の破壊を防止できる。これにより、優れた減衰特性で高信頼性のＥＳＤ保護デバイスを実現できる。 In this way, by inserting the resistors Ra and Rb on the input port Pi side and the output port Po side with respect to one end (signal line side) of the ESD element ESD3, either of the input port Pi and the output port Po is selected. Even if ESD from the port is input, it is attenuated to some extent by the resistors Ra and Rb before reaching the ESD element ESD3. Therefore, even if the capacitance of the ESD element ESD3 connected for adjusting the attenuation pole is small, the ESD element ESD3 can be prevented from being destroyed. In other words, even if the ESD element ESD3 is formed in the same configuration as the ESD elements ESD1 and ESD2 without forming the capacitor for adjusting the attenuation pole in a different configuration from the other ESD elements ESD1 and ESD2, The destruction of the ESD element ESD3 can be prevented. Thereby, a highly reliable ESD protection device with excellent attenuation characteristics can be realized.
　ところで、上述したように、ＥＳＤ素子ＥＳＤ３は、単にキャパシタで構成してもよい。この場合、当該キャパシタは、Ｓｉ基板の表面の電極パターンと再配線層の電極パターンにより形成すればよい。これにより、簡素な構成で減衰極調整用のキャパシタを形成することができる。さらに、このようなキャパシタの一方の対向電極に、Ｓｉ基板上に形成したインダクタＬｒの電極パターンを利用し、他方の対向電極を再配線層に形成することで、Ｓｉ基板上に形成したインダクタＬｒを再配線層に接続するための接続電極（導電性ビアホール等）を形成する必要がなくなる。これにより、さらに簡素な構成で、ＥＳＤ保護デバイスを実現することができる。 By the way, as described above, the ESD element ESD3 may be simply constituted by a capacitor. In this case, the capacitor may be formed by an electrode pattern on the surface of the Si substrate and an electrode pattern on the rewiring layer. Thereby, a capacitor for adjusting the attenuation pole can be formed with a simple configuration. Further, the inductor Lr formed on the Si substrate is formed by using the electrode pattern of the inductor Lr formed on the Si substrate as one counter electrode of the capacitor and forming the other counter electrode on the rewiring layer. There is no need to form a connection electrode (such as a conductive via hole) for connecting to the rewiring layer. Thereby, an ESD protection device can be realized with a simpler configuration.
　なお、上述の説明では、スパイラル電極を用いた例を示したが、ＬＣ並列共振回路のインダクタＬｒとして、ミアンダ電極を用いることもできる。 In the above description, an example using a spiral electrode has been shown, but a meander electrode can also be used as the inductor Lr of the LC parallel resonant circuit.
　また、上述の説明では、再配線層を用いてＬＣ並列共振回路のインダクタＬｒを形成したが、Ｓｉ基板上の導電性パターンのみによって、インダクタＬｒを形成してもよい。 In the above description, the inductor Lr of the LC parallel resonant circuit is formed using the rewiring layer. However, the inductor Lr may be formed only by the conductive pattern on the Si substrate.
　また、再配線層を用いてＬＣ並列共振回路のインダクタＬｒを形成する場合であっても、２つのスパイラル電極が必ずしも同一形状、同一領域、同一方向に巻回するように形成されなくてもよい。 Further, even when the inductor Lr of the LC parallel resonant circuit is formed using the rewiring layer, the two spiral electrodes do not necessarily have to be formed in the same shape, the same region, and the same direction. .
　また、上述の説明では、ＥＳＤ素子は、ダイオードの直列回路で実現する例を示したが、Ｓｉ基板を用いる場合であればツェナーダイオードやＦＥＴを用いてもよく、バリスタを用いてもよい。また、ＥＳＤ保護デバイスを、Ｓｉ基板を用いたＣＳＰで実現する例を示したが、樹脂系の積層基板と当該積層基板に形成されたパターン電極と実装部品とから、上述のＥＳＤ保護回路を構成してもよい。 In the above description, an example in which the ESD element is realized by a series circuit of diodes has been shown. However, if a Si substrate is used, a Zener diode or FET may be used, or a varistor may be used. Moreover, although the example which implement | achieves an ESD protection device by CSP using Si substrate was shown, the above-mentioned ESD protection circuit is comprised from the resin-type laminated substrate, the pattern electrode formed in the said laminated substrate, and mounting components. May be.
１－ＬＣ並列共振回路、１０－ＥＳＤ保護デバイス、１０Ｐ，１０Ｐ’，１１Ｐ，１２Ｐ，１３Ｐ－π型ＥＳＤ保護回路、１０Ｔ，１０Ｔ’－Ｔ型ＥＳＤ保護回路、２０Ａ－Ｓｉ基板、２０Ｂ－絶縁性材料層、２０Ｂｐ－パッシべーション層、２０Ｂｉ－保護層、２１Ａ－第１スパイラル電極、２１Ｂ－第２スパイラル電極、２１Ｃ－第３スパイラル電極、３１，３２－引き回し電極、４０－ＵＢＭ、４１，４１’，４２－ビアホール、５０－半田バンプ、２００－コンタクト層、２０１－導電性パターン、２０２－導電性パターン 1-LC parallel resonant circuit, 10-ESD protection device, 10P, 10P ′, 11P, 12P, 13P-π type ESD protection circuit, 10T, 10T′-T type ESD protection circuit, 20A-Si substrate, 20B-insulating Material layer, 20Bp-passivation layer, 20Bi-protective layer, 21A-first spiral electrode, 21B-second spiral electrode, 21C-third spiral electrode, 31,32-leading electrode, 40-UBM, 41,41 ', 42-via hole, 50-solder bump, 200-contact layer, 201-conductive pattern, 202-conductive pattern

Claims (15)

  1. 　信号ラインに挿入された抵抗器と、
    　該抵抗器の両端とグランドとをそれぞれに接続する２個のＥＳＤ素子と、
    　前記信号ライン上において前記抵抗器に直列接続されたＬＣ並列共振器と、
    　を備えたＥＳＤ保護デバイス。     A resistor inserted in the signal line;
    Two ESD elements connecting both ends of the resistor and the ground, respectively;
    An LC parallel resonator connected in series with the resistor on the signal line;
    ESD protection device.
  2. 　請求項１に記載のＥＳＤ保護デバイスであって、
    　前記ＬＣ並列共振器は、
    　前記信号ラインにおける前記抵抗器の一方端と該一方端に接続する前記ＥＳＤ素子との間に接続されている、ＥＳＤ保護デバイス。     The ESD protection device according to claim 1,
    The LC parallel resonator is
    An ESD protection device connected between one end of the resistor in the signal line and the ESD element connected to the one end.
  3. 　信号ラインに挿入され、互いに直列接続された２個の抵抗器と、
    　該直列接続された２個の抵抗器の接続点とグランドとを接続するＥＳＤ素子と、
    　前記抵抗器のいずれか一方と前記接続点との間の信号ラインに直列接続されたＬＣ並列共振器と、
    　を備えたＥＳＤ保護デバイス。     Two resistors inserted in the signal line and connected in series with each other;
    An ESD element for connecting the connection point of the two resistors connected in series and the ground;
    An LC parallel resonator connected in series to a signal line between any one of the resistors and the connection point;
    ESD protection device.
  4. 　請求項１乃至請求項３のいずれかに記載のＥＳＤ保護デバイスであって、
    　前記ＬＣ並列共振器を構成するインダクタは、
    　前記信号ラインが形成されるシリコン基板上に形成された導電性パターンからなる、ＥＳＤ保護デバイス。     The ESD protection device according to any one of claims 1 to 3,
    The inductor constituting the LC parallel resonator is:
    An ESD protection device comprising a conductive pattern formed on a silicon substrate on which the signal line is formed.
  5. 　請求項４に記載のＥＳＤ保護デバイスであって、
    　前記インダクタは、
    　前記シリコン基板上に形成された導電性パターンに対して離間された再配線層の導電性パターンと、
    　該再配線層の導電性パターンと、前記シリコン基板上の導電性パターンとを導通するビアホールと、をさらに備えるＥＳＤ保護デバイス。     The ESD protection device according to claim 4,
    The inductor is
    A conductive pattern of a redistribution layer spaced from a conductive pattern formed on the silicon substrate;
    An ESD protection device further comprising: a conductive pattern of the rewiring layer; and a via hole that conducts the conductive pattern on the silicon substrate.
  6. 　請求項５に記載のＥＳＤ保護デバイスであって、
    　前記インダクタは、
    　さらなる少なくとも１つの前記再配線層の導電性パターンと、
    　各再配線層の導電性パターン同士を接続するビアホールとを、さらに備えるＥＳＤ保護デバイス。     The ESD protection device according to claim 5,
    The inductor is
    A further at least one conductive pattern of the redistribution layer;
    An ESD protection device further comprising a via hole connecting the conductive patterns of each redistribution layer.
  7. 　請求項５または請求項６のいずれかに記載のＥＳＤ保護デバイスであって、
    　前記再配線層の導電性パターンは、前記シリコン基板上の導電性パターンよりも電極厚みが厚い、ＥＳＤ保護デバイス。     An ESD protection device according to claim 5 or claim 6,
    The ESD protection device, wherein the conductive pattern of the redistribution layer has a larger electrode thickness than the conductive pattern on the silicon substrate.
  8. 　請求項５乃至請求項７のいずれかに記載のＥＳＤ保護デバイスであって、
    　前記再配線層の導電性パターンは、前記シリコン基板上の導電性パターンよりも導電率が高い材料で形成されている、ＥＳＤ保護デバイス。     An ESD protection device according to any one of claims 5 to 7,
    The ESD protection device, wherein the conductive pattern of the redistribution layer is formed of a material having higher conductivity than the conductive pattern on the silicon substrate.
  9. 　請求項４乃至請求項８のいずれかに記載のＥＳＤ保護デバイスであって、
    　前記シリコン基板上の導電性パターンは、スパイラル電極からなるＥＳＤ保護デバイス。     An ESD protection device according to any one of claims 4 to 8,
    The conductive pattern on the silicon substrate is an ESD protection device comprising a spiral electrode.
  10. 　請求項５乃至請求項８のいずれかに記載のＥＳＤ保護デバイスであって、
    　前記シリコン基板上の導電性パターンと前記再配線層の導電性パターンは、略同一形状で、且つ、同一領域で、前記シリコン基板を平面視した状態で同一方向に巻回するスパイラル電極からなるＥＳＤ保護デバイス。     An ESD protection device according to any one of claims 5 to 8,
    The conductive pattern on the silicon substrate and the conductive pattern on the rewiring layer have substantially the same shape, and are ESDs comprising spiral electrodes that are wound in the same direction in the same region in a plan view of the silicon substrate. Protective device.
  11. 　請求項２に記載のＥＳＤ保護デバイスであって、
    　前記抵抗器と前記ＬＣ並列共振器との間の信号ラインに一方端が接続し、他方端がグランドへ接続するキャパシタをさらに備えたＥＳＤ保護デバイス。     An ESD protection device according to claim 2,
    An ESD protection device further comprising a capacitor having one end connected to a signal line between the resistor and the LC parallel resonator and the other end connected to the ground.
  12. 　請求項１１に記載のＥＳＤ保護デバイスであって、
    　前記キャパシタは、前記２個のＥＳＤ素子とは異なる第３のＥＳＤ素子からなる、ＥＳＤ保護デバイス。     An ESD protection device according to claim 11, comprising:
    The capacitor is an ESD protection device including a third ESD element different from the two ESD elements.
  13. 　請求項１２に記載のＥＳＤ保護デバイスであって、
    　前記抵抗器は２個の部分抵抗器からなり、該２個の部分抵抗器は前記第３のＥＳＤ素子の一方端から前記２個のＥＳＤ素子に向かうそれぞれの信号ライン上に個別に接続されている、ＥＳＤ保護デバイス。     An ESD protection device according to claim 12, comprising:
    The resistors are composed of two partial resistors, and the two partial resistors are individually connected on respective signal lines from one end of the third ESD element to the two ESD elements. An ESD protection device.
  14. 　請求項１１に記載のＥＳＤ保護デバイスであって、
    　前記キャパシタは、
    　前記信号ラインが形成されるシリコン基板上に形成された導電性パターンと、前記シリコン基板上に形成された導電性パターンに対して離間された再配線層の導電性パターンと、から構成される、ＥＳＤ保護デバイス。     An ESD protection device according to claim 11, comprising:
    The capacitor is
    A conductive pattern formed on a silicon substrate on which the signal line is formed; and a conductive pattern on a redistribution layer spaced from the conductive pattern formed on the silicon substrate. ESD protection device.
  15. 　請求項１４に記載のＥＳＤ保護デバイスであって、
    　前記キャパシタを形成する前記シリコン基板上に形成された導電性パターンは、前記ＬＣ並列共振器のインダクタを構成する導電性パターンを兼ねる、ＥＳＤ保護デバイス。     An ESD protection device according to claim 14, comprising:
    The ESD protection device, wherein a conductive pattern formed on the silicon substrate forming the capacitor also serves as a conductive pattern constituting an inductor of the LC parallel resonator.
PCT/JP2010/057859 2009-08-21 2010-05-10 Esd protection device WO2011021411A1 (en)

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