JP7020280B2 - Latch-up prevention circuit - Google Patents

Description

The present invention relates to a latch-up prevention circuit.

In recent years, in various electronic circuit devices, there is a demand for low voltage drive and high density of semiconductor integrated circuits (ICs) constituting these electronic circuit devices due to demands for power saving and miniaturization. On the other hand, with the introduction of MOS (Metal Oxide Semiconductor) transistors that make up analog circuits, ICs that have both analog and digital circuits are becoming more widespread. In an IC in which such an analog circuit and a digital circuit are mixedly mounted, there is a configuration using a power supply voltage for an analog circuit and a power supply for a digital circuit having a lower voltage than the power supply for the analog circuit from the viewpoint of noise resistance and the like. ..

Generally, in an IC having a CMOS (Complementary MOS) configuration that requires a plurality of power supply voltages, the absolute maximum voltage of the voltage between power supply terminals is specified. In such an IC, when a potential difference exceeding the absolute maximum voltage is applied, a so-called latch-up phenomenon may occur and a short circuit may occur between the IC and the reference potential (for example, the GND potential), causing element destruction. For example, a power supply device including a voltage step-down means for stepping down the output voltage of a high-voltage power supply to the output voltage of a low-voltage power supply is disclosed. (For example, Patent Document 1).

Japanese Unexamined Patent Publication No. 7-191622

However, in the above-mentioned conventional technique, when noise such as accidental ESD (Electrostatic Discharge) or surge is superimposed on the power supply line, the voltage between the power supply terminals deviates from the specification of the absolute maximum voltage, and the latch-up phenomenon occurs. It can occur. Further, in a configuration in which a power supply device is shared by a plurality of ICs, the configuration of the voltage step-down means may be complicated.

The present invention has been made in view of the above problems, and provides a latch-up prevention circuit capable of suppressing the occurrence of a latch-up phenomenon in a configuration having a plurality of power supply terminals to which different power supply voltages are applied. The purpose is to do.

In order to achieve the above object, the latch-up prevention circuit according to one aspect of the present invention has a first power supply voltage having a predetermined potential difference with respect to a reference potential, and a second power supply voltage lower than the first power supply voltage. An IC latch-up prevention circuit that operates by supplying a power supply voltage, wherein a cathode is connected to a first power supply terminal of the IC to which the first power supply voltage is applied, and the second power supply voltage is applied. The IC includes a first diode having an anode connected to the second power supply terminal of the IC, and the IC has a voltage applied to the first power supply terminal as V1 and a voltage applied to the second power supply terminal as V2. When, the following equation (1) is defined as the absolute maximum rating of the voltage between the first power supply terminal and the second power supply terminal, and the first diode is described below when the forward voltage is VF. (2) Satisfies.

V2 ≤ V1 + α ... (1)

VF <α ... (2)

According to the above configuration, noise such as ESD and surge can be suppressed, and the occurrence of a latch-up phenomenon due to noise such as ESD and surge can be suppressed.

As a desirable embodiment of the latch-up prevention circuit, it is preferable that a plurality of the first diodes are provided in parallel.

As a result, it is possible to obtain a noise suppression effect according to the magnitude of the forward current flowing due to noise such as ESD and surge.

As a desirable embodiment of the latch-up prevention circuit, the first diode is preferably a Schottky barrier diode.

This makes it possible to effectively suppress steep noise such as ESD and surge.

As a desirable embodiment of the latch-up prevention circuit, it is preferable to include a second diode having a cathode connected to the second power supply terminal and an anode connected to the reference potential.

As a result, the absolute voltage value of the negative electrode noise superimposed on the second power supply voltage is suppressed.

As a desirable embodiment of the latch-up prevention circuit, the second diode is preferably a Schottky barrier diode.

As a result, the steep negative electrode noise superimposed on the second power supply voltage can be effectively suppressed.

As a preferred embodiment of the latch-up prevention circuit, the second diode is preferably a Zener diode.

As a result, the absolute voltage value of the positive electrode noise superimposed on the second power supply voltage is suppressed.

As a preferred embodiment of the latch-up prevention circuit, it is preferable to include a third diode having a cathode connected to the first power supply terminal and an anode connected to the reference potential.

As a result, the absolute voltage value of the negative electrode noise superimposed on the first power supply voltage is suppressed.

As a desirable embodiment of the latch-up prevention circuit, the third diode is preferably a Schottky barrier diode.

As a result, the steep negative electrode noise superimposed on the first power supply voltage can be effectively suppressed.

As a desirable embodiment of the latch-up prevention circuit, the third diode is preferably a Zener diode.

As a result, the absolute voltage value of the positive electrode noise superimposed on the first power supply voltage is suppressed.

According to the present invention, it is possible to provide a latch-up prevention circuit capable of suppressing the occurrence of a latch-up phenomenon in a configuration having a plurality of power supply terminals to which different power supply voltages are applied.

FIG. 1 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the first embodiment is applied. FIG. 2 is a diagram showing an example of the configuration according to the comparative example. FIG. 3 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the modified example of the first embodiment is applied. FIG. 4 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the second embodiment is applied. FIG. 5 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the modified example of the second embodiment is applied. FIG. 6 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the third embodiment is applied. FIG. 7 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the modified example of the third embodiment is applied.

Hereinafter, embodiments for carrying out the invention (hereinafter referred to as embodiments) will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments. Further, the components in the following embodiments include those that can be easily assumed by those skilled in the art, those that are substantially the same, and those that are in a so-called equal range. Further, the components disclosed in the following embodiments can be appropriately combined.

(Embodiment 1)
FIG. 1 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the first embodiment is applied. The IC 2 to be protected by the latch-up prevention circuit 1 according to the present embodiment has a plurality of power supply voltages (first power supply voltage Vdd1 and second power supply voltage Vdd2 in the example shown in FIG. 2) from the power supply circuit (not shown). It is a semiconductor integrated circuit that operates by being applied. This IC2 is composed of, for example, CMOS (Complementary MOS). The present disclosure is not limited by the configuration of IC2.

The IC 2 has a first power supply terminal 21, a second power supply terminal 22, and a reference potential terminal 23. A first power supply voltage Vdd1 having a predetermined potential difference with respect to the reference potential GND is applied to the first power supply terminal 21. A second power supply voltage Vdd2, which is lower than the first power supply voltage Vdd1, is applied to the second power supply terminal 22. A reference potential GND is applied to the reference potential terminal 23. The reference potential is not limited to the GND potential. Further, in FIG. 1, an example in which one each of the first power supply terminal 21, the second power supply terminal 22, and the reference potential terminal 23 is shown, but these first power supply terminal 21, the second power supply terminal 22, and the reference potential are shown. The number of terminals 23 is not limited to this.

The first power supply voltage Vdd1 is, for example, a 5V positive power supply voltage supplied to the analog circuit constituting the IC2. Further, the second power supply voltage Vdd2 is, for example, a 3.3V positive power supply voltage supplied to the digital circuit constituting the IC2. The first power supply voltage Vdd1 and the second power supply voltage Vdd2 are not limited to the above.

Here, the voltage applied to the first power supply terminal 21 is V1, and the voltage applied to the second power supply terminal 22 is V2. At this time, in the present embodiment, the IC 2 has the following (1) as the absolute maximum rating of the voltage between the first power supply terminal 21 and the second power supply terminal 22 (hereinafter, also referred to as “voltage between power supply terminals”). The formula is specified. α is a value defined by the absolute maximum rating of the IC2 to be protected.

V2 ≤ V1 + α ... (1)

The latch-up prevention circuit 1 according to the present embodiment includes a diode 11 (first diode) in which a cathode is connected to a first power supply terminal 21 and an anode is connected to a second power supply terminal 22.

When a forward current flows through the diode 11, assuming that the forward voltage of the diode 11 is VF, the voltage V2 applied to the second power supply terminal 22 is expressed by the following equation (2).

V2 = V1 + VF ... (2)

That is, in order to satisfy the above equation (1), the forward voltage VF of the diode 11 needs to satisfy the following equation (3).

VF <α ... (3)

FIG. 2 is a diagram showing an example of the configuration according to the comparative example. In FIG. 2, a configuration in which Zener diodes 14 and 15 are provided between the first power supply terminal 21 and the reference potential terminal 23 and between the second power supply terminal 22 and the reference potential terminal 23 (reference potential), respectively. Shows.

When protecting the IC2 from external noise such as accidental ESD (Electrostatic Discharge) and surge, as shown in FIG. 2, each power supply terminal (in the example shown in FIG. 2, the first power supply terminal 21 and the second) Generally, Zener diodes 14 and 15 are provided between the power supply terminal 22) and the reference potential terminal 23 (reference potential), respectively. When a plurality of Zener diodes 14 and 15 (first power supply terminal 21, second power supply terminal 22) exist, it is necessary to provide one Zener diode 14 and 15 corresponding to each power supply terminal.

The Zener voltage (decay voltage) of the Zener diode has a variation error of generally about several percent, and is set corresponding to the absolute maximum rating of the input voltage of each power supply terminal (first power supply terminal 21, second power supply terminal 22). To. Therefore, the absolute maximum rating of the voltage between the power supply terminals of the above equation (1) is not always satisfied, and a latch-up phenomenon may occur, causing element destruction.

In the latch-up prevention circuit 1 according to the present embodiment, noise such as ESD and surge is provided by providing at least one diode 11 satisfying the above equation (3) between the first power supply voltage Vdd1 and the second power supply voltage Vdd2. Is suppressed. As a result, it is possible to suppress the occurrence of the latch-up phenomenon due to noise such as ESD and surge, and it is possible to prevent the element destruction of the IC2 in advance.

Further, in the above equations (1) and (3), when α is, for example, 0.3V, the forward voltage VF of the diode 11 needs to be less than 0.3V from the equation (3). In this case, it is desirable that the diode 11 is, for example, a Schottky barrier diode having a small forward voltage VF.

By using a switching Schottky barrier diode as the diode 11, steep noise such as ESD and surge can be effectively suppressed.

FIG. 3 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the modified example of the first embodiment is applied.

In the latch-up prevention circuit 1a according to the modification of the first embodiment shown in FIG. 3, a plurality of diodes 11 are provided in parallel between the first power supply voltage Vdd1 and the second power supply voltage Vdd2.

In the latch-up prevention circuit 1 according to the first embodiment shown in FIG. 1, when the forward current flowing due to noise such as ESD or surge increases, the forward voltage VF increases accordingly. In such a case, as shown in FIG. 3, a plurality of diodes 11 are provided in parallel between the first power supply voltage Vdd1 and the second power supply voltage Vdd2 to form the above equation (3). You may try to meet.

As described above, in the latch-up prevention circuit 1 according to the first embodiment, the cathode is connected to the first power supply terminal 21 to which the first power supply voltage Vdd1 is applied in the IC2 to be protected, and the second power supply voltage Vdd2 is applied. A diode 11 (first diode) having an anode connected to the second power supply terminal 22 is included. The diode 11 satisfies the absolute maximum rating of the voltage between the voltage V1 applied to the first power supply terminal 21 and the voltage V2 applied to the second power supply terminal 22.

With the above configuration, it is possible to suppress the occurrence of the latch-up phenomenon due to noise such as ESD and surge, and it is possible to prevent the element destruction of the IC2 in advance.

(Embodiment 2)
FIG. 4 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the second embodiment is applied. The same components as those described in the first embodiment are designated by the same reference numerals, and duplicate description will be omitted.

In the configuration according to the first embodiment, when noise such as negative ESD or surge (hereinafter, also simply referred to as “negative noise”) is superimposed on the second power supply voltage Vdd2, the absolute voltage value of the negative noise becomes the diode 11. There is a possibility that the diode 11 will be destroyed by exceeding the withstand voltage of the reverse voltage VR. When the diode 11 is short-circuited and broken, the first power supply voltage Vdd1 having a voltage value higher than that of the second power supply voltage Vdd2 is applied to the second power supply terminal 22, which causes secondary destruction of the IC2 and the power supply circuit (not shown). obtain.

In the latch-up prevention circuit 1b according to the present embodiment, as shown in FIG. 4, in addition to the diode 11, a diode having a cathode connected to a second power supply terminal 22 and an anode connected to a reference potential terminal 23 (reference potential). A configuration in which 12 (second diode) is provided is shown. In such a configuration, when the negative electrode noise is superimposed on the second power supply voltage Vdd2, a forward current flows through the diode 12, and the absolute voltage value of the negative electrode noise is suppressed. This makes it possible to prevent the destruction of the diode 11 and the secondary destruction of the IC2 and the like.

Further, by providing the diode 12, it works effectively even when the negative electrode noise is superimposed on the first power supply voltage Vdd1. That is, when the negative electrode noise is superimposed on the first power supply voltage Vdd1, a forward current flows through the diode 11 and the diode 12, and the absolute voltage value of the negative electrode noise is suppressed.

As the diode 12, for example, by using a switching Schottky barrier diode as in the diode 11, it is possible to effectively suppress steep negative electrode noise.

Further, as the diode 12, for example, a Zener diode may be used. As a result, even when noise such as positive ESD or surge (hereinafter, also simply referred to as “positive electrode noise”) is superimposed on the second power supply voltage Vdd2, it works effectively. That is, when positive noise is superimposed on the second power supply voltage Vdd2, a Zener current flows through the diode 12 (Zener diode), and the absolute voltage value of the positive noise is suppressed.

FIG. 5 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the modified example of the second embodiment is applied.

In the latch-up prevention circuit 1c according to the modified example of the second embodiment shown in FIG. 5, there are a plurality of latch-up prevention circuits 1c between the first power supply voltage Vdd1 and the second power supply voltage Vdd2 as in the modified example of the first embodiment shown in FIG. The configuration is such that the diodes 11 are provided in parallel. With such a configuration, the above equation (3) may be satisfied as in the modification of the first embodiment.

(Embodiment 3)
FIG. 6 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the third embodiment is applied. The same components as those described in the above-described first and second embodiments are designated by the same reference numerals, and duplicated description will be omitted.

In the configuration according to the second embodiment, when the negative voltage is superimposed on the first power supply voltage Vdd1, a forward current flows through the diode 11 and the diode 12, and the absolute voltage value of the negative noise is suppressed, but the diode 11 and the diode are suppressed. Twelve forward voltage drops will occur.

In the latch-up prevention circuit 1d according to the present embodiment, as shown in FIG. 6, in addition to the diode 11 and the diode 12, the cathode is connected to the first power supply terminal 21, and the anode is connected to the reference potential terminal 23 (reference potential). The configuration in which the diode 13 (third diode) is provided is shown. In such a configuration, when the negative electrode noise is superimposed on the first power supply voltage Vdd1, a forward current flows through the diode 13 and the absolute voltage value of the negative electrode noise is suppressed. As a result, the effect of suppressing negative noise can be enhanced.

As the diode 13, for example, by using a switching Schottky barrier diode as in the diode 12, it is possible to effectively suppress steep negative electrode noise.

Further, as the diode 13, for example, a Zener diode may be used as in the diode 12. As a result, even when positive noise is superimposed on the first power supply voltage Vdd1, it works effectively. That is, when positive noise is superimposed on the first power supply voltage Vdd1, a Zener current flows through the diode 13 (Zener diode), and the absolute voltage value of the positive noise is suppressed.

FIG. 7 is a diagram showing an example of a configuration to which the latch-up prevention circuit according to the modified example of the third embodiment is applied.

In the latch-up prevention circuit 1e according to the modified example of the third embodiment shown in FIG. 7, between the first power supply voltage Vdd1 and the second power supply voltage Vdd2 as in the modified example of the first embodiment and the modified example of the second embodiment. A plurality of diodes 11 are provided in parallel. With such a configuration, the above equation (3) may be satisfied as in the modified example of the first embodiment and the modified example of the second embodiment.

1,1a, 1b, 1c, 1d, 1e Latch-up prevention circuit 2 IC
11 Diode (first diode)
12 diode (second diode)
13 Diode (third diode)
14,15 Zener diode 21 1st power supply terminal 22 2nd power supply terminal 23 Reference potential terminal

Claims (9)

An IC latch-up prevention circuit that operates by supplying a first power supply voltage having a predetermined potential difference with respect to a reference potential and a second power supply voltage lower than the first power supply voltage.
A first diode having a cathode connected to a first power supply terminal of the IC to which the first power supply voltage is applied and an anode connected to a second power supply terminal of the IC to which the second power supply voltage is applied is included. ,
The IC is the voltage between the first power supply terminal and the second power supply terminal when the voltage applied to the first power supply terminal is V1 and the voltage applied to the second power supply terminal is V2. The following formula (1) is specified as the absolute maximum rating.
The first diode is a latch-up prevention circuit that satisfies the following equation (2) when the forward voltage is VF.
V2 ≤ V1 + α ... (1)
VF <α ... (2) The latch-up prevention circuit according to claim 1, wherein a plurality of the first diodes are provided in parallel. The latch-up prevention circuit according to claim 1 or 2, wherein the first diode is a Schottky barrier diode. The latch-up prevention circuit according to any one of claims 1 to 3, further comprising a second diode having a cathode connected to the second power supply terminal and an anode connected to the reference potential. The latch-up prevention circuit according to claim 4, wherein the second diode is a Schottky barrier diode. The latch-up prevention circuit according to claim 4, wherein the second diode is a Zener diode. The latch-up prevention circuit according to any one of claims 1 to 6, comprising a third diode having a cathode connected to the first power supply terminal and an anode connected to the reference potential. The latch-up prevention circuit according to claim 7, wherein the third diode is a Schottky barrier diode. The latch-up prevention circuit according to claim 7, wherein the third diode is a Zener diode.

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