TWI619106B - Power voltage synchronization circuit and display apparatus - Google Patents

Abstract

Power supply voltage synchronization circuit and display device thereof. The power supply voltage synchronization circuit includes a comparator circuit, a voltage output judgment circuit, and a synchronization control circuit. The comparator circuit provides a voltage difference between the first power supply voltage and the second power supply voltage. The voltage output determination circuit determines to output the first power supply voltage or the ground voltage according to the voltage difference and the reference voltage. The synchronization control circuit determines whether to output the first power supply voltage or the ground voltage provided by the voltage determination circuit according to the second power supply voltage.

Description

Power supply voltage synchronization circuit and display device

The invention relates to a voltage synchronization circuit, and in particular to a power supply voltage synchronization circuit and a display device thereof.

Source driver IC (SDIC) In order to increase the protection capability of Electrostatic Discharge (ESD), an electrostatic discharge element such as an electrostatic discharge diode is placed between each power line (or power electrode). Or electrostatic discharge can block the circuit to prevent abnormal surges and large voltage breakdown. The current source drivers for high-resolution applications are mostly half-voltage designs. Inside the source driver integrated circuit, an electrostatic discharge diode is added between the high voltage and the intermediate voltage, where the intermediate voltage is about half of the high voltage. The breakdown voltage of the electrostatic discharge diode is designed to be approximately equal to the intermediate voltage, but usually the high voltage will be ready before the intermediate voltage. Therefore, the electrostatic discharge diode may be subjected to excessive voltage and operate in the collapse region, which is too high. Large currents can cause damage to the electrostatic discharge diode. Therefore, how to avoid the damage of the electrostatic discharge diode has become an important issue in designing a display device.

The invention provides a power supply voltage synchronization circuit and a display device thereof. When the power supply voltage is not stable, the electrostatic discharge element in the source driver can be prevented from suffering from excessive voltage and collapse.

The power supply voltage synchronization circuit of the present invention includes a comparator circuit, a voltage output determination circuit, and a synchronization control circuit. The comparator circuit receives a first power supply voltage for supplying power to the source driver and a second power supply voltage lower than the first power supply voltage to provide a voltage difference between the first power supply voltage and the second power supply voltage. The voltage output judging circuit is coupled to the comparator circuit, and receives the first power voltage, the voltage difference, the reference voltage, and the ground voltage to determine to output the first power voltage or the ground voltage according to the voltage difference and the reference voltage. The synchronization control circuit is coupled to the voltage output determination circuit and the first power supply line of the source driver, and receives the second power supply voltage to determine whether to output the first power supply voltage or the ground voltage provided by the voltage output determination circuit according to the second power supply voltage.

The display device of the present invention includes a power supply circuit, a display panel, a source driver, and the power supply voltage synchronization circuit as described above. The power circuit provides a first power voltage and a second power voltage lower than the first power voltage. The source driver is coupled to the power supply circuit, the power supply voltage synchronization circuit, and the display panel to drive the display panel using the synchronized first power supply voltage and the second power supply voltage. The first power supply line of the source driver is used to receive the synchronized first power supply line. A power supply voltage. The second power supply line of the source driver is used to receive the second power supply voltage. A first electrostatic protection (ESD) element is disposed between the first power supply line and the second power supply line, and the second power supply line is connected to a ground. A second electrostatic protection element is arranged between the wires. The power supply voltage synchronization circuit is coupled between the power supply circuit and the source driver. Between the first power lines, whether to provide the first power voltage to the first power line is determined according to a voltage difference between the first power voltage and the second power voltage.

Based on the above, the power supply voltage synchronization circuit and the display device of the embodiment of the present invention compare the voltage difference between the first power supply voltage and the second power supply voltage with a reference voltage to determine whether the first power supply voltage is provided to the source driver. First power cord. Thereby, the electrostatic discharge element in the source driver can be prevented from being collapsed due to excessive voltage.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

100‧‧‧ display device

110‧‧‧Power circuit

120‧‧‧ Power supply voltage synchronization circuit

130‧‧‧Source Driver

131‧‧‧Drive circuit

140‧‧‧display panel

310‧‧‧ Comparator Circuit

320‧‧‧Voltage output judgment circuit

330‧‧‧The first voltage divider

340‧‧‧Voltage maintenance circuit

350‧‧‧Synchronous control circuit

360‧‧‧Push-Pull Circuit

370‧‧‧Second Voltage Divider

380‧‧‧Voltage maintenance and discharge circuit

AVDD‧‧‧First power supply voltage

AVDD1‧‧‧ the first power supply voltage after synchronization

BT1‧‧‧First interface transistor

C1‧‧‧first capacitor

C2‧‧‧Second capacitor

DVDD‧‧‧Main Power Supply Voltage

ESD1‧‧‧The first electrostatic protection element

ESD2‧‧‧Second ESD Protection Element

GND‧‧‧ ground voltage

HAVDD‧‧‧Second power supply voltage

LGD‧‧‧ ground wire

LP1‧‧‧First Power Cord

LP2‧‧‧Second Power Cord

M1‧‧‧The first metal oxide semiconductor

M2‧‧‧Second Metal Oxide Semitransistor

M3‧‧‧Third Metal Oxide Semitransistor

R1‧‧‧first resistor

R10‧‧‧Tenth resistor

R11‧‧‧Eleventh resistor

R12‧‧‧Twelfth resistor

R13‧‧‧Thirteenth resistor

R14‧‧‧fourteenth resistor

R2‧‧‧Second resistor

R3‧‧‧Third resistor

R4‧‧‧Fourth resistor

R5‧‧‧Fifth resistor

R6‧‧‧sixth resistor

R7‧‧‧seventh resistor

R8‧‧‧eighth resistor

R9‧‧‧ Ninth Resistor

U1‧‧‧ Operational Amplifier

U2‧‧‧ Comparator

Va‧‧‧Voltage difference

Vcom‧‧‧common voltage

VGMA‧‧‧Gamma Reference Voltage

Vin‧‧‧ main power supply voltage

VP‧‧‧Pixel voltage

VR‧‧‧ Reference Voltage

FIG. 1 is a system diagram of a display device according to an embodiment of the invention.

FIG. 2A and FIG. 2B are timing synchronization diagrams of a first power voltage and a second power voltage according to an embodiment of the present invention.

FIG. 3 is a system schematic diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention.

FIG. 1 is a system diagram of a display device according to an embodiment of the invention. Please refer to FIG. 1. In this embodiment, the display device 100 includes a power supply circuit 110, a power supply voltage synchronization circuit 120, a source driver 130, and a display panel 140. The power supply circuit 110 receives a main power supply voltage Vin to provide the source driver 130. The required digital power supply voltage DVDD, the gamma reference voltage VGMA, the first power supply voltage AVDD, the second power supply voltage HAVDD, and the ground voltage GND.

The source driver 130 is coupled to the power supply circuit 110 and the display panel 140, and has at least a drive circuit 131, a first power supply line LP1, a second power supply line LP2, and a ground line LGD. Only necessary parts are illustrated here, but not Other types of source drivers are limited to the embodiments of the present invention. In other words, in some embodiments, the driving circuit 131 has at least a gamma voltage generator, a control logic, a data channel, etc., which may be determined by a person skilled in the art.

The first power supply line LP1 of the source driver 130 is used to receive the first power supply voltage AVDD1 (that is, the synchronized first power supply voltage AVDD), the second power supply line LP2 is used to receive the second power supply voltage HAVDD, and the ground line LGD is used To receive a ground voltage GND, where the second power supply voltage HAVDD is less than the first power supply voltage AVDD. The driving circuit 131 uses the synchronized first power voltage AVDD1 and the second power voltage HAVDD to provide a plurality of pixel voltages VP to the display panel 140 to drive the display panel 140. At least one first electrostatic protection (ESD) element ESD1 is disposed between the first power line LP1 and the second power line LP2, and at least one second electrostatic protection element ESD2 is disposed between the second power line LP2 and the ground line LGD. The driving circuit 131 uses the synchronized first power voltage AVDD1 to provide multiple gamma voltages, and the second power voltage HAVDD may be an intermediate voltage value of the multiple gamma voltages.

The power supply voltage synchronization circuit 120 is coupled between the power supply circuit 110 and the first power supply line LP2 of the source driver 130, and receives a first power supply voltage AVDD and a second power supply voltage HAVDD, so as to comply with the first power supply voltage AVDD and the second power supply. The voltage difference between the voltages HAVDD determines whether to provide the first power supply voltage AVDD to the first power supply line LP1. In addition, the power supply voltage synchronization circuit 120 is coupled to the display panel 140 and provides a common voltage Vcom to the display panel 140 by using the synchronized first power supply voltage AVDD1. The display panel 140 may only receive the common voltage Vcom provided by the power supply voltage synchronization circuit 120 to avoid pulling between the power supply circuits leading to an increase in power consumption.

In this embodiment, the power supply voltage synchronization circuit 120 and the source driver 130 are configured separately, but in other embodiments, the power supply voltage synchronization circuit 120 is configured in the source driver 130, which may vary depending on the process capability. The embodiment of the present invention is not limited thereto.

FIG. 2A and FIG. 2B are timing synchronization diagrams of a first power voltage and a second power voltage according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2A. Generally speaking, the second power supply voltage HAVDD is generated by using the first power supply voltage AVDD. Therefore, the first power supply voltage AVDD is usually ready first, that is, first reaches a predetermined level, and After a period of time, the second power supply voltage HAVDD will reach a predetermined level to prevent the generation of the second power supply voltage HAVDD from affecting the stability of the first power supply voltage AVDD.

Then, when the first power supply voltage AVDD is ready, the power supply voltage synchronization circuit 120 is activated by the trigger of the first power supply voltage AVDD, but at this time the first power supply The voltage difference between the voltage AVDD and the second power supply voltage HAVDD is too large, so the first power supply voltage AVDD is blocked, so that the synchronized first power supply voltage AVDD1 is still the ground voltage GND. Then, after the second power supply voltage HAVDD is ready, the voltage difference between the first power supply voltage AVDD and the second power supply voltage HAVDD is less than the breakdown voltage of the first electrostatic protection element ESD1, the power supply voltage synchronization circuit 120 starts transmitting the first power supply voltage AVDD, Therefore, the time points when the first power supply voltage AVDD1 and the second power supply voltage HAVDD after synchronization are ready will be similar.

In addition, when the voltage of the second power supply voltage HAVDD is too low or the voltage difference between the first power supply voltage AVDD and the second power supply voltage HAVDD is too large, since the source driver 130 is not yet stable at this time, the power supply voltage synchronization circuit 120 may transfer the common voltage Vcom is pulled down to the ground voltage GND to discharge the charges in the display panel 140, thereby preventing display panel 140 from displaying errors.

FIG. 3 is a system schematic diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention. Please refer to FIGS. 1 and 3. In this embodiment, the power supply voltage synchronization circuit 120 includes a comparator circuit 310, a voltage output determination circuit 320, a first voltage divider 330, a voltage maintenance circuit 340, a synchronization control circuit 350, and a push-pull. A circuit 360, a second voltage divider 370, and a voltage sustaining and discharging circuit 380.

The comparator circuit 310 receives a first power supply voltage AVDD for supplying power to the source driver 130 and a second power supply voltage HAVDD that is lower than the first power supply voltage AVDD to provide a voltage between the first power supply voltage AVDD and the second power supply voltage HAVDD. The voltage difference Va, where the voltage difference Va is the first power supply voltage AVDD minus the second power supply voltage HAVDD. The first voltage divider 330 is used to provide a reference voltage VR, The reference voltage VR is smaller than the minimum breakdown voltage of the ESD protection element (such as ESD1) coupled to the first power line LP1 in the source driver 130.

The voltage output judging circuit 320 is coupled to the comparator circuit 310 and the first voltage divider 330, and receives a first power voltage AVDD, a voltage difference Va, a reference voltage VR, and a ground voltage GND to determine the output according to the voltage difference Va and the reference voltage VR. The first power supply voltage AVDD or the ground voltage GND. Further, when the voltage difference Va is greater than or equal to the reference voltage VR, the voltage output determination circuit 320 outputs a ground voltage GND; when the voltage difference Va is less than the reference voltage VR, the voltage output determination circuit 320 outputs a first power supply voltage AVDD.

The voltage maintaining circuit 340 is coupled to the voltage output determination circuit 320 to maintain the first power supply voltage AVDD or the ground voltage GND provided by the voltage output determination circuit 320. The synchronization control circuit 350 is coupled to the voltage output determination circuit 320 and is coupled to the first power line LP1 of the source driver 130 through the push-pull circuit 360. In addition, the second power supply voltage HAVDD is received to determine whether to output the first power supply voltage AVDD or the ground voltage GND provided by the voltage output determination circuit 320 according to the second power supply voltage HAVDD. In other words, when the second power supply voltage HAVDD is less than or equal to a critical value, the synchronization control circuit 350 is rendered non-conductive, that is, the first voltage source AVDD provided by the voltage output determination circuit 320 is not output, and only the ground voltage GND is output. When the power supply voltage HAVDD is greater than the aforementioned threshold, the synchronization control circuit 350 is turned on, that is, the first power supply voltage AVDD or the ground voltage GND provided by the voltage output determination circuit 320 is output.

The push-pull circuit 360 is coupled to the synchronization control circuit 350 and the first power line LP1. To enhance the synchronized first power voltage AVDD1 or the ground voltage GND provided by the synchronization control circuit 350. The second voltage divider 370 is coupled to the first power line LP1 through the push-pull circuit 360 to provide a common voltage Vcom to the display panel 140 according to the synchronized first power voltage AVDD1 or the ground voltage GND provided by the push-pull circuit 360. The voltage maintaining and discharging circuit 380 is coupled to the first power line LP1 through the push-pull circuit 360 to perform voltage maintenance or discharge according to the synchronized first power voltage AVDD1 or the ground voltage GND provided by the push-pull circuit 360.

FIG. 4 is a circuit diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention. Please refer to FIGS. 3 and 4. In this embodiment, the comparator circuit 310 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The operational amplifier U1 has a first input terminal (here, a negative input terminal is taken as an example), a second input terminal (here, a positive input terminal is taken as an example), and an output terminal providing a voltage difference Va. The first resistor R1 is coupled between the second power voltage HAVDD and the first input terminal of the operational amplifier U1. The second resistor R2 is coupled between the first power voltage AVDD and the second input terminal of the operational amplifier U1. The third resistor R3 is coupled between the second input terminal of the operational amplifier U1 and the ground voltage GND. The fourth resistor R4 is coupled between the first input terminal of the operational amplifier U1 and the output terminal of the operational amplifier U1.

In this embodiment, the first voltage divider 330 includes a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is coupled between the first power voltage AVDD and the reference voltage VR. The sixth resistor R6 is coupled between the reference voltage VR and the ground voltage GND. Here, the resistance value of the sixth resistor R6 is shown to be variable, but in other embodiments, the resistance value of the fifth resistor R5 may be variable, or the fifth resistance R5 and the The resistance values of the six resistors R6 are all variable, which can be determined according to the circuit design, and the embodiment of the present invention is not limited thereto.

In this embodiment, the voltage output determination circuit 320 includes a comparator U2. The comparator U2 has a first terminal for receiving the voltage difference Va (here, a negative input terminal is taken as an example), a second terminal for receiving a reference voltage VR (here, a positive input terminal is taken as an example), and a positive terminal for receiving the first power supply voltage AVDD. A power supply terminal, a negative power supply terminal receiving a ground voltage GND, and output terminals of a ninth resistor R9 and a tenth resistor R10 coupled to the synchronization control circuit 350. The voltage maintaining circuit 340 includes a first capacitor C1 which is coupled between the output terminal of the comparator U2 and the ground voltage GND.

In this embodiment, the synchronization control circuit 350 includes a first junction transistor BT1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a first metal-oxide semiconductor transistor M1. The first junction transistor BT1 has a base, a collector, and an emitter that receives a ground voltage GND. The seventh resistor R7 is coupled between the second power voltage HAVDD and the base of the first junction transistor BT1. The eighth resistor R8 is coupled between the base of the first junction transistor BT1 and the ground voltage GND. The resistance of the eighth resistor R8 is variable here, but in other embodiments, it may be the seventh The resistance value of the resistor R7 is variable, or the resistance values of the seventh resistor R7 and the eighth resistor R8 are both variable. This may depend on the circuit design, and the embodiment of the present invention is not limited thereto. The ninth resistor R9 is coupled between the voltage output determination circuit 320 and the collector of the first junction transistor BT1. The first metal-oxide-semiconductor M1 has a gate, a drain coupled to a collector of the first junction transistor BT1, and a source receiving a ground voltage GND. The tenth resistor R10 is coupled between the voltage output judgment circuit 320 and the drain of the first metal-oxide semiconductor transistor M1. between.

In this embodiment, the push-pull circuit 360 includes a second metal-oxide semiconductor transistor M2, a third metal-oxide semiconductor transistor M3, and an eleventh resistor R11. The second metal-oxide-semiconductor transistor M2 has a gate of the synchronous control circuit 350, a drain coupled to the eleventh resistor R11, and a source coupled to the first power line LP1. The third metal-oxide semiconductor transistor M3 has a gate coupled to the synchronization control circuit 350, a source coupled to the first power line LP1, and a drain receiving the ground voltage GND. The eleventh resistor R11 is coupled between the first power supply voltage AVDD and the drain of the second metal-oxide-semiconductor M2.

In this embodiment, the second voltage divider 370 includes a twelfth resistor R12 and a thirteenth resistor R13. The twelfth resistor R12 is coupled between the first power line LP1 and the common voltage Vcom. The thirteenth resistor R13 is coupled between the common voltage Vcom and the ground voltage GND. The resistance of the thirteenth resistor R13 is variable here, but in other embodiments, it may be the resistance of the twelfth resistor R12. The value is variable, or the resistance values of the eleventh resistor R11 and the twelfth resistor R12 are both variable. This may be determined according to the circuit design, and the embodiment of the present invention is not limited thereto.

In this embodiment, the voltage sustaining and discharging circuit 380 includes a fourteenth resistor R14 and a second capacitor C2. The fourteenth resistor R14 is coupled between the first power line LP1 and the ground voltage GND. The second capacitor C2 is coupled between the first power line LP1 and the ground voltage GND.

When the main power supply voltage Vin is turned on, the power ready sequence is Vin → DVDD → AVDD → VGMA / HAVDD. Next, the first power supply voltage AVDD and the second power supply voltage HAVDD pass through a subtractor constituted by the operational amplifier U1 as a main, and then output power. Pressure difference Va. When the voltage difference Va is greater than or equal to the breakdown voltage of the electrostatic protection element (such as ESD1), the comparator U2 outputs a ground voltage GND; when the voltage difference Va is less than the breakdown voltage of the electrostatic protection element (such as ESD1), the comparator U2 outputs a first power source Voltage AVDD. The breakdown voltage of the ESD protection element (such as ESD1) may depend on the design of the source driver, and the embodiment of the present invention is not limited thereto.

While the comparator circuit 310 determines the voltage difference Va between the first power supply voltage AVDD and the second power supply voltage HAVDD, the voltage timing synchronous output control of the synchronization control circuit 350 is as follows. When the second power supply voltage HAVDD is established, the synchronization control circuit 350 is triggered with the second power supply voltage HAVDD, and the timing of the power supply voltage is re-established as Vin → DVDD → AVDD / VGMA / HAVDD in cooperation with the comparator circuit 310 and the voltage output determination circuit 320. .

Further, when the voltage difference Va is greater than or equal to the breakdown voltage of the ESD protection element (such as EDS1), the comparator U2 outputs a ground voltage GND, where the third metal-oxide semiconductor transistor M3 is turned on and the first metal-oxide semiconductor transistor M3 is turned on. M1 and the second metal-oxide semiconductor transistor M2 are not conductive. At this time, the synchronized first power supply voltage AVDD1 is the ground voltage, and the display panel 140 displays a black screen, thereby avoiding the introduction of a large current by the electrostatic protection element (such as ESD1) operating in the collapse area, which may cause the source driver 130 to be damaged or damaged. The power circuit 110 is turned off.

When the voltage difference Va is less than the breakdown voltage of the electrostatic protection element (such as ESD1), the comparator U2 outputs a first power supply voltage AVDD, wherein the first junction transistor BT1 and the second metal-oxide semiconductor transistor M2 are turned on, and the first The metal-oxide-semiconductor M1 and the third metal-oxide-semiconductor M3 are non-conducting. At this time, the first power supply voltage after synchronization AVDD1 is the first power supply voltage AVDD, and the display panel 140 displays normally.

On the other hand, during the power supply establishment process, when the second power supply voltage HAVDD has not been established, the first metal-oxide semiconductor transistor M1 is turned on, and the first junction transistor BT1 is not turned on. At this time, the second metal-oxide-semiconductor M2 is non-conducting, the third metal-oxide-semiconductor M3 is non-conductive, and the synchronized first power supply voltage AVDD1 and the common voltage Vcom are ground voltages GND. Next, the display panel 140 displays a black screen, which can prevent the power supply voltage of the source driver 130 from being set up asynchronously and violating the operation regulations to cause an abnormality. On the other hand, the power supply voltage synchronization circuit 120 causes the pixel voltage VP and the common voltage Vcom to be the ground voltage GND when the power supply voltage is ready or when an abnormal state occurs, which can quickly clear the liquid crystal charge and prevent unnecessary charge. Accumulate and reduce the residual charge from the last shutdown to improve problems such as flicker and image sticking.

In addition, during the power-off sequence, all power supplies are in a floating state. Among them, the discharge timing is different due to the display panel 140 design or load relationship. The power supply voltage synchronization circuit 120 is not AVDD / HAVDD / GMA. The order of the discharges can also make the synchronized first power supply voltage AVDD1 and the common voltage Vcom the ground voltage GND. The discharging (off) timing of the power supply voltage is, for example: (a) Vin → AVDD / HAVDD / VGMA → DVDD (black screen); (b) Vin → HAVDD / VGMA → AVDD → DVDD (black screen); (c) Vin → AVDD → HAVDD / VGMA → DVDD (black screen).

Therefore, the power supply voltage synchronization circuit 120 is turned on regardless of the display device 100. When the power supply is switched off, the first power supply voltage AVDD and the second power supply voltage HAVDD can be used to pull down the first power supply voltage AVDD and the common voltage Vcom to the ground voltage GND to achieve rapid discharge and charge emptying in the display panel 140. , It can reduce the charge residual of the liquid crystal cell (not shown) in the display panel 140, reduce the flickering at power-on, and improve the image sticking (IS).

In summary, the power supply voltage synchronization circuit and the display device of the embodiment of the present invention compare the voltage difference between the first power supply voltage and the second power supply voltage and the reference voltage to determine whether the first power supply voltage is provided to the source. The first power cord of the drive. Thereby, the electrostatic discharge element in the source driver can be prevented from being collapsed due to excessive voltage. In addition, when the source driver is not yet stable, the power supply voltage synchronization circuit can pull the common voltage to the ground voltage to discharge the charge in the display panel, thereby avoiding display panel display errors.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ display device

110‧‧‧Power circuit

120‧‧‧ Power supply voltage synchronization circuit

130‧‧‧Source Driver

131‧‧‧Drive circuit

140‧‧‧display panel

AVDD‧‧‧First power supply voltage

AVDD1‧‧‧ the first power supply voltage after synchronization

DVDD‧‧‧ Digital Power Supply Voltage

ESD1‧‧‧The first electrostatic protection element

ESD2‧‧‧Second ESD Protection Element

GND‧‧‧ ground voltage

HAVDD‧‧‧Second power supply voltage

LGD‧‧‧ ground wire

LP1‧‧‧First Power Cord

LP2‧‧‧Second Power Cord

Vcom‧‧‧common voltage

VGMA‧‧‧Gamma Reference Voltage

Vin‧‧‧ main power supply voltage

VP‧‧‧Pixel voltage

Claims (20)

A power supply voltage synchronization circuit includes: a comparator circuit that receives a first power supply voltage for supplying power to a source driver and a second power supply voltage lower than the first power supply voltage to provide the first power supply voltage A voltage difference from the second power supply voltage; a voltage output judging circuit coupled to the comparator circuit, and receiving the first power supply voltage, the voltage difference, a reference voltage, and a ground voltage according to the voltage The difference and the reference voltage determine to output the first power voltage or the ground voltage. A voltage maintaining circuit is coupled to the voltage output judgment circuit to maintain the first power voltage or the ground voltage provided by the voltage output judgment circuit. A synchronization control circuit, which is coupled to the voltage output judgment circuit and the voltage maintaining circuit, and receives the second power voltage to determine whether to output the synchronized first voltage provided by the voltage output judgment circuit according to the second power voltage; A power supply voltage or the ground voltage; and a push-pull circuit coupled to the synchronous control circuit and receiving the synchronous control circuit output The synchronized first power supply voltage or the ground voltage is provided according to the synchronized first power supply voltage or the ground voltage push-pull circuit and the synchronized first power supply is output according to the synchronization control circuit. Voltage or the ground voltage to the first power line. The power supply voltage synchronization circuit according to item 1 of the scope of patent application, wherein the voltage difference is the first power supply voltage minus the second power supply voltage. The power supply voltage synchronization circuit according to item 2 of the scope of patent application, wherein the comparator circuit includes: an operational amplifier having a first input terminal, a second input terminal, and an output terminal providing the voltage difference; a first A resistor coupled between the second power supply voltage and the first input terminal of the operational amplifier; a second resistor coupled between the first power supply voltage and the second input terminal of the operational amplifier; A third resistor is coupled between the second input terminal of the operational amplifier and the ground voltage; and a fourth resistor is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier between. The power supply voltage synchronization circuit according to item 1 of the patent application scope further includes a first voltage divider for providing the reference voltage. The power supply voltage synchronization circuit according to item 4 of the scope of patent application, wherein the first voltage divider comprises: a fifth resistor coupled between the first power supply voltage and the reference voltage; and a sixth resistor, Is coupled between the reference voltage and the ground voltage. The power supply voltage synchronization circuit according to item 1 of the patent application scope, wherein the voltage output judging circuit includes: a comparator having a first terminal receiving the voltage difference, a second terminal receiving the reference voltage, and receiving the A positive power terminal of the first power voltage, a negative power terminal receiving the ground voltage, and an output terminal coupled to the synchronization control circuit. The power supply voltage synchronization circuit according to item 1 of the patent application scope, wherein the voltage maintaining circuit includes a first capacitor. The power supply voltage synchronization circuit according to item 1 of the patent application scope, wherein the synchronization control circuit includes: a first junction transistor having a base, a collector, and an emitter receiving the ground voltage; a first Seven resistors are coupled between the second power supply voltage and the base; an eighth resistor is coupled between the base and the ground voltage; a ninth resistor is coupled between the voltage output judgment circuit and Between the collectors; a first metal-oxide semiconductor transistor having a gate, a drain coupled to the collector, and a source receiving the ground voltage; and a tenth resistor coupled to the voltage An output judgment circuit is connected to the drain of the first metal-oxide semiconductor transistor. The power supply voltage synchronization circuit according to item 1 of the patent application scope, wherein the push-pull circuit enhances the first power supply voltage or the ground voltage after synchronization provided by the synchronization control circuit. The power supply voltage synchronization circuit according to item 9 of the scope of patent application, wherein the push-pull circuit includes: a second metal-oxide-semiconductor having a gate electrode, a drain electrode coupled to the synchronization control circuit and A source of the first power line; a third metal-oxide semiconductor transistor having a gate coupled to the synchronization control circuit, a source coupled to the first power line, and a drain electrode receiving the ground voltage And an eleventh resistor, which is coupled between the first power voltage and the drain of the second metal-oxide-semiconductor transistor. The power supply voltage synchronization circuit according to item 1 of the patent application scope further includes a second voltage divider coupled to the synchronization control circuit, so as to be based on the first power supply voltage or the synchronization after the synchronization control circuit provides the synchronization. The ground voltage provides a common voltage to a display panel. The power supply voltage synchronization circuit according to item 11 of the scope of the patent application, wherein the second voltage divider includes: a twelfth resistor coupled between the first power line and the common voltage; and a thirteenth The resistor is coupled between the common voltage and the ground voltage. The power supply voltage synchronization circuit according to item 1 of the patent application scope further includes a voltage sustaining and discharging circuit coupled to the synchronization control circuit, so as to be based on the first power supply voltage or the synchronization after the synchronization control circuit provides. The ground voltage is maintained or discharged. The power supply voltage synchronization circuit according to item 13 of the patent application scope, wherein the voltage maintaining and discharging circuit comprises: a fourteenth resistor coupled between the first power line and the ground voltage; and a second capacitor Is coupled between the first power line and the ground voltage. The power supply voltage synchronization circuit according to item 1 of the scope of patent application, wherein the second power supply voltage is an intermediate voltage value of a plurality of gamma voltages provided by the first power supply voltage after synchronization. The power supply voltage synchronization circuit according to item 1 of the scope of the patent application, wherein the reference voltage is less than a minimum breakdown voltage of a plurality of electrostatic protection elements coupled to the first power line in the source driver. A display device includes: a power circuit providing a first power voltage and a second power voltage lower than the first power voltage; a display panel; a source driver coupled to the power circuit and the display panel, The display panel is driven by using the first power voltage and the second power voltage, wherein a first power line of the source driver is used to receive the first power voltage, and a second power line of the source driver is used to After receiving the second power voltage, a first electrostatic protection (ESD) element is disposed between the first power line and the second power line, and a second electrostatic protection element is disposed between the second power line and a ground line. ; And a power supply voltage synchronization circuit as described in item 1 of the scope of the patent application, coupled between the power supply circuit and the first power supply line of the source driver so as to be based on the first power supply voltage and the second power supply A voltage difference between the voltages determines whether to provide the first power supply voltage after synchronization to the first power supply line. The display device according to item 17 of the patent application, wherein the power supply voltage synchronization circuit is disposed in the source driver. The display device as described in claim 18, wherein the power supply voltage synchronization circuit and the source driver are configured separately. The display device as described in claim 18, wherein the power supply voltage synchronization circuit is coupled to the display panel to provide a common voltage to the display panel.