TW201913623A - Power supply voltage synchronization circuit and display device thereof - Google Patents
Power supply voltage synchronization circuit and display device thereof Download PDFInfo
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- TW201913623A TW201913623A TW106129618A TW106129618A TW201913623A TW 201913623 A TW201913623 A TW 201913623A TW 106129618 A TW106129618 A TW 106129618A TW 106129618 A TW106129618 A TW 106129618A TW 201913623 A TW201913623 A TW 201913623A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
- H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
- H02M5/22—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M5/275—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M5/293—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
- H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
- H02M5/22—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M5/275—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M5/293—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M5/2932—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage, current or power
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- Power Engineering (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
本發明是有關於一種電壓同步電路,且特別是有關於一種電源電壓同步電路及其顯示裝置。The invention relates to a voltage synchronization circuit, and in particular to a power supply voltage synchronization circuit and a display device thereof.
源極驅動器積體電路(Source driver IC,SDIC)為了增加靜電放電(Electrostatic Discharge,ESD)的保護能力,會在各個電源線(或電源電極)之間放置靜電放電元件,例如靜電放電二極體或靜電放電阻斷電路,以防止異常突波與大電壓的擊穿。以目前針對高解析度應用的源極驅動器,多以半壓設計為主。源極驅動器積體電路內部在高壓與中間電壓之間加入靜電放電二極體,其中中間電壓大約為高壓的一半。而靜電放電二極體的崩潰電壓的設計規格為大約等於中間電壓,但通常高壓會比中間壓先就緒,因此靜電放電二極體可能會遭受過高的電壓而操作在崩潰區,而過高的大電流則會造成靜電放電二極體的毀損。因此,如何避免靜電放電二極體的毀損則成為設計顯示裝置的一個重點課題。Source driver IC (SDIC) In order to increase the protection capability of Electrostatic Discharge (ESD), an electrostatic discharge element such as an electrostatic discharge diode is placed between each power line (or power electrode). Or electrostatic discharge can block the circuit to prevent abnormal surges and large voltage breakdown. The current source drivers for high-resolution applications are mostly half-voltage designs. Inside the source driver integrated circuit, an electrostatic discharge diode is added between the high voltage and the intermediate voltage, where the intermediate voltage is about half of the high voltage. The breakdown voltage of the electrostatic discharge diode is designed to be approximately equal to the intermediate voltage, but usually the high voltage will be ready before the intermediate voltage. Therefore, the electrostatic discharge diode may be subjected to excessive voltage and operate in the collapse region, which is too high. Large currents can cause damage to the electrostatic discharge diode. Therefore, how to avoid the damage of the electrostatic discharge diode has become an important issue in designing a display device.
本發明提供一種電源電壓同步電路及其顯示裝置,在電源電壓未穩定時,可避免源極驅動器內的靜電放電元件遭受過高電壓而崩潰。The invention provides a power supply voltage synchronization circuit and a display device thereof. When the power supply voltage is not stable, the electrostatic discharge element in the source driver can be prevented from suffering from excessive voltage and collapse.
本發明的電源電壓同步電路,包括比較器電路、電壓輸出判斷電路及同步控制電路。比較器電路接收用以供電至源極驅動器的第一電源電壓及低於第一電源電壓的第二電源電壓,以提供第一電源電壓與第二電源電壓之間的電壓差。電壓輸出判斷電路耦接比較器電路,且接收第一電源電壓、電壓差、參考電壓及接地電壓,以依據電壓差及參考電壓決定輸出第一電源電壓或接地電壓。同步控制電路耦接電壓輸出判斷電路及源極驅動器的第一電源線,且接收第二電源電壓,以依據第二電源電壓決定是否輸出電壓輸出判斷電路所提供的第一電源電壓或接地電壓。The power supply voltage synchronization circuit of the present invention includes a comparator circuit, a voltage output determination circuit, and a synchronization control circuit. The comparator circuit receives a first power supply voltage for supplying power to the source driver and a second power supply voltage lower than the first power supply voltage to provide a voltage difference between the first power supply voltage and the second power supply voltage. The voltage output judging circuit is coupled to the comparator circuit, and receives the first power voltage, the voltage difference, the reference voltage, and the ground voltage to determine to output the first power voltage or the ground voltage according to the voltage difference and the reference voltage. The synchronization control circuit is coupled to the voltage output determination circuit and the first power supply line of the source driver, and receives the second power supply voltage to determine whether to output the first power supply voltage or the ground voltage provided by the voltage output determination circuit according to the second power supply voltage.
本發明的顯示裝置,包括電源電路、顯示面板、源極驅動器及如上所述的電源電壓同步電路。電源電路提供第一電源電壓及低於第一電源電壓的第二電源電壓。源極驅動器耦接電源電路、電源電壓同步電路及顯示面板,以利用同步後的第一電源電壓及第二電源電壓驅動顯示面板,其中源極驅動器的第一電源線用以接收同步後的第一電源電壓,源極驅動器的第二電源線用以接收第二電源電壓,第一電源線與第二電源線之間配置一第一靜電防護(ESD)元件,並且第二電源線與一接地線之間配置一第二靜電防護元件。電源電壓同步電路耦接於電源電路與源極驅動器的第一電源線之間,以依據第一電源電壓與第二電源電壓之間的電壓差決定是否提供第一電源電壓至第一電源線。The display device of the present invention includes a power supply circuit, a display panel, a source driver, and the power supply voltage synchronization circuit as described above. The power circuit provides a first power voltage and a second power voltage lower than the first power voltage. The source driver is coupled to the power supply circuit, the power supply voltage synchronization circuit, and the display panel to drive the display panel using the synchronized first power supply voltage and the second power supply voltage. The first power supply line of the source driver is used to receive the synchronized first power supply line. A power supply voltage. The second power supply line of the source driver is used to receive the second power supply voltage. A first electrostatic protection (ESD) element is disposed between the first power supply line and the second power supply line, and the second power supply line is connected to a ground. A second electrostatic protection element is arranged between the wires. The power supply voltage synchronization circuit is coupled between the power supply circuit and the first power supply line of the source driver to determine whether to provide the first power supply voltage to the first power supply line according to a voltage difference between the first power supply voltage and the second power supply voltage.
基於上述,本發明實施例的電源電壓同步電路及其顯示裝置,會比較第一電源電壓與第二電源電壓之間的電壓差與參考電壓,以決定第一電源電壓是否提供至源極驅動器的第一電源線。藉此,可避免源極驅動器內的靜電放電元件遭受過高電壓而崩潰。Based on the above, the power supply voltage synchronization circuit and the display device of the embodiment of the present invention compare the voltage difference between the first power supply voltage and the second power supply voltage with a reference voltage to determine whether the first power supply voltage is provided to the source driver. First power cord. Thereby, the electrostatic discharge element in the source driver can be prevented from being collapsed due to excessive voltage.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
圖1為依據本發明一實施例的顯示裝置的系統示意圖。請參照圖1,在本實施例中,顯示裝置100包括電源電路110、電源電壓同步電路120、源極驅動器130及顯示面板140,其中電源電路110接收主電源電壓Vin以提供源極驅動器130所需要的數位電源電壓DVDD、伽瑪參考電壓VGMA、第一電源電壓AVDD、第二電源電壓HAVDD及接地電壓GND。FIG. 1 is a system diagram of a display device according to an embodiment of the invention. Please refer to FIG. 1. In this embodiment, the display device 100 includes a power supply circuit 110, a power supply voltage synchronization circuit 120, a source driver 130, and a display panel 140. The power supply circuit 110 receives a main power supply voltage Vin to provide the source driver 130. The required digital power supply voltage DVDD, the gamma reference voltage VGMA, the first power supply voltage AVDD, the second power supply voltage HAVDD, and the ground voltage GND.
源極驅動器130耦接電源電路110及顯示面板140,並且例如至少具有驅動電路131、第一電源線LP1、第二電源線LP2及接地線LGD,在此僅繪示說明所需部分,但不限制本發明實施例的其他類型的源極驅動器。換言之,在部分實施例中,驅動電路131例如至少具有伽瑪電壓產生器、控制邏輯、資料通道等,此可依據本領域通常知識者而定。The source driver 130 is coupled to the power supply circuit 110 and the display panel 140, and has at least a drive circuit 131, a first power supply line LP1, a second power supply line LP2, and a ground line LGD. Only necessary parts are illustrated here, but not Other types of source drivers are limited to the embodiments of the present invention. In other words, in some embodiments, the driving circuit 131 has at least a gamma voltage generator, a control logic, a data channel, etc., which may be determined by a person skilled in the art.
源極驅動器130的第一電源線LP1用以接收第一電源電壓AVDD1(亦即同步後的第一電源電壓AVDD),第二電源線LP2用以接收第二電源電壓HAVDD,並且接地線LGD用以接收接地電壓GND,其中第二電源電壓HAVDD小於第一電源電壓AVDD。驅動電路131利用同步後的第一電源電壓AVDD1及第二電源電壓HAVDD提供多個畫素電壓VP至顯示面板140、以驅動顯示面板140。第一電源線LP1與第二電源線之LP2間至少配置一第一靜電防護(ESD)元件ESD1,並且第二電源線LP2與接地線LGD之間至少配置一第二靜電防護元件ESD2。其中,驅動電路131會利用同步後的第一電源電壓AVDD1多個伽瑪電壓,而第二電源電壓HAVDD可以是上述多個伽瑪電壓的中間電壓值。The first power supply line LP1 of the source driver 130 is used to receive the first power supply voltage AVDD1 (that is, the synchronized first power supply voltage AVDD), the second power supply line LP2 is used to receive the second power supply voltage HAVDD, and the ground line LGD is used To receive a ground voltage GND, where the second power supply voltage HAVDD is less than the first power supply voltage AVDD. The driving circuit 131 uses the synchronized first power voltage AVDD1 and the second power voltage HAVDD to provide a plurality of pixel voltages VP to the display panel 140 to drive the display panel 140. At least one first electrostatic protection (ESD) element ESD1 is disposed between the first power line LP1 and the second power line LP2, and at least one second electrostatic protection element ESD2 is disposed between the second power line LP2 and the ground line LGD. The driving circuit 131 uses a plurality of gamma voltages of the synchronized first power supply voltage AVDD1, and the second power supply voltage HAVDD may be an intermediate voltage value of the plurality of gamma voltages.
電源電壓同步電路120耦接於電源電路110與源極驅動器130的第一電源線LP2之間,並且接收第一電源電壓AVDD及第二電源電壓HAVDD,以依據第一電源電壓AVDD與第二電源電壓HAVDD之間的電壓差決定是否提供第一電源電壓AVDD至第一電源線LP1。並且,電源電壓同步電路120耦接至顯示面板140,及利用同步後的第一電源電壓AVDD1提供共同電壓Vcom至顯示面板140。其中,顯示面板140可僅接收電源電壓同步電路120所提供的共同電壓Vcom,以避免電源電路之間的拉扯導至電力消耗的增加。The power supply voltage synchronization circuit 120 is coupled between the power supply circuit 110 and the first power supply line LP2 of the source driver 130, and receives a first power supply voltage AVDD and a second power supply voltage HAVDD, so as to comply with the first power supply voltage AVDD and the second power supply. The voltage difference between the voltages HAVDD determines whether to provide the first power supply voltage AVDD to the first power supply line LP1. In addition, the power supply voltage synchronization circuit 120 is coupled to the display panel 140 and provides a common voltage Vcom to the display panel 140 by using the synchronized first power supply voltage AVDD1. The display panel 140 may only receive the common voltage Vcom provided by the power supply voltage synchronization circuit 120 to avoid pulling between the power supply circuits leading to an increase in power consumption.
在本實施例中,電源電壓同步電路120與源極驅動器130為分離配置,但在其他實施例中,電源電壓同步電路120為配置於源極驅動器130之中,此可依據製程能力而變,本發明實施例不以此為限。In this embodiment, the power supply voltage synchronization circuit 120 and the source driver 130 are configured separately, but in other embodiments, the power supply voltage synchronization circuit 120 is configured in the source driver 130, which may vary depending on the process capability. The embodiment of the present invention is not limited thereto.
圖2A及圖2B為依據本發明一實施例的第一電源電壓及第二電源電壓的時序同步示意圖。請參照圖1及圖2A,一般而言,第二電源電壓HAVDD是利用第一電源電壓AVDD來產生的,因此第一電源電壓AVDD通常會先就緒,亦即先達到預定準位,並且在預定時間之後,第二電源電壓HAVDD才會達到預定準位,以避免第二電源電壓HAVDD的產生影響到第一電源電壓AVDD的穩定。FIG. 2A and FIG. 2B are timing synchronization diagrams of a first power voltage and a second power voltage according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2A. Generally speaking, the second power supply voltage HAVDD is generated by using the first power supply voltage AVDD. Therefore, the first power supply voltage AVDD is usually ready first, that is, first reaches a predetermined level, and After a period of time, the second power supply voltage HAVDD will reach a predetermined level to prevent the generation of the second power supply voltage HAVDD from affecting the stability of the first power supply voltage AVDD.
接著,當第一電源電壓AVDD就緒時,電源電壓同步電路120會受第一電源電壓AVDD的觸發而啟動,但此時第一電源電壓AVDD及第二電源電壓HAVDD的壓差過大,因此第一電源電壓AVDD會被阻擋,以致於同步後的第一電源電壓AVDD1仍為接地電壓GND。接著,當第二電源電壓HAVDD就緒後,第一電源電壓AVDD及第二電源電壓HAVDD的壓差小於第一靜電防護元件ESD1的崩潰電壓之後,電源電壓同步電路120開始傳送第一電源電壓AVDD,以致於同步後的第一電源電壓AVDD1及第二電源電壓HAVDD就緒的時間點會差不多。Then, when the first power supply voltage AVDD is ready, the power supply voltage synchronization circuit 120 is activated by the trigger of the first power supply voltage AVDD, but at this time, the pressure difference between the first power supply voltage AVDD and the second power supply voltage HAVDD is too large, so the first The power supply voltage AVDD will be blocked, so that the synchronized first power supply voltage AVDD1 is still the ground voltage GND. Then, after the second power supply voltage HAVDD is ready, the voltage difference between the first power supply voltage AVDD and the second power supply voltage HAVDD is less than the breakdown voltage of the first electrostatic protection element ESD1, the power supply voltage synchronization circuit 120 starts transmitting the first power supply voltage AVDD, Therefore, the time points when the first power supply voltage AVDD1 and the second power supply voltage HAVDD after synchronization are ready will be similar.
並且,在第二電源電壓HAVDD的電壓過低或第一電源電壓AVDD及第二電源電壓HAVDD的壓差過大時,由於此時源極驅動器130尚未穩定,因此電源電壓同步電路120可將共同電壓Vcom拉低至接地電壓GND,以對顯示面板140中的電荷進行放電,進而避免顯示面板140顯示錯誤。In addition, when the voltage of the second power supply voltage HAVDD is too low or the voltage difference between the first power supply voltage AVDD and the second power supply voltage HAVDD is too large, since the source driver 130 is not yet stable at this time, the power supply voltage synchronization circuit 120 may transfer the common voltage Vcom is pulled down to the ground voltage GND to discharge the charges in the display panel 140, thereby preventing display panel 140 from displaying errors.
圖3為依據本發明一實施例的電源電壓同步電路的系統示意圖。請參照圖1及圖3,在本實施例中,電源電壓同步電路120包括比較器電路310、電壓輸出判斷電路320、第一分壓器330、電壓維持電路340、同步控制電路350、推挽電路360、第二分壓器370及電壓維持及放電電路380。FIG. 3 is a system schematic diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention. Please refer to FIGS. 1 and 3. In this embodiment, the power supply voltage synchronization circuit 120 includes a comparator circuit 310, a voltage output determination circuit 320, a first voltage divider 330, a voltage maintenance circuit 340, a synchronization control circuit 350, and a push-pull. A circuit 360, a second voltage divider 370, and a voltage sustaining and discharging circuit 380.
比較器電路310接收用以供電至源極驅動器130的第一電源電壓AVDD及低於第一電源電壓AVDD的第二電源電壓HAVDD,以提供第一電源電壓AVDD與第二電源電壓HAVDD之間的電壓差Va,其中電壓差Va在此為第一電源電壓AVDD減去第二電源電壓HAVDD。第一分壓器330用以提供參考電壓VR,其中參考電壓VR小於源極驅動器130中與第一電源線LP1耦接的靜電防護元件(如ESD1)中的最小崩潰電壓。The comparator circuit 310 receives a first power supply voltage AVDD for supplying power to the source driver 130 and a second power supply voltage HAVDD that is lower than the first power supply voltage AVDD to provide a voltage between the first power supply voltage AVDD and the second power supply voltage HAVDD. The voltage difference Va, where the voltage difference Va is the first power supply voltage AVDD minus the second power supply voltage HAVDD. The first voltage divider 330 is used to provide a reference voltage VR, where the reference voltage VR is smaller than a minimum breakdown voltage in the ESD protection element (such as ESD1) coupled to the first power line LP1 in the source driver 130.
電壓輸出判斷電路320耦接比較器電路310及第一分壓器330,且接收第一電源電壓AVDD、電壓差Va、參考電壓VR及接地電壓GND,以依據電壓差Va及參考電壓VR決定輸出第一電源電壓AVDD或接地電壓GND。進一步來說,當電壓差Va大於等於參考電壓VR,則電壓輸出判斷電路320輸出接地電壓GND;當電壓差Va小於參考電壓VR,則電壓輸出判斷電路320輸出第一電源電壓AVDD。The voltage output judging circuit 320 is coupled to the comparator circuit 310 and the first voltage divider 330, and receives a first power voltage AVDD, a voltage difference Va, a reference voltage VR, and a ground voltage GND to determine the output according to the voltage difference Va and the reference voltage VR. The first power supply voltage AVDD or the ground voltage GND. Further, when the voltage difference Va is greater than or equal to the reference voltage VR, the voltage output determination circuit 320 outputs a ground voltage GND; when the voltage difference Va is less than the reference voltage VR, the voltage output determination circuit 320 outputs a first power supply voltage AVDD.
電壓維持電路340耦接於電壓輸出判斷電路320,以維持電壓輸出判斷電路320所提供的第一電源電壓AVDD或接地電壓GND。同步控制電路350耦接電壓輸出判斷電路320,且透過推挽電路360耦接源極驅動器130的第一電源線LP1。並且,接收第二電源電壓HAVDD,以依據第二電源電壓HAVDD決定是否輸出電壓輸出判斷電路320所提供的第一電源電壓AVDD或接地電壓GND。換言之,當第二電源電壓HAVDD小於等於一臨界值時,同步控制電路350呈現不導通,亦即不輸出電壓輸出判斷電路320所提供的第一電壓源AVDD,僅輸出接地電壓GND;當第二電源電壓HAVDD大於上述臨界值時,同步控制電路350呈現導通,亦即會輸出電壓輸出判斷電路320所提供的第一電源電壓AVDD或接地電壓GND。The voltage maintaining circuit 340 is coupled to the voltage output determination circuit 320 to maintain the first power supply voltage AVDD or the ground voltage GND provided by the voltage output determination circuit 320. The synchronization control circuit 350 is coupled to the voltage output determination circuit 320 and is coupled to the first power line LP1 of the source driver 130 through the push-pull circuit 360. In addition, the second power supply voltage HAVDD is received to determine whether to output the first power supply voltage AVDD or the ground voltage GND provided by the voltage output determination circuit 320 according to the second power supply voltage HAVDD. In other words, when the second power supply voltage HAVDD is less than or equal to a critical value, the synchronization control circuit 350 is rendered non-conductive, that is, the first voltage source AVDD provided by the voltage output determination circuit 320 is not output, and only the ground voltage GND is output. When the power supply voltage HAVDD is greater than the aforementioned threshold, the synchronization control circuit 350 is turned on, that is, the first power supply voltage AVDD or the ground voltage GND provided by the voltage output determination circuit 320 is output.
推挽電路360耦接同步控制電路350及第一電源線LP1,以增強同步控制電路350所提供的同步後的第一電源電壓AVDD1或接地電壓GND。第二分壓器370透過推挽電路360耦接第一電源線LP1,以依據推挽電路360所提供的同步後的第一電源電壓AVDD1或接地電壓GND提供共同電壓Vcom至顯示面板140。電壓維持及放電電路380透過推挽電路360耦接第一電源線LP1,以依據推挽電路360所提供的同步後的第一電源電壓AVDD1或接地電壓GND進行電壓維持或放電。The push-pull circuit 360 is coupled to the synchronization control circuit 350 and the first power line LP1 to enhance the synchronized first power voltage AVDD1 or the ground voltage GND provided by the synchronization control circuit 350. The second voltage divider 370 is coupled to the first power line LP1 through the push-pull circuit 360 to provide a common voltage Vcom to the display panel 140 according to the synchronized first power voltage AVDD1 or the ground voltage GND provided by the push-pull circuit 360. The voltage maintaining and discharging circuit 380 is coupled to the first power line LP1 through the push-pull circuit 360 to perform voltage maintenance or discharge according to the synchronized first power voltage AVDD1 or the ground voltage GND provided by the push-pull circuit 360.
圖4為依據本發明一實施例的電源電壓同步電路的電路示意圖。請參照圖3及圖4,在本實施例中,比較器電路310包括運算放大器U1、第一電阻R1、第二電阻R2、第三電阻R3及第四電阻R4。運算放大器U1具有第一輸入端(在此以負輸入端為例)、第二輸入端(在此以正輸入端為例)及提供電壓差Va的輸出端。第一電阻R1耦接於第二電源電壓HAVDD與運算放大器U1的第一輸入端之間。第二電阻R2耦接於第一電源電壓AVDD與運算放大器U1的第二輸入端之間。第三電阻R3耦接於運算放大器U1的第二輸入端與接地電壓GND之間。第四電阻R4耦接於運算放大器U1的第一輸入端與運算放大器U1的輸出端之間。FIG. 4 is a circuit diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention. Please refer to FIGS. 3 and 4. In this embodiment, the comparator circuit 310 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The operational amplifier U1 has a first input terminal (here, a negative input terminal is taken as an example), a second input terminal (here, a positive input terminal is taken as an example), and an output terminal that provides a voltage difference Va. The first resistor R1 is coupled between the second power voltage HAVDD and the first input terminal of the operational amplifier U1. The second resistor R2 is coupled between the first power voltage AVDD and the second input terminal of the operational amplifier U1. The third resistor R3 is coupled between the second input terminal of the operational amplifier U1 and the ground voltage GND. The fourth resistor R4 is coupled between the first input terminal of the operational amplifier U1 and the output terminal of the operational amplifier U1.
在本實施例中,第一分壓器330包括第五電阻R5及第六電阻R6。第五電阻R5耦接於第一電源電壓AVDD與參考電壓VR之間。第六電阻R6耦接於參考電壓VR與接地電壓GND之間。其中,在此繪示第六電阻R6的阻值為可變的,但在其他實施例中,可以是第五電阻R5的阻值為可變的,或者第五電阻R5及第六電阻R6的阻值都為可變的,此可依據電路設計而定,本發明實施例不以此為限。In this embodiment, the first voltage divider 330 includes a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is coupled between the first power voltage AVDD and the reference voltage VR. The sixth resistor R6 is coupled between the reference voltage VR and the ground voltage GND. Here, the resistance value of the sixth resistor R6 is shown to be variable, but in other embodiments, the resistance value of the fifth resistor R5 may be variable, or the resistance values of the fifth resistor R5 and the sixth resistor R6 may be variable. The resistance values are all variable, which can be determined according to the circuit design, and the embodiments of the present invention are not limited thereto.
在本實施例中,電壓輸出判斷電路320包括比較器U2。比較器U2具有接收電壓差Va的第一端(在此以負輸入端為例)、接收參考電壓VR的第二端(在此以正輸入端為例)、接收第一電源電壓AVDD的正電源端、接收接地電壓GND的負電源端、以及耦接至同步控制電路350的第九電阻R9及第十電阻R10的輸出端。電壓維持電路340包括第一電容C1,其耦接於比較器U2的輸出端與接地電壓GND之間。In this embodiment, the voltage output determination circuit 320 includes a comparator U2. Comparator U2 has a first terminal that receives a voltage difference Va (here, a negative input terminal is taken as an example), a second terminal that receives a reference voltage VR (a positive input terminal is taken as an example here), and a positive terminal that receives a first power supply voltage AVDD. A power supply terminal, a negative power supply terminal receiving a ground voltage GND, and output terminals of a ninth resistor R9 and a tenth resistor R10 coupled to the synchronization control circuit 350. The voltage maintaining circuit 340 includes a first capacitor C1 which is coupled between the output terminal of the comparator U2 and the ground voltage GND.
在本實施例中,同步控制電路350包括第一接面電晶體BT1、第七電阻R7、第八電阻R8、第九電阻R9、第十電阻R10及第一金氧半電晶體M1。第一接面電晶體BT1具有基極、集極及接收接地電壓GND的射極。第七電阻R7耦接於第二電源電壓HAVDD與第一接面電晶體BT1的基極之間。第八電阻R8耦接於第一接面電晶體BT1的基極與接地電壓GND之間,其中第八電阻R8的阻值在此為可變的,但在其他實施例中,可以是第七電阻R7的阻值為可變的,或者第七電阻R7及第八電阻R8的阻值都為可變的,此可依據電路設計而定,本發明實施例不以此為限。第九電阻R9耦接於電壓輸出判斷電路320與第一接面電晶體BT1的集極之間。第一金氧半電晶體M1具有耦接第一接面電晶體BT1的集極的閘極、汲極及接收接地電壓GND的源極。第十電阻R10耦接於電壓輸出判斷電路320與第一金氧半電晶體M1的汲極之間。In this embodiment, the synchronization control circuit 350 includes a first junction transistor BT1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a first metal-oxide semiconductor transistor M1. The first junction transistor BT1 has a base, a collector, and an emitter that receives a ground voltage GND. The seventh resistor R7 is coupled between the second power voltage HAVDD and the base of the first junction transistor BT1. The eighth resistor R8 is coupled between the base of the first junction transistor BT1 and the ground voltage GND. The resistance of the eighth resistor R8 is variable here, but in other embodiments, it may be the seventh The resistance value of the resistor R7 is variable, or the resistance values of the seventh resistor R7 and the eighth resistor R8 are both variable. This may depend on the circuit design, and the embodiment of the present invention is not limited thereto. The ninth resistor R9 is coupled between the voltage output determination circuit 320 and the collector of the first junction transistor BT1. The first metal-oxide-semiconductor M1 has a gate, a drain coupled to a collector of the first junction transistor BT1, and a source receiving a ground voltage GND. The tenth resistor R10 is coupled between the voltage output determination circuit 320 and the drain of the first metal-oxide-semiconductor M1.
在本實施例中,推挽電路360包括第二金氧半電晶體M2、第三金氧半電晶體M3及第十一電阻R11。第二金氧半電晶體M2具有同步控制電路350的閘極、耦接第十一電阻R11的汲極及耦接第一電源線LP1的源極。第三金氧半電晶體M3具有耦接同步控制電路350的閘極、耦接第一電源線LP1的源極及接收接地電壓GND的汲極。第十一電阻R11耦接於第一電源電壓AVDD與第二金氧半電晶體M2的汲極之間。In this embodiment, the push-pull circuit 360 includes a second metal-oxide semiconductor transistor M2, a third metal-oxide semiconductor transistor M3, and an eleventh resistor R11. The second metal-oxide-semiconductor transistor M2 has a gate of the synchronous control circuit 350, a drain coupled to the eleventh resistor R11, and a source coupled to the first power line LP1. The third metal-oxide semiconductor transistor M3 has a gate coupled to the synchronization control circuit 350, a source coupled to the first power line LP1, and a drain receiving the ground voltage GND. The eleventh resistor R11 is coupled between the first power supply voltage AVDD and the drain of the second metal-oxide-semiconductor M2.
在本實施例中,第二分壓器370包括第十二電阻R12及第十三電阻R13。第十二電阻R12耦接於第一電源線LP1與共同電壓Vcom之間。第十三電阻R13耦接於共同電壓Vcom與接地電壓GND之間,其中第十三電阻R13的阻值在此為可變的,但在其他實施例中,可以是第十二電阻R12的阻值為可變的,或者第十一電阻R11及第十二電阻R12的阻值都為可變的,此可依據電路設計而定,本發明實施例不以此為限。In this embodiment, the second voltage divider 370 includes a twelfth resistor R12 and a thirteenth resistor R13. The twelfth resistor R12 is coupled between the first power line LP1 and the common voltage Vcom. The thirteenth resistor R13 is coupled between the common voltage Vcom and the ground voltage GND. The resistance of the thirteenth resistor R13 is variable here, but in other embodiments, it may be the resistance of the twelfth resistor R12. The value is variable, or the resistance values of the eleventh resistor R11 and the twelfth resistor R12 are both variable. This may be determined according to the circuit design, and the embodiment of the present invention is not limited thereto.
在本實施例中,電壓維持及放電電路380包括第十四電阻R14及第二電容C2。第十四電阻R14耦接於第一電源線LP1與接地電壓GND之間。第二電容C2耦接於第一電源線LP1與接地電壓GND之間。In this embodiment, the voltage sustaining and discharging circuit 380 includes a fourteenth resistor R14 and a second capacitor C2. The fourteenth resistor R14 is coupled between the first power line LP1 and the ground voltage GND. The second capacitor C2 is coupled between the first power line LP1 and the ground voltage GND.
當主電源電壓Vin開啟時,電源就緒順序為Vin→DVDD→AVDD→VGMA/HAVDD。接著,第一電源電壓AVDD及第二電源電壓HAVDD經運算放大器U1為主所構成的減法器後,輸出電壓差Va。當電壓差Va大於等於靜電防護元件(如ESD1)的崩潰電壓時,比較器U2輸出接地電壓GND;當電壓差Va小於靜電防護元件(如ESD1)的崩潰電壓時,比較器U2輸出第一電源電壓AVDD。其中,靜電防護元件(如ESD1)的崩潰電壓可視源極驅動器的設計而定,本發明實施例不以此為限。When the main power supply voltage Vin is turned on, the power ready sequence is Vin → DVDD → AVDD → VGMA / HAVDD. Next, the first power supply voltage AVDD and the second power supply voltage HAVDD pass through a subtractor constituted by the operational amplifier U1 as a main, and then output a voltage difference Va. When the voltage difference Va is greater than or equal to the breakdown voltage of the electrostatic protection element (such as ESD1), the comparator U2 outputs the ground voltage GND; when the voltage difference Va is less than the breakdown voltage of the electrostatic protection element (such as ESD1), the comparator U2 outputs the first power source Voltage AVDD. The breakdown voltage of the ESD protection element (such as ESD1) may depend on the design of the source driver, and the embodiment of the present invention is not limited thereto.
在比較器電路310判斷第一電源電壓AVDD及第二電源電壓HAVDD的電壓差Va的同時,同步控制電路350的電壓時序同步輸出控制如下。當第二電源電壓HAVDD建立時,以第二電源電壓HAVDD觸發同步控制電路350,並且配合比較器電路310及電壓輸出判斷電路320將電源電壓的時序重新建立為Vin→DVDD→AVDD/VGMA/HAVDD。While the comparator circuit 310 determines the voltage difference Va between the first power supply voltage AVDD and the second power supply voltage HAVDD, the voltage timing synchronous output control of the synchronization control circuit 350 is as follows. When the second power supply voltage HAVDD is established, the synchronization control circuit 350 is triggered with the second power supply voltage HAVDD, and the timing of the power supply voltage is re-established as Vin → DVDD → AVDD / VGMA / HAVDD in cooperation with the comparator circuit 310 and the voltage output determination circuit 320. .
進一步來說,當電壓差Va大於等於靜電防護元件(如EDS1)的崩潰電壓時,比較器U2輸出接地電壓GND,其中第三金氧半電晶體M3為導通,而第一金氧半電晶體M1及第二金氧半電晶體M2為不導通。此時,同步後的第一電源電壓AVDD1為接地電壓,顯示面板140顯示黑畫面,藉此可避免靜電防護元件(如ESD1)操作在崩潰區而引入大電流,進而造成源極驅動器130毀損或電源電路110關閉。Further, when the voltage difference Va is greater than or equal to the breakdown voltage of the electrostatic protection element (such as EDS1), the comparator U2 outputs a ground voltage GND, where the third metal-oxide semiconductor transistor M3 is turned on and the first metal-oxide semiconductor transistor M3 is turned on. M1 and the second metal-oxide semiconductor transistor M2 are not conductive. At this time, the synchronized first power supply voltage AVDD1 is a ground voltage, and the display panel 140 displays a black screen, thereby avoiding the introduction of a large current by the electrostatic protection element (such as ESD1) operating in the collapsed area, which may cause damage to the source driver 130 or The power circuit 110 is turned off.
當電壓差Va小於靜電防護元件(如ESD1)的崩潰電壓時,比較器U2輸出第一電源電壓AVDD,其中第一接面電晶體BT1及第二金氧半電晶體M2為導通,而第一金氧半電晶體M1及第三金氧半電晶體M3為不導通,此時同步後的第一電源電壓AVDD1為第一電源電壓AVDD,顯示面板140正常顯示。When the voltage difference Va is less than the breakdown voltage of the electrostatic protection element (such as ESD1), the comparator U2 outputs a first power supply voltage AVDD, wherein the first junction transistor BT1 and the second metal-oxide semiconductor transistor M2 are turned on, and the first The metal-oxide-semiconductor M1 and the third metal-oxide-semiconductor M3 are non-conducting. At this time, the synchronized first power supply voltage AVDD1 is the first power supply voltage AVDD, and the display panel 140 displays normally.
另一方面,在電源建立的過程中,在第二電源電壓HAVDD尚未建立時,第一金氧半電晶體M1為導通,而第一接面電晶體BT1為不導通。此時,第二金氧半電晶體M2為不導通,第三金氧半電晶體M3為導通,同步後的第一電源電壓AVDD1及共同電壓Vcom為接地電壓GND,並且因為液晶無壓差狀況下,顯示面板140顯示黑畫面,可避免源極驅動器130的電源電壓建立時序不同步違反操作規定而產生異常。另一方面,開機在電源電壓就緒過程中或異常狀態發生時,電源電壓同步電路120會使畫素電壓VP及共同電壓Vcom皆為接地電壓GND,可使液晶電荷快速清除,防止電荷不必要的累積,以及減少上一次關機所殘存電荷,以改善開機閃爍(flicker)及影像殘留IS(Image sticking)等問題。On the other hand, during the power supply establishment process, when the second power supply voltage HAVDD has not been established, the first metal-oxide semiconductor transistor M1 is turned on, and the first junction transistor BT1 is not turned on. At this time, the second metal-oxide-semiconductor M2 is non-conducting, the third metal-oxide-semiconductor M3 is non-conductive, and the synchronized first power supply voltage AVDD1 and the common voltage Vcom are ground voltages GND. Next, the display panel 140 displays a black screen, which can prevent the power supply voltage of the source driver 130 from being set up asynchronously and violating the operation regulations to cause an abnormality. On the other hand, the power supply voltage synchronization circuit 120 causes the pixel voltage VP and the common voltage Vcom to be the ground voltage GND when the power supply voltage is ready or when an abnormal state occurs, which can quickly clear the liquid crystal charges and prevent unnecessary charges. Accumulate and reduce the residual charge from the last shutdown to improve problems such as flicker and image sticking.
此外,在電源關閉時序時,所有電源皆在浮接(Floating)狀態,其中由於顯示面板140因設計或負載關係而使放電時序有所不同,而電源電壓同步電路120不管是AVDD/HAVDD/GMA的放電先後順序,亦可使同步後的第一電源電壓AVDD1及共同電壓Vcom為接地電壓GND。上述電源電壓的放電(關閉)時序例如是:(a)Vin→AVDD/HAVDD/VGMA→DVDD (黑畫面);(b)Vin→ HAVDD/VGMA→AVDD→DVDD (黑畫面);(c)Vin→AVDD→HAVDD/VGMA→DVDD (黑畫面)。In addition, during the power-off sequence, all power supplies are in a floating state. Among them, the discharge timing is different due to the design or load of the display panel 140, and the power supply voltage synchronization circuit 120 is not AVDD / HAVDD / GMA. The order of the discharges can also make the synchronized first power supply voltage AVDD1 and the common voltage Vcom the ground voltage GND. The discharging (off) timing of the power supply voltage is, for example: (a) Vin → AVDD / HAVDD / VGMA → DVDD (black screen); (b) Vin → HAVDD / VGMA → AVDD → DVDD (black screen); (c) Vin → AVDD → HAVDD / VGMA → DVDD (black screen).
因此,電源電壓同步電路120不管是顯示裝置100開機或關機時,可透過第一電源電壓AVDD與第二電源電壓HAVDD時間差會先把第一電源電壓AVDD及共同電壓Vcom拉低至接地電壓GND,以達到快速放電以及顯示面板140中電荷清空的功能,將可降低顯示面板140中液晶胞(未繪示)的電荷殘留,減少開機閃爍,改善影像殘留IS(Image sticking)。Therefore, when the power supply voltage synchronization circuit 120 is turned on or off, the first power supply voltage AVDD and the common voltage Vcom can be pulled down to the ground voltage GND through the time difference between the first power supply voltage AVDD and the second power supply voltage HAVDD. In order to achieve the functions of fast discharge and charge emptying in the display panel 140, the charge residual of the liquid crystal cells (not shown) in the display panel 140 can be reduced, the flicker at startup, and the image sticking (IS) can be improved.
綜上所述,本發明實施例的電源電壓同步電路及其顯示裝置,會比較第一電源電壓與第二電源電壓之間的電壓差與參考電壓,以決定第一電源電壓是否提供至源極驅動器的第一電源線。藉此,可避免源極驅動器內的靜電放電元件遭受過高電壓而崩潰。並且,在源極驅動器尚未運作穩定時,電源電壓同步電路可將共同電壓拉低至接地電壓,以對顯示面板中的電荷進行放電,進而避免顯示面板顯示錯誤。In summary, the power supply voltage synchronization circuit and the display device of the embodiment of the present invention compare the voltage difference between the first power supply voltage and the second power supply voltage and the reference voltage to determine whether the first power supply voltage is provided to the source. The first power cord of the drive. Thereby, the electrostatic discharge element in the source driver can be prevented from being collapsed due to excessive voltage. In addition, when the source driver is not yet stable, the power supply voltage synchronization circuit can pull the common voltage to the ground voltage to discharge the charge in the display panel, thereby avoiding display panel display errors.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
100‧‧‧顯示裝置100‧‧‧ display device
110‧‧‧電源電路110‧‧‧Power circuit
120‧‧‧電源電壓同步電路120‧‧‧ Power supply voltage synchronization circuit
130‧‧‧源極驅動器130‧‧‧Source Driver
131‧‧‧驅動電路131‧‧‧Drive circuit
140‧‧‧顯示面板140‧‧‧display panel
310‧‧‧比較器電路310‧‧‧ Comparator Circuit
320‧‧‧電壓輸出判斷電路320‧‧‧Voltage output judgment circuit
330‧‧‧第一分壓器330‧‧‧The first voltage divider
340‧‧‧電壓維持電路340‧‧‧Voltage maintenance circuit
350‧‧‧同步控制電路350‧‧‧Synchronous control circuit
360‧‧‧推挽電路360‧‧‧Push-Pull Circuit
370‧‧‧第二分壓器370‧‧‧Second Voltage Divider
380‧‧‧電壓維持及放電電路380‧‧‧Voltage maintenance and discharge circuit
AVDD‧‧‧第一電源電壓AVDD‧‧‧First power supply voltage
AVDD1‧‧‧同步後的第一電源電壓AVDD1‧‧‧ the first power supply voltage after synchronization
BT1‧‧‧第一接面電晶體BT1‧‧‧First interface transistor
C1‧‧‧第一電容C1‧‧‧first capacitor
C2‧‧‧第二電容C2‧‧‧Second capacitor
DVDD‧‧‧主電源電壓DVDD‧‧‧Main Power Supply Voltage
ESD1‧‧‧第一靜電防護元件ESD1‧‧‧The first electrostatic protection element
ESD2‧‧‧第二靜電防護元件ESD2‧‧‧Second ESD Protection Element
GND‧‧‧接地電壓GND‧‧‧ ground voltage
HAVDD‧‧‧第二電源電壓HAVDD‧‧‧Second power supply voltage
LGD‧‧‧接地線LGD‧‧‧ ground wire
LP1‧‧‧第一電源線LP1‧‧‧First Power Cord
LP2‧‧‧第二電源線LP2‧‧‧Second Power Cord
M1‧‧‧第一金氧半電晶體M1‧‧‧The first metal oxide semiconductor
M2‧‧‧第二金氧半電晶體M2‧‧‧Second Metal Oxide Semitransistor
M3‧‧‧第三金氧半電晶體M3‧‧‧Third Metal Oxide Semitransistor
R1‧‧‧第一電阻R1‧‧‧first resistor
R10‧‧‧第十電阻R10‧‧‧Tenth resistor
R11‧‧‧第十一電阻R11‧‧‧Eleventh resistor
R12‧‧‧第十二電阻R12‧‧‧Twelfth resistor
R13‧‧‧第十三電阻R13‧‧‧Thirteenth resistor
R14‧‧‧第十四電阻R14‧‧‧fourteenth resistor
R2‧‧‧第二電阻R2‧‧‧Second resistor
R3‧‧‧第三電阻R3‧‧‧Third resistor
R4‧‧‧第四電阻R4‧‧‧Fourth resistor
R5‧‧‧第五電阻R5‧‧‧Fifth resistor
R6‧‧‧第六電阻R6‧‧‧sixth resistor
R7‧‧‧第七電阻R7‧‧‧seventh resistor
R8‧‧‧第八電阻R8‧‧‧eighth resistor
R9‧‧‧第九電阻R9‧‧‧ Ninth Resistor
U1‧‧‧運算放大器U1‧‧‧ Operational Amplifier
U2‧‧‧比較器U2‧‧‧ Comparator
Va‧‧‧電壓差Va‧‧‧Voltage difference
Vcom‧‧‧共同電壓Vcom‧‧‧common voltage
VGMA‧‧‧伽瑪參考電壓VGMA‧‧‧Gamma Reference Voltage
Vin‧‧‧主電源電壓Vin‧‧‧ main power supply voltage
VP‧‧‧畫素電壓VP‧‧‧Pixel voltage
VR‧‧‧參考電壓VR‧‧‧ Reference Voltage
圖1為依據本發明一實施例的顯示裝置的系統示意圖。 圖2A及圖2B為依據本發明一實施例的第一電源電壓及第二電源電壓的時序同步示意圖。 圖3為依據本發明一實施例的電源電壓同步電路的系統示意圖。 圖4為依據本發明一實施例的電源電壓同步電路的電路示意圖。FIG. 1 is a system diagram of a display device according to an embodiment of the invention. FIG. 2A and FIG. 2B are timing synchronization diagrams of a first power voltage and a second power voltage according to an embodiment of the present invention. FIG. 3 is a system schematic diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram of a power supply voltage synchronization circuit according to an embodiment of the present invention.
Claims (20)
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