KR100780239B1 - Electro static discharge protection device - Google Patents

Abstract

An electrostatic discharge protection device is provided to reduce a manufacturing cost by removing a coupling capacitor and a coupling register. A plurality of gate electrodes(114) are formed on a substrate. A first junction region and a second junction region are formed within the well which is exposed to both sides of the gate electrode. A dielectric layer is formed on the gate electrodes. An electrode(116) is formed on the dielectric layer. An insulating layer is formed on both sidewalls of the gate electrode. A resistor(117) is separated from the gate electrode by using the insulating layer. A first metal line is used for connecting the gate electrodes with one side of the resistor. A second metal line is used for connecting the other side of the resistor, the first junction region, and a first power ring to each other. A third metal line is used for connecting the electrode, the second junction region, and a second power ring to each other.

Description

Electrostatic Discharge Protection Device {ELECTRO STATIC DISCHARGE PROTECTION DEVICE}

1 is a circuit diagram showing a typical gate grounded N-type MOSFET (GGNMOS) device.

Figure 2 is a circuit diagram showing a typical gate coupled N-type MOSFET (GCNMOS) device.

3A is a plan view of a GGNMOS device.

3B is a cross-sectional view taken along the line II ′ of FIG. 3A.

4 is a plan view showing a GCNMOS device;

Figure 5a is a plan view showing a gate self coupled EDNMOS (GSCEDNMOS) device in accordance with an embodiment of the present invention.

FIG. 5B is a cross-sectional view taken along the line II ′ of FIG. 5A.

Figure 6a is a plan view showing a ring-shaped resistor shown in Figure 5a.

FIG. 6B is a cross-sectional view taken along the line II-II ′ of FIG. 6A.

<Explanation of symbols for main parts of drawing>

1, 3: local ESD protection circuit

2, 4: power clamp

10, 110: HP-well

11, 111: Well Pick-Up Area

12, 112: device isolation film

13A, 13B, 113A, 113B: N ^- drift region

14, 114: gate electrode

15A, 15B, 115A, 115B: N ⁺ Diffusion Area

116 electrodes

117: resistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a power clamp of an electro-static discharge (ESD) protection element of a semiconductor device.

In general, the characteristics of the ESD protection circuit in the manufacturing process of the semiconductor chip (chip) is an important factor that determines the performance of the chip. In recent years, as the size of a semiconductor chip is reduced and the degree of integration is increased, the efficiency of the layout area occupied by the ESD protection circuit is a key factor for determining the size of the entire semiconductor chip.

A typical way of protecting the core circuit of a semiconductor chip from ESD is shown in FIG.

Referring to FIG. 1, in general, an electrode constituting an input / output cell, an input cell, an output cell, or an input / output cell of a semiconductor chip is described. Vss pad (Vss pad), Vdd pad (Vdd pad), I / O pad (I / O pad).

ESD stress current can flow randomly between two of the three electrodes (Vss pad, Vdd pad, I / O pad). Thus, for three electrode combinations such as I / O pad-Vdd pad, I / 0 pad-Vss pad, Vdd pad-Vss pad- to effectively protect the internal circuit against all possible forms of ESD stress current. Since each ESD protection circuit must be installed independently, a total of three types of ESD protection circuits are required. Among these, the ESD protection circuit installed between the I / O pads-Vss pads and between the I / O pads-Vdd pads is referred to as a local ESD protection circuit (1), and is installed between the Vdd pads-Vss pads. The resulting ESD protection circuit is called a power clamp (2).

Of the plurality of ESD protection circuits, the power clamp 21 plays a larger role than other protection circuits. The reason is that even though the ESD stress current flows into the individual I / O pads, the ESD stress current is connected to the Vdd power ring through a diode (or parasitic diode) that must be present in the local ESD protection circuit (1). This is because it flows into the (Vdd power ring) or the Vss power ring and then is discharged to the outside through the power clamp 2. That is, the power clamp 2 plays an important role in handling the ESD stress current no matter which pad the ESD stress current flows into. Therefore, it is very important to develop a power clamp that effectively responds to the introduced ESD stress current.

In most cases, the power clamp 2 uses an N-type MOSFET (hereinafter referred to as a GGNMOS) having a gate connected to a ground voltage node Vss. For most ESD stress currents, GGNMOS power clamps work relatively effectively. However, GGNMOS power clamps do not operate fast enough for currents that flow in or out very quickly, such as CDM-type ESD stress currents, and internal circuits are destroyed by ESD stress currents.

To remedy this problem, it is necessary to develop power clamps that operate faster than GGNMOS power clamps. One methodology that can be used to improve the problems of the GGNMOS power clamp method is to replace the GGNMOS power clamp with a power clamp of a gate coupled N-type MOSFET (GCNMOS) device.

2 is a circuit diagram illustrating a method of using a GCNMOS power clamp.

2, the GCNMOS power clamp is a coupling capacitor (Cc) connected between the gate of the N-type MOSFET and the supply voltage node Vdd, and a coupling resistor (Rc) connected between the gate and Vss. ). In the method using the GCNMOS power clamp 4 having such a structure, when an ESD stress current having a polarity of '+' flows into the I / O pad or the Vdd pad, the Vdc is coupled to the Vdd through the coupling capacitor Cc. Since the voltage is applied to the gate of the power clamp 4 N-type MOSFET as it is, the channel of the N-type MOSFET is opened, thereby enabling the power clamp to operate faster. In other words, the ESD protection scheme employing GCNMOS as a power clamp has the advantage of being able to respond quickly to the ESD stress current flowing rapidly, such as the CDM-type ESD stress current. The time that the voltage applied to Vdd is applied to the gate of the N-type MOSFET is maintained by "τ = Rc x Cc".

In the normal operation of the semiconductor chip, the coupling resistor (Rc) and the coupling resistor (Rc) are generally set to about " τ &lt; The value of the coupling capacitor Cc is determined. In conclusion, the method employing the GCNMOS power clamp has an advantage of more effectively responding to the ESD stress current than the method employing the GGNMOS power clamp. However, there is a disadvantage in that an additional area is required to additionally install the coupling capacitor Cc and the coupling resistor Rc. Therefore, in order to manufacture a semiconductor chip which is still superior in terms of price competitiveness, it is necessary to propose a gate coupling method that can minimize additional consumption of an area.

Accordingly, an object of the present invention is to provide an ESD protection device capable of improving ESD protection characteristics without any burden in terms of size of a semiconductor chip.

According to an aspect of the present invention, a plurality of gate electrodes formed on a substrate, first and second junction regions respectively formed in the substrate exposed to both sides of the gate electrode, and the gate electrode are provided. A dielectric film formed on the dielectric film, an electrode formed on the dielectric film, an insulating film formed on both side walls of the gate electrode, a resistor separated from the gate electrode through the insulating film, and the plurality of gate electrodes and one side of the resistor A first metal wire connecting the first metal wire, a second metal wire connecting the other side of the resistor, the first junction region and the first power ring, and a second connector connecting the electrode, the second junction region and the second power ring. It provides an electrostatic discharge protection device comprising a metal wiring.

Hereinafter, the area consumption of the power clamp will be described with reference to FIGS. 3A, 3B, and 4.

One of the basic characteristics of a semiconductor device operating at high voltage is that the breakdown voltage must be higher than the operation voltage.

In order to satisfy such characteristics, an N-type MOSFET employing a drain (or a source) in which impurities are diffused in a double manner, a so-called double diffused drain N-type MOSFET (DDDNMOS) is basically used. Used as an element. In order to make the DDDNMOS structure, the implantation of the impurity constituting the drain is performed twice, but the impurity implantation is performed at a sufficiently high concentration in the internal drain diffusion (or source diffusion) region. . For example, the dose of N ⁺ diffusion is 10 ¹⁵ to 10 ¹⁶ atoms / cm ³ . On the other hand, the drain drift (or source drift) region outside thereof is impurity implanted at a relatively low concentration. For example, the dose of N ^- drift is 10 ¹³ atoms / cm ³ .

In general, the breakdown voltage has polarities that are electrically opposite to each other, and the lower the impurity concentration of the two regions that meet each other, the higher the tendency is. Therefore, if the structure such as DDDNMOS is employed, the impurity concentration of the drain drift region in contact with the HP-well region can be sufficiently lowered, so that a breakdown voltage as high as desired can be realized.

3A is a plan view illustrating a planar structure of an extended drain N-type MOSFET (EDNMOS) device, which is one type of the DDDNMOS devices. As shown in FIG. 3, the EDNMOS device sufficiently secures an overlap margin of the N ⁺ diffusion (N +) regions 15A and 15B with respect to the N ⁻ drift regions 13A and 13B. As part of the method, the drain diffusion (or source diffusion) regions 15A and 15B are spaced apart from the gate edge by a predetermined distance (Ld, Ls ≒ 1.0 to 3.0 μm). In general, in the case of high voltage NMOS devices such as DDDNMOS (EDNMOS), the channel region under the gate is wide enough to prevent the drain region and the source region from being electrically connected by diffusion of the N ^- drift regions 13A and 13B. Set it. This means that the length Lg of the gate 14 is set sufficiently large (usually Lg? 2.0 to 6.0 mu m).

FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 3A, and is used when the gate 14 of the EDNMOS device is connected to a Vss power ring, that is, a GGEDNMOS (Gate Ground EDNMOS) to be used as an ESD protection circuit. A diagram illustrating an electrode connection method. As shown in FIG. 3B, in order to use EDNMOS operating at high voltage as an ESD protection circuit, a gate, a source, a well pick-up (P ⁺ diffusion) 11 are tied together to form a Vss power line on the circuit. Connect to the (Vss power line) and use only the drain to connect to the Vdd power line or to individual I / O pads. As described above, in the GGEDNMOS configuring the electrode, little current flows when the voltage applied to the drain is lower than the breakdown voltage. On the other hand, when the voltage applied to the drain is higher than the breakdown voltage, impact ionization occurs at the interface where the HP-well 10 and the drain drift region 15B meet to form a plurality of electrical carriers. As a result, a parasitic NPN Bipolar Junction Transistor (NPN-BJT) is formed, and a large amount of current flows between the drain and the source. As a result, the GGEDNMOS, which constitutes the electrode as described above, does not flow under the breakdown voltage, and has a function of flowing the current smoothly only at a voltage higher than the above, thereby protecting the internal circuit by extinguishing an unwanted stress current in an ESD situation. It satisfies basic characteristics that can be used as a circuit.

To increase the amount of ESD stress current the device can extinguish, use a multi-finger GGEDNMOS with multiple single finger structure GGEDNMOS in parallel. These GGEDNMOS devices respond relatively effectively to ESD stress currents that flow in or out relatively slowly, such as human body mode (HBM) type ESD stress. However, for ESD stress currents that flow in or out very quickly, such as CDM type ESD stress currents, the GGEDNMOS device does not operate fast enough so that internal circuits are sometimes destroyed by ESD stress currents. To remedy this problem, it is necessary to use devices that operate faster than GGEDNMOS for ESD stress current, namely gate coupled EDNMOS (GCEDNMOS).

4 is a diagram illustrating a problem in converting a GGEDNMOS device into a GCEDNMOS device. In order to convert the GGEDNMOS device into a GCEDNMOS device, an additional area for installing the coupling capacitor (Cc) and the coupling resistor (Rc) is required. However, as shown in FIG. 3A, the EDNMOS device has a very large base width (transverse distance from the drain region to the source region) due to the characteristics of the high voltage device. Thus, the area occupied by the GGEDNMOS device required to pass the specified ESD stress zapping test is already large enough to be burdensome in terms of the overall chip size. The total area occupied by the GCEDNMOS device is increased because the area for installing the coupling capacitor Cc and the coupling resistor Rc must be added to the area occupied by the large enough EDNMOS device. .

In fact, although the GCEDNMOS device's ESD protection is generally superior to the ESD protection of the GGEDNMOS device, the GGEDNMOS device is used instead of the GCEDNMOS device as the ESD protection circuit of the actual semiconductor chip due to the additional area burden. Frequently occurs. In conclusion, it is necessary to develop a GCEDNMOS device that does not consume an additional area for installing the coupling capacitor (Cc) and the coupling resistor (Rc) in order to maintain a good ESD protection characteristics without burdening the size of the semiconductor chip. have.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example

5A is a plan view illustrating an ESD protection device according to an exemplary embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line II ′ of FIG. 5A. Here, a GSCEDNMOS (Gate Self Coupled Extended Drain N-Type MOSFET) device is shown.

5A and 5B, in the GSCEDNMOS device according to an exemplary embodiment of the present invention, the gate 114 of the basic EDNMOS device illustrated in FIGS. 3A and 3B is used as a lower electrode of the coupling capacitor Cc (see FIG. 2). use. In addition, an electrode 116 is formed on the gate 114 to be separated through a dielectric film (not shown), and the electrode 116 thus formed is used as the upper electrode. In addition, a resistor 117 separated through an insulating film (not shown) is formed on both side walls of the gate 114, and the resistor 117 thus formed is used as a coupling resistor Rc (see FIG. 2).

The gate 114 serving as the lower electrode of the coupling capacitor Cc may be formed of any material that can be used as an electrode material, for example, any one selected from transition metals and rare earth metals, and here, for example, a polysilicon film. Form. In addition, the electrode 116 serving as the upper electrode may also be formed of any material that can be used as the electrode material. In addition, a dielectric film is formed between the lower electrode and the upper electrode, wherein the dielectric film is formed in a stacked structure in which an oxide film-nitride film-oxide film is stacked or a metal oxide film having a high dielectric film higher than that of a silicon oxide film (SiO ₂ ), such as HfO _2. , Al ₂ O ₃ , ZrO ₂ can be formed.

The coupling resistor Rc is formed of a resistor 117 formed in a ring shape so as to surround both side walls of the gate 114. In this case, the resistor 117 may be formed of any material having resistance. It is formed of a polysilicon film for convenience in the manufacturing process. The resistor 117 is electrically separated through the gate 114 and the insulating layer. The resistor 117 is formed to overlap not only both sidewalls of the gate 114 but also a portion of the gate 114, and a portion of the resistor 117 has a low concentration in the junction region. It is preferable to form the phosphorus N ^- drift 113A, 113B and the element isolation film (field oxide film) 112 to overlap. The reason is that when the polysilicon film, which is the resistor 117, does not completely cover both sidewalls of the gate 114, polysilicon may remain on both sidewalls of the gate 114 to affect device characteristics. In addition, the end portions of the resistors 117 overlapping the N ⁻ drifts 113A and 113B are formed so as not to overlap the N ⁺ diffusion regions 115A and 115B which are high concentration regions in the junction region. In addition, the resistor 117 is connected to each other with a ring-shaped resistor formed to surround a neighboring resistor-a neighboring gate 114 on the device isolation layer 112.

The electrode 116 and the gate 114 thus formed are connected in parallel to the Vdd power ring through a metal wiring (not shown). In this way, the gate 114 itself becomes the lower electrode of the coupling capacitor Cc, and the electrode 116 becomes the upper electrode connected to the power supply voltage node Vdd. As a result, the gate 114 of the EDNMOS device is coupled with Vdd through the coupling capacitor Cc. In addition, each gate 114 is connected in parallel using a separate metal wiring (not shown), and the metal wiring is connected to one end of the resistor 117 already connected in series, and the other of the resistor 117 is connected. The side end is connected to the Vss power ring. In this way, as a result, the gates 114 of all the EDNMOS devices are coupled to the ground voltage node Vss through the coupling resistor Rc.

As described above, coupling is performed between the gate 114 and Vdd of the EDNMOS device through a coupling capacitor Cc, and through the coupling resistor Rc between the gate 114 and Vss of the EDNMOS device. Coupling is made. That is, the GCNMOS structure shown in FIG. 2 is formed. As such, the GSCEDNMOS device does not need to implement the coupling capacitor Cc and the coupling resistor Rc separately from the outside of the EDNMOS device, and thus does not require an additional area.

Meanwhile, in order for the GSCEDNMOS device according to the embodiment of the present invention to operate efficiently when an ESD stress current is introduced without causing a problem in a normal operating state of a semiconductor chip, a voltage applied to Vdd is applied to a gate of an N-type MOSFET. It is necessary to adjust the values of the coupling resistor Rc and the coupling capacitor Cc such that the state is maintained for about τ 10 ~ 50 ns. The values of the coupling resistor Rc and the coupling capacitor Cc are determined by the 'Lc' and 'Lr' values shown in FIG. 6 and the width of the total diffusion region of the EDNMOS device, that is, the total gate width of the EDNNMOS device. Depends. Therefore, once the width of the total diffusion region of the EDNMOS device is determined, the value of τ can be adjusted to a desired range by appropriately adjusting the values of 'Lc' and 'Lr'.

Although the technical spirit of the present invention described above has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, if the GSCEDNMOS device according to the present invention is implemented, the following effects can be obtained.

First, according to the present invention, in implementing an ESD protection circuit, a GCNMOS device can be used as a power clamp. Therefore, it is possible to sufficiently and efficiently cope with ESD stress current flowing in or out very quickly, such as CDM-type ESD stress current, thereby ensuring more stable ESD protection characteristics in the semiconductor chip.

Second, according to the present invention, unlike the ESD protection circuit employing the GCNMOS device according to the prior art, it is not necessary to form the coupling capacitor and the coupling resistor according to a separate position. In other words, in ESD protection circuits employing GGNMOS devices, the use of ESD protection circuits employing GCNMOS devices does not place an additional burden on the overall size of the semiconductor chip. Therefore, it is possible to maintain an advantage in price competitiveness of semiconductor chips.

Claims (14)

A plurality of gate electrodes formed on the substrate; First and second junction regions respectively formed in the substrate exposed to both sides of the gate electrode; A dielectric film formed on the gate electrode; An electrode formed on the dielectric film; An insulating film formed on both sidewalls of the gate electrode; A resistor separated from the gate electrode through the insulating layer; A first metal wire connecting the plurality of gate electrodes and one side of the resistor; A second metal wire connecting the other side of the resistor, the first junction region, and the first power ring; And A third metal wiring connecting the electrode, the second junction region, and the second power ring Electrostatic discharge protection device comprising a. The method of claim 1, The resistor is formed in a ring shape so as to surround both side walls of the gate electrode. The method of claim 2, The resistor having the ring shape is an electrostatic discharge protection device connected to each other in series. The method of claim 3, wherein The portion connected in series is an electrostatic discharge protection device overlapping with the portion where the device isolation layer is formed. The method of claim 1, Each of the first and second junction regions is Drift region; And A diffusion region formed in the drift region Electrostatic protection device comprising a. The method of claim 5, And the resistor is formed so that a portion thereof overlaps with the drift region. The method of claim 5, And a diffusion region of the first junction region is connected to the second metal wiring. The method of claim 5, And a diffusion region of the second junction region is connected to the third metal wiring. The method according to any one of claims 5 to 8, And the diffusion region and the drift region have N-type conductivity. The method of claim 1, And the resistor is formed so that a portion thereof overlaps with an upper portion of the gate electrode. The method of claim 1, And the gate electrode, the electrode and the resistor are formed of a polysilicon film. The method of claim 1, And the electrode is formed so as not to overlap with the resistor. The method of claim 1, A well formed in the substrate; And Well pick-up formed in the well Electrostatic discharge protection device further comprising. The method of claim 13, The well pick-up is connected to the second metal wiring electrostatic discharge protection device.

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