KR100914680B1 - Electrostatic discharge protection circuit - Google Patents

Abstract

The present invention relates to an electrostatic protection circuit capable of flexibly responding to a required high voltage while ensuring the characteristics of the electrostatic protection circuit. The electrostatic protection circuit according to the present invention includes a first node to which a high voltage is applied. A second node to which a relatively low voltage is applied relative to one node, and a plurality of NMOS transistors (first NMOS transistors to nth NMOS transistors) are provided between the first node and the second node. It is characterized by being connected in series.

Description

Electrostatic discharge protection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit. More particularly, the present invention relates to an electrostatic protection circuit that can flexibly cope with a required high voltage while ensuring the characteristics of the electrostatic protection circuit.

In integrated circuits, electrostatic discharge induces electrothermal migration within the integrated circuit, and the resulting high voltages and high currents may cause short or low impedance states between transistor terminals. In particular, a MOSFET (metal-oxide semiconductor field effect transistor) has a high risk of breakage of a dielectric.

An electrostatic protection circuit is provided in the integrated circuit to protect the semiconductor device from such electrostatic discharge. The basic characteristics of the electrostatic protection circuit will be described with reference to FIG. 1.

First, the static electricity protection circuit should not operate when a normal operating voltage (V _op ) is applied to the semiconductor device. That is, in the static electricity protection circuit, the leakage current I _off should be sufficiently small when a voltage smaller than the breakdown voltage V _av is applied. In addition, the breakdown voltage (V _av ) and the bipolar junction transistor (BJT) activation voltage (V _tr ) of the ESD protection circuit must be greater than the operating voltage (V _op ) of the semiconductor device (V _av , V _tr > V _op). , See FIG. 1).

Second, the gate oxide layer should not be damaged during operation of the static electricity protection circuit. For this purpose, the active voltage V _tr and the thermal breakdown voltage V _tb must be smaller than the gate oxide breakdown voltage V _gox (V _tr , V _tb > V _gox ).

Third, the static electricity protection circuit should not be operated abnormally by latch up. This requires a sufficient safety margin (ΔV) and the snapback holding voltage (V _sh ) must be greater than the operating voltage (V _op ) of the semiconductor device (V _sh > V _op + ΔV). Or the triggering current (I _tr ) must be large enough (I _tr > -100 mA). Alternatively, thermal breakdown should not occur in the static electricity protection circuit itself by the latch-up operation. For this purpose, the thermal breakdown voltage (V _tb ) must be sufficiently large compared to the operating voltage (V _op ) (V _tb > V _op + ΔV). .

Fourth, the static electricity protection circuit itself must be strong enough against the current generated by static electricity. That is, it must be able to extinguish a large amount of ESD stress current before thermal breakdown occurs. Typically, the static electricity protection circuit is composed of a plurality of elements (finger), each element (finger) constituting the static electricity protection circuit must be uniformly operated to satisfy such a condition. That is, triggering should not occur in a specific device to reach thermal breakdown, and triggering should occur simultaneously in each device to correspond to electrostatic current. For this purpose, the thermal breakdown voltage V _tb must be greater than or at least similar to the active voltage V _tr (V _tr ≤ V _tb ).

In order to satisfy the requirements of the static electricity protection circuit as described above, a high voltage operation device, for example, a GG_DDDNMOS (Gate Grounded Doubled Diffused Drain N-type MOSFET) device is used for the static electricity protection circuit. The condition that the breakdown voltage V _av is greater than the operating voltage V _op is satisfied.

As shown in FIG. 2, the GG_DDDNMOS device includes a device isolation layer 201 defining an active region, a gate electrode 202 provided in the active region, a source / drain region 203 and 204 and a well pickup. pick-up) region 206. The source / drain regions 203 and 204 and the well pick-up region 206 are formed in a p-well, and the drain region 204 is provided in a drain drift region 205. do. Here, the drain drift region 205 is formed at a relatively low concentration of impurities, while the drain region is formed at a high concentration of impurities. As such, the reason for forming the low concentration drain drift region 205 is that the breakdown voltage increases as the impurity concentration is lower when two regions having opposite polarities electrically meet each other. Thus, the low drain drift region 205 may realize a high breakdown voltage.

When the GG_DDDNMOS device having the above structure is used as the static electricity protection circuit, as shown in FIGS. 3A and 3B, the gate G, the source S, and the well-pickup WP may have low voltages (V _L ,) on the circuit. For example, it is connected to the terminal Vss, and the drain D is connected to the terminal of the high voltage (V _H , for example Vdd or pad of the semiconductor element) on the circuit.

In the electrostatic protection circuit using the GG_DDDNMOS device, when the voltage applied to the drain is lower than the breakdown voltage V _av , the current flows almost because the gate, the source, and the channel (the lower region of the gate electrode) maintain almost the same potential. Will not. On the other hand, when the voltage applied to the drain is higher than the breakdown voltage (V _av ), an ionization impact occurs at the interface where the p-type well and the drain drift region meet to form a plurality of electron-hole pairs, resulting in parasitic npn. The bipolar junction transistor npn-BJT is formed so that a large amount of current flows between the drain and the source. As a result, since the current does not flow below the breakdown voltage (V _av ) and flows smoothly only at higher voltages, it is possible to protect the integrated circuit by extinguishing unwanted ESD stress during electrostatic discharge. .

Recently, in order to increase the amount of electrostatic current that can be extinguished by the electrostatic protection circuit, an electrostatic protection circuit having a plurality of GG_DDDNMOS devices connected in parallel has been used.

However, when a parasitic npn-BJT is formed in the GG_DDDNMOS device and a large amount of current begins to flow, an extremely low resistive current path connecting the drain-channel-source region is formed along the surface of the device. There is this. This surface concentration phenomenon of the current acts as a factor to reduce the ability to respond to the electrostatic current of the GG-DDDNMOS device. In particular, since the electrical resistance of the current path is very low, the thermal breakdown voltage is smaller than that of the BJT active voltage, and as a result, a stable circuit configuration cannot be secured in constructing an electrostatic protection circuit with a plurality of GG_DDDNMOS devices.

4 shows voltage-current characteristics when the GG_DDDNMOS device operates as an electrostatic protection circuit. Compared with the basic characteristics of the electrostatic protection circuit shown in FIG. 1, the GG_DDDNMOS device is used as an electrostatic protection circuit. There is the same problem.

First, there is a possibility that the GG_DDDNMOS device may operate abnormally due to latch-up. That is, the snapback stop voltage (V _sh ) is less than the operating voltage (V _op ), and the BJT active current (I _tr ) is also very small (V _sh <V _op , I _tr ≒ 0 mA).

Second, in the GG_DDDNMOS device, the thermal breakdown voltage V _tb is smaller than the operating voltage V _op . Therefore, the GG_DDDNMOS device itself has a risk of being destroyed by the latch-up operation (V _tb <V _op ).

Third, the GG_DDDNMOS device is not strong enough against ESD stress current. That is, it is not possible to extinguish a sufficiently large amount of electrostatic current.

Fourth, GG_DDDNMOS element is open breakdown voltage (V _tb) is smaller than the active BJT voltage (V _tr). Therefore, when a static electricity protection circuit is composed of a plurality of GG_DDDNMOS devices, each device does not operate uniformly (V _tr > V _tb ).

In conclusion, in order to effectively configure an electrostatic protection circuit of a semiconductor integrated circuit operating at a high voltage, the voltage-current characteristic is improved by exhibiting a high breakdown voltage (V _av ) and at the same time improving the above-described problem of the GG_DDDNMOS device. There is a need to develop an electrostatic protection circuit that satisfies the conditions as shown in FIG.

An object of the present invention is to provide an electrostatic protection circuit that can flexibly cope with the required high voltage, while ensuring the characteristics that an electrostatic protection circuit should have.

An electrostatic protection circuit according to the present invention for achieving the above object comprises a first node to which a high voltage is applied, a second node to which a relatively low voltage is applied as compared to the first node, and between the first node and the second node. A plurality of NMOS transistors (first NMOS transistor to n-th NMOS transistor) are provided, and the plurality of NMOS transistors are connected in series.

The drain terminal of the first NMOS transistor is connected to a first node, and the gate and source terminals of the nth NMOS transistor are connected to a second node. In addition, the drain terminal of the first NMOS transistor is connected to the first node, the gate and source terminals of the n-th NMOS transistor are connected to the drain terminal of the n-th NMOS transistor, and the gate and source terminals of the n-th NMOS transistor are Is connected to the second node.

According to another feature of the present invention, an electrostatic protection circuit according to the present invention comprises a first n-type well (N-Well) to Nth defining a first NMOS transistor region to an Nth NMOS transistor region in a semiconductor substrate, respectively. N-wells are formed at regular intervals, and each of the n-well regions includes a low concentration p-well region and a low concentration n-well. ) And an active region and a well pickup region in the LP-Well region, the active region includes a gate electrode, a source region, and a drain region, and the well pickup region has a high concentration for LP-Well pickup. A p + diffusion layer (LP2) into which p-type impurity ions are implanted, a well pick-up region is provided in the LN-Well region, and a high concentration of n-type impurity ions for LN-Well pickup is provided in the well pickup region Injected n + diffusion layer (LN1) is provided, the first The drain D1 of the NMOS transistor and the n + diffusion layer LN1 for the LN-Well pickup are connected to the high voltage terminal V _H , and the gate G2, the source S2, and the LP-Well pickup of the second NMOS transistor are connected. The p + diffusion layer LP2 for is connected to the low voltage terminal V _L to which a relatively low voltage is applied in comparison to the high voltage terminal V _H.

P + diffusion layer LP1 for gate G1, source S1 and LP-Well pickup of the first NMOS transistor, and n + diffusion layer LN2 for drain D2 and LN-Well pickup of second NMOS transistor ) Are connected by common wiring.

A substrate between the n-type well (N-Well) and the n-type well (N-Well) is provided with a p-type well (HP-Well) implanted with a high concentration of p-type impurity ions, and is in the HP-Well region. A p + diffusion layer (HP) implanted with a high concentration of p-type impurity ions for HP-Well pickup is provided.

In addition, the p + diffusion layer HP for HP-Well pickup in the HP-Well region is connected to the _lowest voltage terminal V _lowest to which a relatively low voltage is applied as compared to the low voltage terminal V _L.

The static electricity protection circuit according to the present invention has the following effects.

According to the structure in which a plurality of GG_NMOS devices are arranged in series between a first node to which a relatively high voltage is applied and a second node to which a relatively low voltage is applied, the number of medium or low voltage GG_NMOS devices is selectively arranged so that It is possible to easily cope with the breakdown voltage required by the static electricity protection circuit.

In addition, all the problems raised by using the conventional GG_DDDNMOS device, that is, the BJT active current (I _tr ) and the extinguishing capacity of the electrostatic current is small, each device does not operate uniformly when using a plurality of GG_DDDNMOS device, etc. Will solve the problem.

1 is a reference diagram showing the optimum voltage-current characteristics of the static electricity protection circuit.

2 is a cross-sectional structure diagram of a GG_DDDNMOS device.

3A and 3B are reference diagrams showing a circuit connection of a static electricity protection circuit according to the prior art.

Figure 4 is a reference diagram showing the voltage-current characteristics of the electrostatic protection circuit according to the prior art.

5 is a circuit diagram of a static electricity protection circuit according to an embodiment of the present invention.

6 is a structural cross-sectional view of an electrostatic protection circuit according to an embodiment of the present invention.

7 is a circuit diagram of a static electricity protection circuit according to another embodiment of the present invention.

8 is a reference diagram showing the voltage-current characteristics of the electrostatic protection circuit according to an embodiment of the present invention.

Hereinafter, an electrostatic protection circuit according to the present invention will be described in detail with reference to the accompanying drawings. 5 is a circuit diagram illustrating an electrostatic protection circuit according to an embodiment of the present invention.

First, as shown in FIG. 5, the electrostatic protection circuit according to the exemplary embodiment of the present invention has a first node N1 to which a relatively high voltage V _H is applied and a second to which a relatively low voltage V _L is applied. A plurality of GG_NMOS elements (first Tr to nth Tr) are arranged in series between the nodes N2.

Each GG_NMOS device provided between the first and second nodes N1 and N2 may be configured as a low voltage or medium voltage GG_NMOS device. Thus, by appropriately arranging the low voltage or medium voltage GG_NMOS devices, the corresponding static electricity protection may be performed. It is possible to variably respond to the breakdown voltage required for the circuit. That is, the breakdown voltage required may be satisfied by selectively combining the low voltage and / or medium voltage GG_NMOS elements in the static electricity protection circuit requiring a specific breakdown voltage.

Meanwhile, in the plurality of GG_NMOS devices, that is, the first Tr to the nth Tr, the drain D of the first Tr is connected to the first node N1 of the high voltage and the gate / source G / of the nth Tr. S) is connected to the low voltage second node N2. In addition, the gate / source (G / S) of the first Tr, the drain (D) of the n-th Tr, and the gate / source / drain (G / S / D) terminals of the second Tr to n-th Tr are common. Is connected.

Looking at the structure of the electrostatic protection circuit according to an embodiment of the present invention configured as described above are as follows. 6 is a structural cross-sectional view of an electrostatic protection circuit according to an embodiment of the present invention. For reference, as described above, the electrostatic protection circuit according to the exemplary embodiment of the present invention is characterized in that a plurality of GG_NMOS devices are arranged in series. Hereinafter, for convenience of description, two GG_NMOS devices are arranged in series. Let's explain.

First, as shown in FIG. 6, n-wells are formed at predetermined intervals in the substrate, and each of the n-wells includes an electrostatic protection circuit according to an embodiment of the present invention. Each GG_NMOS device region to be configured is defined.

Referring to the structure of the GG_NMOS device in each of the n-type wells, an isolation layer 601 is provided in the field region of the substrate to define the active region and the well pickup region. The active region includes a gate electrode G1 (G2), a source region S1 (S2), and a drain region D1 (D2), and the well pick-up region is implanted with a high concentration of impurity ions for well pick-up. Well pick-up areas are provided.

Meanwhile, the n-type well (N-Well) provided with the GG_NMOS device is divided into a low concentration p-type well (LP-Well) region and a low concentration n-type well (LN-Well) region, and the LP-Well An active area and a well pick-up area are provided in the area, and only the well pick-up area is provided in the LN-Well area. Here, the well pick-up region of the LP-Well region is provided with a p + diffusion layer (LP1) (LP2) implanted with a high concentration of p-type impurity ions for LP-Well pick-up. The well pick-up region is provided with n + diffusion layers LN1 and LN2 implanted with a high concentration of n-type impurity ions for LN-Well pickup.

In the gate electrode, the source region and the drain region provided in the active region, the gate electrode structure may include a gate insulating layer 602 and a gate electrode 603 sequentially stacked on both sidewalls of the gate electrode 603. The spacer 604 may be formed, and a silicide layer 605 may be formed on the substrate surface of the source, drain, and drain regions of the gate electrode. High concentrations of n-type impurity ions are implanted into the source and drain regions.

In addition, a p-type well (HP-Well) implanted with a high concentration of p-type impurity ions is provided between the n-type well (N-Well) and the n-type well (N-Well), and the HP-Well region is provided. Inside, a p + diffusion layer (HP-Well Pick-up) implanted with a high concentration of p-type impurity ions for HP-Well pickup is provided.

The structure of the GG_NMOS device has been described above, and the circuit connection relationship of the GG_NMOS devices having such a structure as an electrostatic protection circuit is as follows.

First, as shown in FIG. 6, the drain D1 of the first GG_NMOS and the n + diffusion layer LN1 for picking up the LN-Well are connected to the high voltage terminal V _H and the gate G2 and the source of the second GG_NMOS. The p + diffusion layer LP2 for the S2 and the LP-Well pickup is connected to the low voltage terminal V _L. For reference, in the description of FIG. 5, the drain D of the first Tr is connected to the high voltage terminal V _H , and the gate G and the source S of the n th Tr are connected to the low voltage terminal V _L. 6 is described in addition to the above-described description of FIG. 5 in addition to the connection relationship of the diffusion layer for well pickup.

Meanwhile, the gate G1 of the first GG_NMOS, the source S1 and the p + diffusion layer LP1 for the LP-Well pickup, and the drain D2 of the second GG_NMOS and the n + diffusion layer LN2 for the LN-Well pickup It is connected by common wiring. In addition, the p + diffusion layer HP for HP-Well pickup provided in the HP-Well region is connected to the _lowest voltage terminal V _lowest .

In the above, the circuit configuration and the cross-sectional configuration of the static electricity protection circuit according to an embodiment of the present invention have been described. On the other hand, the above-described static electricity protection circuit of the present invention has been described with a focus on the case of applying a voltage of two sizes, the high voltage terminal (V _H ), the low voltage terminal (V _L ), the electrostatic protection circuit according to the present invention has a variety of sizes The same principle can be applied to a circuit to which a voltage of V is applied. The following description will be made with reference to FIG. 7.

In FIG. 7, a circuit in which four voltages Vgh, Vdd, Vss, and Vgl are applied is illustrated. An arrangement of an electrostatic protection circuit considering voltage differences between two specific voltage terminals among four voltage terminals is shown. This is a reference diagram for explanation. For reference, in Fig. 7, Vgh is 28V, Vdd is 2.5V, Vss is 0V, and Vgl is -20V.

The combination of two specific voltage terminals among the Vgh, Vdd, Vss, and Vgl voltage terminals may be variously derived, but as an example, a combination of Vgh and Vss voltage terminals, Vdd and Vgl voltage terminals, and Vss and Vgl voltage terminals will be described. do.

First, referring to the electrostatic protection circuit to be provided between the Vgh and Vss voltage terminals (see ① in FIG. 7), the voltage difference between the Vgh and Vss voltage terminals is 28V (= 28V-0V), so that the breakdown of (28V + ΔV) or more is achieved. There is a need for an electrostatic protection circuit having a voltage. Is the stability margin.

In order to satisfy the breakdown voltage of (28V + ΔV) or more, a plurality of GG_NMOS devices should be used as an electrostatic protection circuit. Each of the GG_NMOS devices may be a medium voltage GG_NMOS device (MV-NMOS) or a low voltage GG_NMOS device ( LV-NMOS), for example, it is assumed that the medium voltage GG_NMOS device has a breakdown voltage of 10V and the low voltage GG_NMOS device has a breakdown voltage of 6V.

Under this premise, by connecting three MV-NMOS (10V × 3) and one LV-NMOS (6V) in series (30V + 6V = 36V), electrostatic protection satisfies the breakdown voltage above (28V + ΔV). The circuit can be configured.

Next, referring to the static electricity protection circuit to be provided between the Vdd and Vgl voltage terminals (see ② in FIG. 7), the voltage difference between the Vgh and Vss voltage terminals is 22.5V (= 2.5V-(-20V)). In order to satisfy the breakdown voltage of (22.5V + ΔV) or more, three MV-NMOSs (10V × 3 = 30V) may be connected in series to configure an electrostatic protection circuit.

Finally, the electrostatic protection circuit to be provided between the Vss and Vgl voltage terminals (see ③ in FIG. 7) shows that the voltage difference between the Vss and Vss voltage terminals is 22.5V (= 2.5V-(-20V)). In order to satisfy the breakdown voltage of (22.5V + ΔV) or more, two MV-NMOS (10V × 2) and one LV-NMOS (6V) are connected in series (20V + 6V = 26V) to constitute an electrostatic protection circuit. can do.

On the other hand, the characteristics of the electrostatic protection circuit according to an embodiment of the present invention are as follows. 8 illustrates a voltage-current characteristic of an electrostatic protection circuit according to an embodiment of the present invention. Specifically, a GG-NMOS device having a breakdown voltage V _av of about 11 V and an active voltage V _tr of about 12 V is illustrated. The voltage-current characteristics of the four electrostatic protection circuits connected in series are shown.

As shown in FIG. 8, the active voltage (V _{tr_single} ) of each GG_NMOS device is about 12V, the snapback stop voltage (V _{sh_single} ) is about 7V, and the thermal breakdown voltage (V _{tb_single} ) is about 11V, which is used as an electrostatic protection circuit. It can be seen that it is suitable for (see the characteristics of the static electricity protection circuit of FIG. 1). In the case of four GG_NMOS devices connected in series, the active voltage (V _tr ) is about 48V, the snapback stop voltage (V _sh ) is about 28V, and the thermal breakdown voltage (V _tb ) is about 46V. Bar, it can be seen that the value is four times that of each characteristic value of a single GG_NMOS device, and it is effective in using an electrostatic protection circuit when the voltage difference between the high voltage terminal and the low voltage terminal is about 30 to 35V. It can be seen.

Claims (7)

delete delete delete The first n-type wells (N-Well) to N-th n-type wells (N-Well) defining first to Nth NMOS transistor regions, respectively, are formed in the semiconductor substrate at regular intervals. , Each n-well region is divided into a low concentration p-well region and a low concentration n-well region. An active region and a well pick-up region are provided in the LP-Well region. The active region includes a gate electrode, a source region, and a drain region, and the well pick-up region has a high concentration of p-type impurity ions for LP-Well pickup. The injected p + diffusion layer LP2 is provided, Only the well pick-up area is provided in the LN-Well area, and the well pick-up area is provided with an n + diffusion layer LN1 into which a high concentration of n-type impurity ions are implanted for LN-Well pick-up. The drain D1 of the first NMOS transistor and the n + diffusion layer LN1 for LN-Well pickup are connected to the high voltage terminal V _H , and the gate G2, the source S2, and the LP of the second NMOS transistor are connected. And a p + diffusion layer (LP2) for pick-up is connected to a low voltage terminal (V _L ) to which a relatively low voltage is applied relative to the high voltage terminal (V _H ). 5. The PN diffusion layer LP1 for the gate G1, the source S1, and the LP-Well pickup of the first NMOS transistor, and the drain D2 and the LN-Well pickup of the second NMOS transistor. N + diffusion layer (LN2) for the static electricity protection circuit, characterized in that connected by a common wiring. The substrate between the n-type well (N-Well) and the n-type well (N-Well) is provided with a p-type well (HP-Well) implanted with a high concentration of p-type impurity ions, And a p + diffusion layer (HP) implanted with a high concentration of p-type impurity ions for HP-Well pickup in the HP-Well region. The method of claim 6, wherein the p + diffusion layer HP for HP-Well pickup in the HP-Well region is at the lowest voltage terminal (V _lowest ) to which a relatively low voltage is applied as compared to the low voltage terminal (V _L ). Electrostatic protection circuit, characterized in that connected.