JP7126471B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device and, for example, to a technique effectively applied to a semiconductor device including a protection element that protects an internal circuit from electrostatic breakdown.

Japanese Patent Laying-Open No. 2008-78354 (Patent Document 1) discloses an internal circuit arranged in the central portion of a semiconductor chip, a plurality of input/output cells arranged around the internal circuit, and an outer peripheral portion of the semiconductor chip. A semiconductor device is disclosed that includes a plurality of arranged pads.

Japanese Patent Application Laid-Open No. 2008-78354

The input/output cell is provided with a protective element that protects the internal circuit from electrostatic breakdown.

In the semiconductor device under study by the inventor of the present application, one protection element is composed of a plurality of unit transistors connected in parallel. As the miniaturization of semiconductor devices advances, the resistance to static electricity of individual unit transistors decreases, making them more susceptible to thermal destruction. As will be described later, it has been found that if a specific unit transistor constituting one protective element is thermally destroyed, it becomes impossible to ensure sufficient resistance to static electricity as a protective element, and the reliability of the semiconductor device decreases.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A semiconductor device according to one embodiment includes an input/output pad electrode, a protection element formed in a p-type well region, an n-type well region arranged to surround the p-type well region, and a and an n-type guard ring arranged to surround the p-type well region, a first power supply potential wiring, a second power supply potential wiring, and a reference potential wiring. The protection element is composed of a plurality of n-type unit transistors arranged in a matrix. The drain region of the n-type unit transistor is connected to the input/output pad electrode, and the source region is connected to the reference potential wiring. In the input/output cell CL1, the n-type guard ring is connected to the second power supply potential wiring, but is not connected to the first power supply potential wiring.

According to one embodiment, reliability of a semiconductor device can be improved.

1 is a plan view of a semiconductor device according to an embodiment; FIG. FIG. 11 is a plan view of an input/output cell of a semiconductor device of a study example; 3 is a cross-sectional view taken along line X1-X1 in FIG. 2; FIG. 3 is a cross-sectional view taken along line X2-X2 of FIG. 2; FIG. 3 is a cross-sectional view taken along line X3-X3 of FIG. 2; FIG. FIG. 10 is an equivalent circuit diagram of a principal part of a semiconductor device of a study example; FIG. 10 is an operation explanatory diagram of the semiconductor device of the study example; 2 is a plan view of an input/output cell of the semiconductor device of the present embodiment; FIG. FIG. 9 is a cross-sectional view taken along line X4-X4 in FIG. 8; FIG. 4 is an operation explanatory diagram of the semiconductor device of the present embodiment; 10 is an equivalent circuit diagram of a main part of the semiconductor device of Modification 1; FIG. FIG. 11 is a plan view of an input/output cell of a semiconductor device of Modification 1; 13 is a cross-sectional view taken along line X5-X5 of FIG. 12; FIG. FIG. 3 is a cross-sectional view of a semiconductor device of a comparative example; FIG. 11 is a plan view of an input/output cell of a semiconductor device of modification 2; 16 is a cross-sectional view taken along line X6-X6 of FIG. 15; FIG. FIG. 11 is a cross-sectional view of a semiconductor device of Modification 3;

For the sake of convenience, the following embodiments are divided into a plurality of sections or embodiments when necessary, but unless otherwise specified, they are not independent of each other, and one There is a relationship of part or all of the modification, details, supplementary explanation, etc.

In addition, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), when it is particularly specified, when it is clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., unless otherwise explicitly stated or in principle clearly considered to be otherwise, It shall include those that approximate or resemble the shape, etc. This also applies to the above numerical values and ranges.

In addition, in all the drawings for explaining the embodiments, the same members are basically given the same reference numerals, and repeated description thereof will be omitted. In order to make the drawing easier to understand, even a plan view may be hatched.

In the p-channel transistor PMOS and the n-channel transistor NMOS, one of the semiconductor regions arranged on both sides of the gate electrode is called the source region and the other is called the drain region for convenience. It may be reversed.

(Embodiment)
FIG. 1 is a plan view of the semiconductor device of this embodiment. As shown in FIG. 1, the semiconductor device includes an internal circuit region RIT, multiple cells CL, and multiple pad electrodes (terminals) PD. An internal circuit region RIT is arranged in the central portion of the main surface SUBa of the semiconductor substrate SUB, and a plurality of cells CL are arranged around the internal circuit region RIT so as to surround the internal circuit region RIT. A plurality of pad electrodes PD are arranged on the outer peripheral portion of the main surface SUBa so as to surround the plurality of cells CL.

An internal circuit ITC composed of a p-channel transistor PMOS and an n-channel transistor NMOS (not shown) is formed in the internal circuit region RIT, and the internal circuit ITC is supplied with a power supply potential and a reference potential for the internal circuit. A power supply potential wiring (internal power supply potential wiring) VDDL and a reference potential wiring (internal reference potential wiring) GNDL are connected.

Power supply potential lines VDD1 and VDD2 and reference potential lines GND1 and GND2 are arranged over a plurality of cells CL in the outer peripheral portion of the internal circuit region RIT. Power supply potential wirings VDD1 and VDD2 and reference potential wirings GND1 and GND2 are wirings for supplying input/output power supply potentials and reference potentials to each cell CL, and extend to cross each cell. The power supply potential wirings VDD1 and VDD2 as well as the reference potential wirings GND1 and GND2 are arranged in a ring. They are arranged in the order of the potential wiring GND2.

The plurality of pad electrodes PD include input pad electrodes PD1 and PD2, power supply potential pad electrode PVD and reference potential pad electrode PDG. A plurality of cells CL includes input/output cells CL1 and CL2 and power supply cell CLP.

Input/output cell CL1 includes a protection element area RA in which protection element ESD1 is arranged and a logic circuit area (input/output logic circuit area) RB in which logic circuit (input/output logic circuit) ESL1 is arranged. Similarly, the input/output cell CL2 includes a protection element area RA in which the protection element ESD2 is arranged and a logic circuit area (input/output logic circuit area) RB in which the logic circuit (input/output logic circuit) ESL2 is arranged. A power clamp circuit PC is arranged in the power supply cell CLP. In power supply cell CLP, power supply potential lines VDD1 and VDD2 are directly connected to each other, and reference potential lines GND1 and GND2 are also directly connected to each other. Here, direct connection means connection through a conductor layer, wiring, or the like without interposing a switch element therebetween. It should be noted that a simple connection means a direct connection.

Next, with reference to FIGS. 2 to 7, room for improvement in the studied example will be described. The study example is a technology having a problem discovered by the inventor of the present application, but is not a known technology. Also, in the embodiments described later, the description of the parts common to the study example will be omitted. That is, the explanation of the study example can be substituted for the explanation of the common part. 2 is a plan view of the input/output cell CL1 of the semiconductor device of the study example, FIG. 3 is a cross-sectional view along X1-X1 in FIG. 2, FIG. 4 is a cross-sectional view along X2-X2 in FIG. FIG. 6 is a cross-sectional view taken along line X3-X3 of FIG. 2, FIG. 6 is an equivalent circuit diagram of the essential parts of the semiconductor device of the study example, and FIG. 7 is an operation explanatory diagram of the semiconductor device of the study example.

As shown in FIG. 2, the input/output cell CL1 includes a protection element ESD1 and a logic circuit ESL1, and the logic circuit ESL1 is composed of a plurality of p-channel transistors PMOS and a plurality of n-channel transistors NMOS. The protection element ESD1 and the plurality of n-channel transistors NMOS are formed in a p-type well region (p-type semiconductor region) PW, and the plurality of p-channel transistors PMOS are formed in the n-type well region (n-type semiconductor region) It is formed in NW.

The protection element ESD1 is composed of a plurality of n-type unit transistors UTN. A plurality of n-type unit transistors UTN are arranged in a grid pattern in the X and Y directions. The protection element ESD1 is surrounded by a p-type guard ring (p-type semiconductor region) PH formed in a ring shape with a predetermined width. The p-type guard ring PH is formed in the p-type well region PW and is a region for supplying a reference potential to the p-type well region PW. The p-type guard ring PH is connected to the reference potential wiring GND1 at the power supply part PFD3, and the reference potential is supplied to the p-type well region PW via the power supply part PFD3.

The n-type unit transistor UTN includes a gate electrode GE, an n-type drain region (n-type semiconductor region) ND and an n-type source region (n-type semiconductor region) NS arranged on both sides of the gate electrode GE. ND is connected to the input/output pad electrode PD1, and the n-type source region NS is connected to the reference potential wiring GND1. A plurality of n-type unit transistors UTN are arranged in a matrix in the X and Y directions and connected in parallel with each other. That is, when the protective element ESD1 is composed of m n-type unit transistors UTN, the current resistance of the protective element ESD1 is m times the current resistance of the n-type unit transistor UTN.

The n-channel transistor NMOS also includes a gate electrode GE, an n-type drain region (n-type semiconductor region) ND and an n-type source region (n-type semiconductor region) NS arranged on both sides of the gate electrode GE. As shown in FIGS. 5 and 6, the source region NS of the n-channel transistor NMOS forming the logic circuit ESL1 is connected to the reference potential wiring GND2. A linear p-type guard ring PH is arranged between the n-channel transistor NMOS and the ring-shaped p-type guard ring PH. The linear p-type guard ring PH is connected to the reference potential wiring GND2 at the power supply portion PFD4. The linear p-type guard ring PH may have a ring shape surrounding a plurality of n-channel transistors NMOS.

The p-channel transistor PMOS also includes a gate electrode GE, and p-type drain regions (p-type semiconductor regions) PDN and p-type source regions (n-type semiconductor regions) PS arranged on both sides of the gate electrode GE. As shown in FIGS. 4 and 6, the source region PS of the p-channel transistor PMOS forming the logic circuit ESL1 is connected to the power supply potential wiring VDD2.

An n-type guard ring NH for supplying a power supply potential to the n-type well region NW is formed in the n-type well region NW, and the n-type guard ring NH is connected to the power supply potential wiring VDD1 at the power supply portion PFD1. , and is connected to the power supply potential wiring VDD2 at the power supply portion PFD2.

In plan view, the n-type guard ring NH is provided in a ring shape so as to surround the protective element ESD1, the p-type guard ring PH, the n-channel transistor NMOS and the p-channel transistor PMOS.

The power feeding portion PFD1 is located at the intersection (in other words, overlapping region) between the n-type guard ring NH and the power supply potential wiring VDD1, and the power feeding portion PFD2 is located at the intersection (in other words, the overlapping region) between the n-type guard ring NH and the power supply potential wiring VDD2. , overlapping regions). In addition, the power supply part PFD3 is located at the intersection (in other words, overlapping area) between the p-type guard ring PH and the reference potential wiring GND1, and the power supply part PFD4 is located at the intersection (in other words, overlapping area) between the p-type guard ring PH and the reference potential wiring GND2. In other words, it is arranged in the overlapping area).

Further, as shown in FIG. 2, the power supply potential wiring VDD1 and the reference potential wiring GND1 are arranged on the protection element ESD1 so as to overlap the protection element ESD1. The power supply potential wiring VDD2 and the reference potential wiring GND2 are arranged on the logic circuit ESL1 so as to overlap with the logic circuit ESL1. Specifically, the power supply potential wiring VDD2 is arranged on the p-channel transistor PMOS so as to overlap the p-channel transistor PMOS, and the reference potential wiring GND2 is arranged on the n-channel transistor NMOS. It is arranged so as to overlap with the transistor NMOS.

As shown in FIG. 3, the n-type unit transistor UTN forming the protection element ESD1 is formed in the p-type well region PW. The p-type well region PW is formed in the p-type semiconductor substrate SUB via an n-type deep well region (n-type well region, n-type semiconductor region) DNW. The p-type well region PW is surrounded by an n-type well region NW (see FIG. 2), and the n-type well region NW extends from the main surface SUBa in the depth direction of the semiconductor substrate SUB. , reaches the n-type deep well region DNW. That is, the p-type well region PW is electrically isolated from the semiconductor substrate SUB by the n-type well region NW and the n-type deep well region DNW.

A p-type guard ring PH is formed in the p-type well region PW, and an n-type guard ring NH is formed in the n-type well region NW. In addition, over the main surface SUBa of the semiconductor substrate SUB, a plurality of layers of insulating films (interlayer insulating films) IL1 to IL6, a plurality of layers of metal wirings M1 to M3, and a plurality of layers of plug electrodes PG1 to PG3 are provided. Here, three layers of metal wiring will be described as an example, but four or more layers of metal wiring may be used. Metal wirings M1-M3 are made of aluminum or copper, and plug electrodes PG1-PG3 are made of tungsten, copper, or the like.

As shown in FIG. 3, in the power supply portion PFD1, the n-type guard ring NH is connected to the power supply potential wiring VDD1 through the plug electrode PG1, the metal wiring M1, the plug electrode PG2, the metal wiring M2 and the plug electrode PG3 in this order. ing.

The n-type unit transistor UTN is arranged on both sides of the gate electrode GE formed on the main surface SUBa of the semiconductor substrate SUB via the gate insulating film GI and on both sides of the gate electrode GE within the p-type well region PW. an n-type drain region ND and an n-type source region NS. A silicide layer SIL is formed on the n-type drain region ND and the n-type source region NS. A silicide layer SIL is also formed on the p-type guard ring PH and the n-type guard ring NH. A metal wiring M1 is connected to the n-type drain region ND via a plug electrode PG1, and the metal wiring M1 is connected to the input/output pad electrode PD1. A metal wiring M1 is connected to the n-type source region NS via a plug electrode PG1, and the metal wiring M1 is connected to a reference potential wiring GND1.

An element isolation film STI is formed between the n-type unit transistor UTN and the p-type guardrin PH to electrically isolate them. A device isolation film STI is also formed between the p-type guardrin PH and the n-type guardrin NH to electrically isolate them.

As shown in FIG. 4, the p-channel transistor PMOS forming the logic circuit ESL1 is formed in the n-type well region NW. The n-type well region NW is formed in a p-type semiconductor substrate SUB, and a deep well region DNW is interposed between the n-type well region NW and the p-type semiconductor substrate SUB.

The p-channel transistor PMOS is arranged on both sides of the gate electrode GE formed on the main surface SUBa of the semiconductor substrate SUB via the gate insulating film GI and on both sides of the gate electrode GE within the n-type well region NW. a p-type drain region PDN and a p-type source region PS. A silicide layer SIL is formed on the p-type drain region PDN and the p-type source region PS. Also, the p-type source region PS is connected to the power supply potential wiring VDD2 through the plug electrode PG1, the metal wiring M1, the plug electrode PG2, the metal wiring M2 and the plug electrode PG3 in this order.

As shown in FIG. 5, the n-channel transistor NMOS forming the logic circuit ESL1 is formed in the p-type well region PW. The p-type well region PW is electrically isolated from the semiconductor substrate SUB by the n-type well region NW and the n-type deep well region DNW.

The n-channel transistor NMOS is arranged on both sides of the gate electrode GE formed on the main surface SUBa of the semiconductor substrate SUB via the gate insulating film GI and on both sides of the gate electrode GE within the p-type well region PW. an n-type drain region ND and an n-type source region NS. A silicide layer SIL is formed on the n-type drain region ND and the n-type source region NS. Also, the n-type source region NS is connected to the reference potential wiring GND2 via the plug electrode PG1, the metal wiring M1, the plug electrode PG2, the metal wiring M2 and the plug electrode PG3 in order.

As shown in FIG. 6, for example, a signal input from the outside of the semiconductor device to the input/output pad electrode PD1 is transferred to the internal circuit ITC via the logic circuit ESL1 and the level shift circuit LS. The logic circuit ESL1 is composed of a p-channel transistor PMOS and an n-channel transistor NMOS. The p-channel transistor PMOS is connected to the power supply potential wiring VDD2, and the n-channel transistor NMOS is connected to the reference potential wiring GND2. It is The power supply potential wiring VDD2 is connected to the power supply potential wiring VDD1, and the power supply potential pad electrode PDV is connected to the power supply potential wiring VDD1. The reference potential wiring GND2 is connected to the reference potential wiring GND1, and the reference potential pad electrode PDV is connected to the reference potential wiring GND1.

Also, the internal circuit ITC is connected to the power supply potential wiring VDDL and the reference potential wiring GNDL. The power supply potential VL applied to the power supply potential wiring VDDL is lower than the power supply potential VH applied to the power supply potential wirings VDD1 and VDD2. VL is 1.2 [V].

A protective element ESD1 is connected between the input/output pad electrode PD1 and the reference potential wiring GND1. The protective element ESD1 is provided, for example, to prevent the internal circuit ITC from being destroyed by electrostatic discharge (hereinafter referred to as "surge") entering from the input/output pad electrode PD1 of the semiconductor device. In the input/output cell CL1, the protection element ESD1 is provided between the input/output pad electrode PD1 and the reference potential wiring GND1, but is not provided between the input/output pad electrode PD1 and the power supply potential wiring VDD1. .

A power clamp circuit PC is connected between the power supply potential wiring VDD1 and the reference potential wiring GND1. The power clamp circuit PC has a function of short-circuiting between the power supply potential wiring VDD1 and the reference potential wiring GND1, for example, when a surge enters the input/output pad electrode PD1.

For example, when a surge enters the input/output pad electrode PD1 with reference to the power supply potential pad electrode PDV, the internal circuit ITC and the like can be protected by flowing current through the current path I1 shown in FIG. The surge entering the input/output pad electrode PD1 passes through the protective element ESD1, the reference potential wiring GND1, the power clamp circuit PC, and the power supply potential wiring VDD1 in order to the power supply potential pad electrode PDV. Current path I1 is the original current path.

Next, with reference to FIG. 7, the room for improvement of the study example clarified by the studies of the inventors of the present application will be described. In the equivalent circuit diagram shown in FIG. 7, an NPN-type parasitic transistor BiP1 is composed of an n-type drain region ND and an n-type source region NS of an n-type unit transistor UTN, and a p-type well region PW. Transistor BiP2 is composed of an n-type drain region ND, an n-type well region NW and a p-type well region PW.

First, the original current path I1 will be described. When a surge enters the input/output pad electrode PD1, the PN junction between the n-type drain region ND of the n-type unit transistor and the p-type well region PW breaks down, and a breakdown current flows into the p-type well region PW. Then, when the base potential of the parasitic transistor BiP1 rises due to the parasitic resistance R1 of the p-type well region PW and exceeds the threshold voltage Vbe, current flows between the collector and the emitter of the parasitic transistor BiP1. That is, the surge entering the input/output pad electrode PD1 passes through the protection element ESD1, the reference potential wiring GND1, the power clamp circuit PC, and the power supply potential wiring VDD1 to the power supply potential pad electrode PDV.

According to the study of the inventor of the present application, it has been found that an unexpected current path I2 occurs in addition to the original current path I1. That is, when the breakdown current causes the base potential of the parasitic transistor BiP2 to rise and exceed the threshold voltage Vbe, current flows from the input/output pad electrode PD1 to the power supply potential pad electrode PDV via the parasitic transistor BiP2. As the n-type unit transistor UTN is miniaturized, the current resistance of the n-type unit transistor UTN is reduced. flowed, and the n-type unit transistor UTN was thermally destroyed.

Further, the thermal breakdown occurs in the n-type unit transistor UTN arranged close to the input/output pad electrode PD1 and the power supply portion PFD1 of the power supply potential wiring VDD1 among the plurality of n-type unit transistors UTN shown in FIG. It turned out to do. In the case of the n-type unit transistor UTN close to the power supply part PFD1, it is presumed that the base potential of the parasitic transistor BiP2 easily exceeds the threshold voltage Vbe because the parasitic resistance connected to the emitter of the parasitic transistor BiP2 is small. .

If a part of the plurality of n-type unit transistors UTN that constitute the protective element ESD1 is destroyed, the current resistance of the protective element ESD1 is lowered, so that it becomes impossible to prevent the internal circuit ITC from being destroyed by a surge, and the reliability of the semiconductor device is improved. decreases.

The present embodiment is designed to address the room for improvement described above, and the details thereof will be described below. 8 is a plan view of the input/output cell CL1 of the semiconductor device of this embodiment, FIG. 9 is a cross-sectional view taken along line X4-X4 in FIG. 8, and FIG. 10 is an operation explanatory diagram of the semiconductor device of this embodiment. be.

As shown in FIG. 8, the input/output cell CL1 includes a protective element ESD1, a p-type guard ring PH surrounding the protective element ESD1 in plan view, an n-channel transistor NMOS and a p-channel transistor for the logic circuit ESL1. and an n-type guard ring NH surrounding the protection element ESD1 and the n-channel transistor NMOS and the p-channel transistor PMOS in plan view. The input/output cell CL1 is different from the input/output cell CL1 of the study example in that the power supply portion PFD1 is not provided at the intersection between the n-type guard ring NH and the power supply potential wiring VDD1. For the sake of convenience, the intersecting portion between the n-type guard ring NH and the power supply potential wiring VDD1, where the power supply portion PFD1 is arranged in the study example, will be referred to as the A portion. That is, in the input/output cell CL1 of the semiconductor device of this embodiment, the n-type guard ring NH is not connected to the power supply potential wiring VDD1. However, the n-type guard ring NH is connected to the power supply potential wiring VDD2 at the power supply portion PFD2 arranged away from the protection element ESD1 and the A portion. For example, the size of the input/output cell CL1 is about 50 μm in the X direction and about 60 to 80 μm in the Y direction.

As shown in FIG. 9, the A portion and the power supply portion PFD2 are connected by a laminated structure of an n-type well region NW, an n-type guard ring NH and a silicide layer SIL. In the power supply portion PFD2, the n-type well region NW, the n-type guard ring NH and the silicide layer SIL are connected to the power supply potential wiring VDD2.

That is, as shown in FIG. 10, the wiring resistance R2 is inserted between the A portion and the power feeding portion PFD2. Here, the wiring resistance R2 can be regarded as the wiring resistance of the silicide layer SIL from the A portion to the power feeding portion PFD2. This is because when the resistivities of the n-type well region NW, the n-type guard ring NH, and the silicide layer SIL constituting the laminated structure are represented by r1, r2, and r3, respectively, the relationship r3<<r1, r2 holds. is. For example, the wiring resistance R2 can be about 10 [Ω].

As shown in FIG. 10, since the wiring resistor R2 is connected in series with the emitter of the parasitic transistor BiP2, the base potential of the parasitic transistor BiP2 exceeds the threshold Vbe even if a breakdown current flows through the p-type well region PW. can prevent That is, it is possible to prevent the current from flowing from the input/output pad electrode PD1 to the power supply potential pad electrode PDV through the unexpected current path I2. Therefore, it is possible to prevent thermal destruction of the n-type unit transistor UTN arranged in the vicinity of the portion A and the input/output pad electrode PD1 shown in FIG. In addition, since it is possible to prevent a decrease in current resistance of the protection element ESD1 due to thermal breakdown of a part of the n-type unit transistor UTN, the reliability of the semiconductor device can be improved.

<Modification 1>
Modification 1 is a modification of the above-described embodiment. FIG. 11 is an equivalent circuit diagram of the main part of the semiconductor device of Modification 1, and FIG. A plan view and FIG. 13 are sectional views taken along line X5-X5 of FIG. Modification 1 is an example in which an input/output cell CL2 including a protection element ESD2 having a CMOS structure is arranged adjacent to the input/output cell CL1, as shown in FIGS.

As shown in FIG. 11, the input/output cell CL2 includes a logic circuit ESL2 composed of a p-channel transistor PMOS and an n-channel transistor NMOS, and a protective element composed of an n-type unit transistor UTN and a p-type unit transistor UTP. ESD2. For example, a signal input to the input/output pad electrode PD2 from the outside of the semiconductor device is transferred to the internal circuit ITC via the logic circuit ESL2 and the level shift circuit LS in order.

A protection element ESD2 composed of an n-type unit transistor UTN is connected between the input/output pad electrode PD2 and the reference potential wiring GND1, and a p-type unit transistor is connected between the input/output pad electrode PD2 and the power supply potential wiring VDD1. A protection element ESD2 made of UTP is connected.

As shown in FIG. 12, the input/output pad electrode PD2 is connected to the input/output cell CL2, and the input/output pad electrode PD2 is adjacent to the input/output pad electrode PD1 in the X direction. It is adjacent to the input/output cell CL1. Adjacent here means that no other pad electrode is inserted between the two pad electrodes or that no other cell is inserted between the two input/output cells.

As shown in FIG. 12, the protection element ESD2 includes a p-type protection element ESD2 composed of a plurality of p-type unit transistors UTP and an n-type protection element ESD2 composed of a plurality of n-type unit transistors UTN. include. The p-type protection element ESD2 and the n-type protection element ESD2 may be composed of a plurality of p-type unit transistors UTP and a plurality of n-type unit transistors UTN arranged in a matrix in the X and Y directions, respectively. good.

A plurality of p-type unit transistors UTP are provided within an n-type well region NW, and an n-type guard ring NH surrounding the plurality of p-type unit transistors UTP is formed within the n-type well region NW. A power supply portion PFD5 is provided at the intersection of the n-type guard ring NH and the power supply potential wiring VDD1. In the power supply portion PFD5, the n-type guard ring NH is connected to the power supply potential wiring VDD1.

A plurality of n-type unit transistors UTN are provided in the p-type well region PW, and a p-type guard ring PH surrounding the plurality of n-type unit transistors UTN is formed in the p-type well region PW. A power feeding portion PFD3 is provided at the intersection of the p-type guard ring PH and the reference potential wiring GND1. In the power feeding portion PFD3, the p-type guard ring PH is connected to the reference potential wiring GND1. An n-channel transistor NMOS that forms the logic circuit ESL2 is also formed in the p-type well region PW.

Further, an n-type well region NW is arranged so as to surround the p-type well region PW, and in the n-type well region NW, there are a plurality of p-type unit transistors UTP and p A channel type transistor PMOS is also formed. Furthermore, in the n-type well region NW, there are provided a p-type guard ring PH and an n-type guard ring NH surrounding the p-channel transistor PMOS and the n-channel transistor nMOS that constitute the logic circuit ESL2, The n-type guard ring NH is connected to the power supply potential wiring VDD2 in the power supply portion PFD2.

As shown in FIG. 13, a deep well region DNW is provided under the n-type well region NW included in the input/output cell CL2. Also, the n-type guard ring NH of the A portion of the input/output cell CL1 and the n-type guard ring NH of the power supply portion PFD5 of the input/output cell CL2 are electrically connected by the n-type well region NW.

Therefore, in order to prevent the current from flowing through the unexpected current path I2 in the study example, it is essential to separate the power supply portion PFD5 of the input/output cell CL2 from the portion A of the input/output cell CL1 by a desired distance D. is. In other words, it is necessary to separate the n-type guard ring NH of the input/output cell CL2 by a desired distance D from the n-type guard ring NH of the input/output cell CL1 under the power supply potential wiring VDD1.

That is, the wiring resistance R3 of the n-type well region NW from the n-type guard ring NH of the input/output cell CL1 to the n-type guard ring NH of the input/output cell CL2 is transferred from the A portion to the power supply portion PFD2 described with reference to FIG. It is important to make the wiring resistance higher than the wiring resistance R2 of the silicide layer SIL. Since the resistivity of the n-type well region NW is higher than that of the silicide layer SIL, the distance D can be made smaller than the distance from the portion A to the power supply portion PFD2 in FIGS. Incidentally, the distance D can be set to about 10 μm.

<Modification 2>
Modification 2 is a modification of the above-described embodiment, and is an example in which an input/output cell CL2 including a protection element ESD2 having a CMOS structure is arranged adjacent to the input/output cell CL1 as in the above modification 1. be. 14 is a cross-sectional view of a semiconductor device of a comparative example, FIG. 15 is a plan view of a semiconductor device of Modification 2, and FIG. 16 is a cross-sectional view taken along line X6-X6 of FIG.

As shown in FIG. 14, when the input/output cell CL2 including the protection element ESD2 of the CMOS structure is arranged adjacent to the input/output cell CL1, in other words, the n-type that forms the protection element ESD1 of the input/output cell CL1 When unit transistor UTN and p-type unit transistor UTP forming protection element ESD2 of input/output cell CL2 are arranged adjacent to each other, a thyristor structure including parasitic transistors BiP3 and BiP4 is formed in the semiconductor device. Then, a latch-up phenomenon may occur in which a current continues to flow from the power supply potential pad electrode PDV toward the reference potential pad electrode PDG.

The PNP parasitic transistor BiP3 has an emitter at the p-type source region PS of the p-type unit transistor UTP of the input/output cell CL2, a collector at the p-type well region PW in which the n-type unit transistor UTN of the input/output cell CL1 is formed, and an input. The n-type well region NW in which the p-type unit transistor UTP of the output cell CL2 is formed is used as the base. The NPN-type parasitic transistor BiP4 has a collector at the n-type well region NW in which the p-type unit transistor UTP of the input/output cell CL2 is formed, and an emitter at the n-type source region NS of the n-type unit transistor UTN of the input/output cell CL1. , the p-type well region PW in which the n-type unit transistor UTN of the input/output cell CL1 is formed is the base.

When power supply potential is supplied to the n-type guard ring NH from the power supply potential wiring VDD2, a wiring resistance R2 is interposed between the portion A and the power supply portion PFD2. On the other hand, the p-type source region PS of the p-type unit transistor UTP and the n-type gate ring NH are supplied with the power supply potential from the power supply potential wiring VDD1 arranged thereon. Due to the influence of this wiring resistance R2, a potential difference is likely to occur between the p-type source region PS of the p-type unit transistor UTP (the emitter of the parasitic transistor BiP3) and the n-type well region NW (the base of the parasitic transistor BiP3). Then, a base current of the parasitic transistor BiP3 is generated and the parasitic transistor BiP3 is turned on. When the parasitic transistor BiP3 turns on, the collector current of the parasitic transistor BiP3 raises the base potential of the parasitic transistor BiP4, which turns on the parasitic transistor BiP4, causing a latch-up phenomenon.

As shown in FIGS. 15 and 16, in the semiconductor device of Modification 2, a p-type well region PW is provided between input/output cells CL1 and CL2, and an n-type well region NW of input/output cell CL1 and input/output cell CL2 are provided. from the n-type well region NW. Furthermore, a p-type guard ring PH is provided on the surface of the p-type well region PW, and is connected to the reference potential pad electrode PDG to supply the reference potential to the p-type guard ring PH. Note that the n-type well region NW of the input/output cell CL1 and the n-type well region NW of the input/output cell CL2 may be separated by the p-type semiconductor substrate SUB without providing the p-type well region PW.

With such a configuration, even if the PNP-type parasitic transistor BiP3 is turned on, the collector current of the parasitic transistor BiP3 is transferred to the reference potential pad electrode PDG through the p-type well region PW and the p-type guard ring PH. Therefore, the occurrence of the latch-up phenomenon can be prevented.

<Modification 3>
Modification 3 is a modification of the above embodiment. FIG. 17 is a cross-sectional view of a semiconductor device of Modification 3. FIG. Modification 3 is an example of reducing the wiring resistance R2 of the above embodiment.

As shown in FIG. 17, a metal wiring M1 is arranged along the n-type guard ring NH from the A portion to the power feeding portion PFD2. It is connected to the type guard ring NH. Compared with the specific resistance r3 of the silicide layer SIL, the specific resistance r4 of the metal wiring M1 is about one digit lower, and can be regarded as r4<<r3. That is, by forming a layered structure in which the silicide layer SIL and the metal wiring M1 are connected in parallel between the A portion and the power feeding portion PFD2, the wiring resistance R4 between the A portion and the power feeding portion PFD2 can be reduced by the above wiring. It can be reduced more than the resistance R2.

Therefore, the potential difference between the A portion and the power supply portion PFD2 can be reduced as compared with the above-described embodiment, so that the occurrence of the latch-up phenomenon described in Modification 2 can be suppressed.

Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist of the invention. Needless to say.

In addition, part of the content described in the above embodiment will be described below.
[Appendix 1]
a first conductivity type semiconductor substrate having a main surface;
a first pad electrode and a second pad electrode formed on the main surface;
a first input/output cell formed on the main surface and connected to the first pad electrode and a second input/output cell connected to the second pad electrode;
a first power supply potential wiring arranged to intersect the first input/output cell and the second input/output cell and supplying a power supply potential to the second input/output cell;
a second power supply potential wiring arranged to cross the first input/output cell and the second input/output cell and supplying the power supply potential to the first input/output cell and the second input/output cell;
a first reference potential wiring that supplies a reference potential to the first input/output cell and the second input/output cell;
an internal circuit region formed on the main surface and arranged on the opposite side of the first pad electrode and the second pad electrode with respect to the first input/output cell and the second input/output cell;
with
The first input/output cell is
a first well region of the first conductivity type formed in the semiconductor substrate;
a second well region of a second conductivity type, which is a conductivity type different from the first conductivity type, formed in the semiconductor substrate and arranged to surround the first well region in plan view;
a third well region of the second conductivity type formed in the semiconductor substrate, in contact with the second well region, and arranged between the first well region and the semiconductor substrate in a cross-sectional view;
a first protection element formed in the first well region;
a first guard ring of the second conductivity type formed in the second well region and arranged to surround the first well region in plan view;
including
The second input/output cell is
a second protection element formed in the second well region;
a second conductivity type second guard ring formed in the second well region and surrounding the second protection element in plan view;
including
The first power supply potential wiring, the second power supply potential wiring and the first reference potential wiring are arranged on the first input/output cell and the second input/output cell and extend in the first direction of the main surface. exist,
In a second direction intersecting the first direction, the first power supply potential wiring is arranged closer to the first pad electrode and the second pad electrode than the second power supply potential wiring,
The first protection element is composed of a plurality of first transistors,
The first transistor is
a first gate electrode formed on the main surface of the semiconductor substrate with a first gate insulating film interposed therebetween;
the first semiconductor region of the second conductivity type and the second semiconductor region of the second conductivity type arranged in the first well region on both sides of the first gate electrode;
including
The second protection element is composed of a plurality of second transistors,
the second transistor,
a second gate electrode formed on the main surface of the semiconductor substrate with a second gate insulating film interposed therebetween;
the first conductivity type third semiconductor region and the first conductivity type fourth semiconductor region disposed in the second well region on both sides of the second gate electrode;
including
the first semiconductor region is connected to the first pad electrode;
the second semiconductor region is connected to the first reference potential wiring,
the third semiconductor region is connected to the second pad electrode;
the fourth semiconductor region is connected to the first power supply potential wiring,
In a second direction intersecting the first direction, the first power supply potential wiring is arranged closer to the first pad electrode than the second power supply potential wiring,
In the second input/output cell, the second guard ring is connected to the first power supply potential wiring at a first power supply section,
The semiconductor device, wherein in the first input/output cell, the first guard ring is connected to the second power supply potential wiring at the second power supply section, but is not connected to the first power supply potential wiring.
[Appendix 2]
In the semiconductor device according to Supplementary Note 1,
A semiconductor device, wherein a silicide layer is formed on the surface of the first guard ring.
[Appendix 3]
In the semiconductor device according to Supplementary Note 2,
In the first direction, the first resistance value of the second well region from the first guard ring to the second guard ring increases from the crossing region of the first guard ring and the first power supply potential wiring to the A semiconductor device, wherein the second resistance value of the silicide layer reaching the second power supply portion is greater than the second resistance value.

BiP1, BiP2, BiP3, BiP4 Parasitic transistor CL Cell CL1, CL2 Input/output cell CLP Power supply cell DNW Deep well region (n-type well region, n-type semiconductor region)
ESD1, ESD2 protection element ESL1, ESL2 logic circuit (input/output logic circuit)
GE gate electrode GI gate insulating film GND1, GND2 reference potential wiring (reference potential wiring for input/output)
GNDL Reference potential wiring (internal reference potential wiring)
I1, I2 current paths IL1 to IL6 insulating films (interlayer insulating films)
ITC internal circuit (internal logic circuit)
LS Level shift circuit M1, M2, M3 Metal wiring ND N-type drain region (n-type semiconductor region)
NH n-type guard ring (n-type semiconductor region)
NMOS n-channel transistor NS n-type source region (n-type semiconductor region)
NW n-type well region (n-type semiconductor region)
PC Power clamp circuit PD Pad electrode (terminal)
PD1, PD2 input/output pad electrode PDG reference potential pad electrode PDN p-type drain region (p-type semiconductor region)
PDV Power supply potential pad electrode PFD1, PFD2, PFD3, PFD4, PFD5 Feeding part PG1, PG2, PG3 Plug electrode (metal conductor layer)
PH p-type guard ring (p-type semiconductor region)
PMOS p-channel transistor PS p-type source region (p-type semiconductor region)
PW p-type well region (p-type semiconductor region)
R1 Parasitic resistance R2, R3, R4 Wiring resistance (parasitic resistance)
RIT Internal circuit area RA Protection element area RB Logic circuit area (input/output logic circuit area)
SIL silicide layer STI element isolation film SUB semiconductor substrate SUBa main surface UTN n-type unit transistor UTP p-type unit transistor VDD1, VDD2 power supply potential wiring (power supply potential wiring for input/output)
VDDL power supply potential wiring (internal power supply potential wiring)

Claims (8)

a first conductivity type semiconductor substrate having a main surface;
a first pad electrode formed on the main surface;
a first input/output cell formed on the main surface and connected to the first pad electrode;
a first power supply potential wiring arranged to cross the first input/output cell;
a second power supply potential wiring arranged to cross the first input/output cell and supplying a power supply potential to the first input/output cell;
a first reference potential wiring arranged to cross the first input/output cell and supplying a reference potential to the first input/output cell;
an internal circuit region formed on the main surface and arranged opposite to the first pad electrode with respect to the first input/output cell;
with
The first input/output cell is
a first well region of the first conductivity type formed in the semiconductor substrate;
a second well region of a second conductivity type, which is a conductivity type different from the first conductivity type, formed in the semiconductor substrate and arranged to surround the first well region in plan view;
a third well region of the second conductivity type formed in the semiconductor substrate, in contact with the second well region, and arranged between the first well region and the semiconductor substrate in a cross-sectional view;
a first protection element formed in the first well region;
a first guard ring of the second conductivity type formed in the second well region and arranged to surround the first well region in plan view;
including
the first power supply potential wiring, the second power supply potential wiring and the first reference potential wiring are arranged on the first input/output cell and extend in the first direction of the main surface;
the first power supply potential wiring is arranged closer to the first pad electrode than the second power supply potential wiring,
The first protection element is composed of a plurality of first transistors arranged in a matrix in the first direction and in a second direction intersecting the first direction,
The first transistor is
a first gate electrode formed on the main surface of the semiconductor substrate with a first gate insulating film interposed therebetween;
the first semiconductor region of the second conductivity type and the second semiconductor region of the second conductivity type arranged in the first well region on both sides of the first gate electrode;
including
the first semiconductor region is connected to the first pad electrode;
the second semiconductor region is connected to the first reference potential wiring,
The semiconductor device, in the first input/output cell, wherein the first guard ring is connected to the second power supply potential wiring at the first power supply section, but is not connected to the first power supply potential wiring. The semiconductor device according to claim 1,
In plan view, the first guard ring has a ring shape,
The semiconductor device, wherein the first power supply potential wiring and the second power supply potential wiring are connected to each other outside the first guard ring. The semiconductor device according to claim 1,
A semiconductor device, wherein a silicide layer is formed on the surface of the first guard ring. The semiconductor device according to claim 1,
The first power supply unit
a first plug electrode disposed on the first guard ring and connected to the first guard ring;
a first metal wiring disposed on the first plug electrode and connected to the first plug electrode;
including
The semiconductor device, wherein the first guard ring is connected to the second power supply potential wiring via the first plug electrode and the first metal wiring. In the semiconductor device according to claim 4,
the first input/output cell includes a second plug electrode arranged on the first guard ring in a region where the first guard ring and the first power supply potential wiring intersect;
The semiconductor device, wherein the first metal wiring extends along the first guard ring and is connected to the second plug electrode. The semiconductor device according to claim 1,
said first input/output cell further comprising a second transistor formed in said second well region;
the second transistor,
a second gate electrode formed on the main surface of the semiconductor substrate with a second gate insulating film interposed therebetween;
the first conductivity type third semiconductor region and the first conductivity type fourth semiconductor region disposed in the second well region on both sides of the second gate electrode;
including
The semiconductor device, wherein the third semiconductor region is connected to the second power supply potential wiring. In the semiconductor device according to claim 6,
In the semiconductor device, the first reference potential wiring is arranged between the first power supply potential wiring and the second power supply potential wiring in the second direction. The semiconductor device according to claim 1,
moreover,
a second pad electrode formed on the main surface;
a second input/output cell adjacent to the first input/output cell in the first direction and connected to the second pad electrode;
with
The second input/output cell is
a fourth well region of the second conductivity type formed in the semiconductor substrate and spaced from the second well region in the first direction;
a second protection element formed in the fourth well region;
a second conductivity type second guard ring formed in the fourth well region and surrounding the second protection element in plan view;
a fifth well region of the first conductivity type formed in the semiconductor substrate and arranged between the second well region and the fourth well region in plan view;
including
The second protection element is composed of a plurality of third transistors,
the third transistor,
a third gate electrode formed on the main surface of the semiconductor substrate with a third gate insulating film interposed therebetween;
the first conductivity type fifth semiconductor region and the first conductivity type sixth semiconductor region disposed in the fourth well region on both sides of the third gate electrode;
including
the fifth semiconductor region is connected to the second pad electrode;
the second guard ring and the sixth semiconductor region are connected to the first power supply potential wiring;
The semiconductor device, wherein the fifth well region is connected to the first reference potential wiring.

Images