TWI815156B - Chip - Google Patents

Abstract

A chip is provided. The chip includes a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The plurality of first sub-transistors and the plurality of second sub-transistors are staggeredly disposed in a first row and a second row of the circuit block. The first transistor disposed in the first row and the second row receives a first input signal through different signal lines. The second transistor disposed in the first row and the second row receives a second input signal through different signal lines.

Description

wafer

The present invention relates to a wafer, and in particular to a semiconductor wafer.

In today's electronic devices, when a chip in the electronic device cracks, the crack often affects the transmission of signals or voltages in the chip, leading to complete loss of circuit blocks in the chip.

The present invention provides a chip that can effectively prevent chipping from causing complete disability of the circuit block.

The wafer of the present invention includes circuit blocks. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel with each other. The first sub-transistors and the second sub-transistors are arranged alternately in the first column and the second column of the circuit block. The first transistors arranged in the first column and the second column respectively receive the first input signal through different signal lines. The second transistors arranged in the first column and the second column respectively pass through Different signal lines receive the second input signal.

The chip of the present invention includes circuit blocks, power rails and power circuits. The power rails are divided into first power rails and second power rails that are connected in series. Power rails are coupled to the circuit blocks. The power supply circuit is divided into a first power supply circuit and a second power supply circuit. The power circuit is coupled to the power rail. The power circuit provides the first voltage to the circuit block through the power rail. Two ends of the first power rail are coupled to the first power circuit and the second power circuit respectively. Two ends of the second power rail are coupled to the first power circuit and the second power circuit respectively.

Based on the above, by staggering the first and second transistors in the first and second columns of the circuit block and receiving input signals through different signal lines, when a crack occurs on the chip , it can effectively prevent the circuit block from being completely disabled.

10, 20, 30a, 30b: circuit block

40, 41: Chip

100~108, 200~213, 300a~305a, 300b~305b, 306~311: signal line

400, 401, 401a, 401b, 410~413: Power rail

402, 403, 414~417: Power circuit

IN1, IN2: input signal

CRK: crack

M1-1~M1-4, M2-1~M2-4, N1-1~N1-4, N2-1~N2-4, N3-1~N3-4, N4-1~N4-4, P1- 1~P1-4, P2-1~P2-4, P3-1~P3-4, P4-1~P4-4: transistor

V1: first voltage

V2: second voltage

FIG. 1A is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 1B is a schematic diagram of CRK cracking in a circuit block according to Embodiment 1 of the present invention.

FIG. 2 is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 3A is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 3B is a schematic diagram of a circuit block according to an embodiment of the present invention.

FIG. 4A is a schematic diagram of a wafer according to an embodiment of the present invention.

FIG. 4B is a schematic diagram of a wafer according to an embodiment of the present invention.

Please refer to FIG. 1A , which is a schematic diagram of a circuit block 10 according to an embodiment of the present invention. The circuit block 10 includes transistors M1, M2, and signal lines 100~106. To put it simply, the transistors M1 and M2 are respectively arranged in the first column and the second column of the circuit block 10 . The transistors M1 and M2 arranged in the first column can obtain the input signal and the first voltage through the signal lines 100, 101, and 106. The transistors M1 and M2 arranged in the second column can obtain the input signal and the first voltage through the signal lines 102, 103, and 106. In other words, the transistors M1 and M2 in the circuit block 10 are arranged in the first column and the second column and obtain the input signal and the first voltage through different signal lines respectively. In this way, the circuit block 10 is It can effectively prevent the entire transistors M1 and M2 from being disabled or abnormal when the signal lines 101 to 106 are cracked.

First of all, it should be noted that the signal lines and signal lines 100 to 106 shown at the bottom of the net in FIG. 1A are arranged on different layers or at different heights. The signal lines and transistors M1 and M2 arranged on different layers or at different heights can pass through Via to connect. Therefore, when connected through the signal lines shown at the bottom of the net, the transistors M1 and M2 can be connected across the signal lines 100 to 106 to receive appropriate signals, which should be common knowledge in the art.

Specifically, the transistor M1 has sub-transistors M1-1~M1-4, and the sub-transistors M1-1~M1-4 are connected to each other in parallel, so the sub-transistors M1-1~M1-4 can be equal to Effectively it is operated by a single transistor M1. Similarly, the sub-transistors M2-1~M2-4 are connected to each other in parallel and can be equivalent to a single transistor M2 to operate. For example, the transistors M1 and M2 can be N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) or P-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). Semiconductor Field-Effect Transistor, PMOSFET) or other suitable transistor.

The sub-transistors M1-1~M1-4 and M2-1~M2-4 may have substantially the same length and width. The sub-transistors M1-1~M1-4 are sequentially arranged at the first row of the first column, the second row of the second column, the third row of the first column and the fourth row of the second column. The sub-transistors M2- 1~M2-4 are sequentially set at the first row of the second column, the second row of the first column, the third row of the second column and the fourth row of the first column. Therefore, in each column and each row of the circuit block 10, the sub-transistors M1-1~M1-4 of the transistor M1 and the sub-transistors M2-1~M2-4 of the transistor M2 are arranged staggered with each other. The sub-transistors M1-1~M1-4 of the transistor M1 and the sub-transistors M2-1~M2-4 of the transistor M2 are arranged staggeredly in the first column and the second column in a checkerboard pattern.

The signal lines 100 and 101 are arranged on the upper side of the circuit block 10, and the signal lines 102 and 103 are arranged on the lower side of the circuit block. The signal lines 100 and 101 are adjacent to the first column of the circuit block 10 , and the signal lines 100 and 101 are away from the second column of the circuit block 10 . The signal lines 102 and 103 are adjacent to the second column of the circuit block 10 , and the signal lines 102 and 103 are away from the first column of the circuit block 10 . The signal lines 100 and 101 can be used to provide input signals IN1 and IN2 to the sub-transistors of the first column respectively. The signal lines 102 and 103 can be used to provide input signals IN1 and IN2 to the sub-transistors of the second column respectively.

The signal line 104 is arranged on the right side of the circuit block 10, and the Both ends are coupled to signal lines 100 and 102 respectively. The signal line 105 is disposed on the left side of the circuit block 10, and two ends of the signal line 105 are coupled to the signal lines 101 and 103 respectively. That is to say, the signal lines 104 and 105 are respectively arranged on both sides of the circuit block 10 . The signal lines 100, 102, and 104 may jointly form a U-shaped structure surrounding the transistors M1 and M2. The signal lines 101, 103, and 105 may jointly form another U-shaped structure surrounding M1 and M2. The openings of the two U-shaped structures are arranged corresponding to each other.

The signal line 106 completely surrounds the transistors M1 and M2. The signal line 106 is disposed on the upper side of the circuit block 10 between the signal lines 100 and 101 and the first column of the circuit block 10 . The signal line 106 is disposed on the lower side of the circuit block 10 between the signal lines 103 and 104 and the second column of the circuit block 10 . The signal line 106 is on the right side of the circuit block 10 and can be disposed between the signal line 105 and the fourth row of the circuit block 10 . The signal line 106 is on the left side of the circuit block 10 and can be disposed between the signal line 105 and the first row of the circuit block 10 .

The signal lines 100, 102, and 104 can provide the input signal IN1 to the transistors M1 and M2, the signal lines 101, 103, and 105 can provide the input signal IN2 to the transistors M1 and M2, and the signal line 106 can provide the first voltage V1 to the transistors M1 and M2. .

In this embodiment, the first terminal of the transistor M1 receives the input signal IN1, the second terminal of the transistor M1 receives the first voltage V1, and the third terminal of the transistor M1 receives the input signal IN2. In order to achieve the above coupling relationship, the first ends of the sub-transistors M1-1 and M1-3 in the first column of the transistor M1 are coupled to the signal line 100, and the first ends of the sub-transistors M1-1 and M1-3 are The second end is coupled to the signal line 106 . The first ends of the sub-transistors M1-2 and M1-4 of the transistor M1 in the second column are coupled to the signal line 102, and the sub-transistors The second ends of M1-2 and M1-4 are coupled to the signal line 106. All the sub-transistors M1-1~M1-4 of the transistor M1 couple the third terminals of each sub-transistor M1-1~M1-4 to each other through the signal line 107, and receive the input signal IN2, wherein the signal line 107 is provided at between the first column and the second column of the circuit block 10 . The signal lines 107 are arranged in an oblique staggered manner, and are further connected to the third ends of the sub-transistors M1-1~M1-4 arranged staggered in the first column and the second column.

Similarly, the first terminal of the transistor M2 receives the input signal IN2, the second terminal of the transistor M2 receives the first voltage V1, and the third terminal of the transistor M1 receives the input signal IN1. In order to achieve the above coupling relationship, the first ends of the sub-transistors M2-2 and M2-4 in the first column of the transistor M2 are coupled to the signal line 101, and the first ends of the sub-transistors M2-2 and M2-4 are The second end is coupled to the signal line 101. The first ends of the sub-transistors M2-1 and M2-3 of the transistor M2 in the second column are coupled to the signal line 102, and the second ends of the sub-transistors M2-1 and M2-3 are coupled to the signal line. 106. All the sub-transistors M2-1~M2-4 of the transistor M1 couple the third terminals of each sub-transistor M2-1~M2-4 to each other through the signal line 108 and receive the input signal IN1, wherein the signal line 108 is provided at between the first column and the second column of the circuit block 10 . The signal lines 108 are arranged in an oblique and reciprocating manner, and are further connected to the third terminals of the sub-transistors M2-1 to M2-4 arranged in a staggered manner in the first column and the second column.

Therefore, the sub-transistors M1-1~M1-4 of the transistor M1 and the sub-transistors M2-1~M2-4 of the transistor M2 in the circuit block 10 are connected in each row and column of the circuit block 10. Staggered settings. The transistors M1-1, M2-1, M1-3 and M2-4 arranged in the first row can receive the input signals IN1, IN2 and The first voltage V1, the transistors M2-1, M1-1, M2-3, and M1-4 arranged in the second column can receive the input signals IN1, IN2 and the first voltage V1 through the signal lines 102, 103, and 106. Therefore, the circuit block 10 can effectively prevent the transistor M1 or the transistor M2 from being completely disabled when a crack occurs in any one of the signal lines 100 to 103.

Furthermore, by staggering the sub-transistors M1-1~M1-4 and M2-1~M2-4 in the first and second columns of the circuit block 10, the non-ideal gradient differences in the process can also be eliminated. Evenly distributed to transistors M1 and M2. In other words, by staggering the transistors M1 and M2 in each row and column, the impact of process non-idealities on the transistors M1 and M2 can be effectively reduced. When the transistors M1 and M2 have a differential circuit structure, a better matching effect can be achieved through the design of the circuit block 10 .

FIG. 1B is a schematic diagram of CRK cracking in the circuit block 10 according to Embodiment 1 of the present invention. In this embodiment, the circuit block 10 can be disposed on a flexible substrate. Due to the bending characteristics of the flexible substrate, crack CRK is more likely to occur in the circuit block 10 on the flexible substrate. Specifically, the crack CRK occurs on the signal lines 100, 101, and 106 of the circuit block 10, that is, the crack CRK occurs on the upper side of the circuit block 10. Therefore, the first terminal of the sub-transistor M1-1 cannot receive the input signal IN1, and the first terminals of the sub-transistors M2-2 and M2-4 cannot receive the input signal IN2. In other words, when crack CRK occurs, the sub-transistors M1-1, M2-2, and M2-4 in the first column cannot operate normally.

However, the first end of the transistor M1-3 in the first column can receive the input signal IN1 through the signal line 100, and the second end of the transistor M1-3 can receive the first voltage V1 through the ring-shaped signal line 106. In addition, the sub-transistors M2-1, M1-2, M2-3, M1-4 can receive input signals IN1 and IN2 from signal lines 102 and 103 respectively. In addition, the third terminals of the sub-transistors M1-1~M1-4 can receive the input signal IN2 through the signal line 107, and the third terminals of the sub-transistors M2-1~M2-4 can receive the input signal IN1 through the signal line 108. Therefore, the transistor M1-3 in the first column and the sub-transistors M2-1, M1-2, M2-3, and M1-4 in the second column can operate normally.

In short, the circuit blocks 10 are arranged alternately in the first column and the second column through the sub-transistors M1-1~M1-4 and M2-1~M2-4. In addition, the circuit block 10 also provides the input signal IN1 on both sides of the circuit block 10 through the signal lines 100 and 102, and provides the input signal IN2 on both sides of the circuit block 10 through the signal lines 101 and 103. In this way, when crack CRK occurs in the circuit block 10, it can be effectively avoided that the crack CRK occurs on the only signal line connected to the transistor M1 or M2, thereby causing one of the transistors M1 and M2 to become completely disabled. That is to say, when crack CRK occurs in the circuit block 10, the transistors M1 and M2 can still receive the input signals IN1, IN2 and the first voltage V1 to operate without completely disabling the circuit block 10.

In another embodiment, those of ordinary skill in the art can of course modify the circuit block 10 according to different design requirements. For example, the transistors M1 and M2 of the circuit block 10 may be divided into more than four. That is to say, the number of rows of the circuit block 10 can be increased or decreased, as long as the number of rows of the circuit block 10 is at least two rows. For example, the signal lines 100, 102, and 104 of the circuit block 10 do not need to have a U-shaped structure. That is to say, the signal lines 100, 102, and 104 are also replaced by signal line structures that completely surround or partially surround the transistors M1 and M2, as long as the circuit block 10 can receive the input signal IN1 on both the upper and lower sides. That’s it. The same modifications of course also apply to signal line 101, 103 and 105, the signal lines 101, 103 and 105 can be replaced by signal lines that completely surround the transistors M1 and M2. In this way, by providing the input signals IN1 and IN2 through the completely surrounding signal lines, the circuit block 10 can completely prevent any of the sub-transistors M1-1~M1-4 and M2-1~M2-4 from failing due to cracking. .

FIG. 2 is a schematic diagram of the circuit block 20 according to the first embodiment of the present invention. The circuit block 20 includes transistors P1, P2, N1, and N2. In this embodiment, the transistors P1 and P2 may be P-type metal oxide semi-field effect transistors, and the transistors N1 and N2 may be N-type metal oxide semi-field effect transistors. Transistor P1 has sub-transistors P1-1 to P1-4, and transistor P2 has sub-transistors P2-1 to P2-4. The transistor N1 has sub-transistors N1-1 to N1-4, and the transistor N2 has sub-transistors N2-1 to N2-4.

The sub-transistors P1-1~P1-4 and P2-1~P2-4 may have substantially the same length and width, and the sub-transistors N1-1~N1-4 and N2-1~N2-4 may have substantially the same length and width. Same length and width. The sub-transistors P1-1~P1-4 are sequentially arranged at the first row of the first column, the second row of the second column, the third row of the first column and the fourth row of the second column. The sub-transistors P2- 1~P2-4 are sequentially set at the first row of the second column, the second row of the first column, the third row of the second column and the fourth row of the first column. Therefore, in each column and each row of the circuit block 10, the sub-transistors P1-1 to P1-4 of the transistor P1 and the sub-transistors P2-1 to P2-4 of the transistor P2 are arranged staggered with each other. The sub-transistors P1-1 to P1-4 of the transistor P1 and the sub-transistors P2-1 to P2-4 of the transistor P2 are arranged staggeredly in the first column and the second column in a checkerboard pattern.

The sub-transistors N1-1~N1-4 are sequentially arranged at the first row of the third column, the second row of the fourth column, the third row of the third column and the fourth row of the fourth column. The sub-transistors N2- 1 ~N2-4 is sequentially placed at the first row of the fourth column, the second row of the third column, the third row of the fourth column, and the fourth row of the third column. Therefore, in each column and each row of the circuit block 10, the sub-transistors N1-1~N1-4 of the transistor N1 and the sub-transistors N2-1~N2-4 of the transistor N2 are arranged staggered with each other. The sub-transistors N1-1~N1-4 of the transistor N1 and the sub-transistors N2-1~N2-4 of the transistor N2 are arranged staggeredly in the third and fourth columns in a chessboard pattern.

The signal line 200 is disposed on the upper side of the circuit block 20 , the signal line 202 is disposed between the second column and the third column of the circuit block 20 , and the signal line 204 is disposed on the lower side of the circuit block 20 . The signal line 201 is disposed on the upper side of the circuit block 20 , the signal line 203 is disposed between the second column and the third column of the circuit block 20 , and the signal line 205 is disposed on the lower side of the circuit block 20 . The signal line 206 is connected to the signal lines 200, 202, and 204, and the signal line 207 is connected to the signal lines 201, 203, and 205. The signal line 208 completely surrounds the transistors P1 and P2, and the signal line 209 completely surrounds the transistors N1 and N2. The signal lines 200, 202, and 204 can be used to provide the input signal IN1, the signal lines 201, 203, and 205 can be used to provide the input signal IN2, the signal line 208 can be used to provide the first voltage V1, and the signal line 209 can be used to provide the first voltage V1.

In addition, the signal lines 210 are arranged between the first column and the second column of the circuit block 20. The signal lines 210 are arranged in diagonal staggers to connect the sub-transistors arranged staggered in the first and second columns. The third end of P1-1~P1-4. Similarly, the signal line 211 is disposed between the first column and the second column of the circuit block 20 to connect the third terminals of the sub-transistors P2-1 to P2-4. The signal line 212 is provided between the third column and the fourth column of the circuit block 20 to connect the third terminals of the sub-transistors N1-1 to N1-4. News The number line 213 is provided between the third column and the fourth column of the circuit block 20 to connect the third terminals of the sub-transistors N2-1 to N2-4.

Therefore, the sub-transistors P1-1, P2-2, P1-3, and P2-4 in the first column of the circuit block 20 can obtain the input signals IN1, IN2 and the first voltage V1 through the signal lines 200, 201, and 208. The sub-transistors P2-1, P1-2, P2-3, and P1-4 in the second column of the circuit block 20 can obtain the input signals IN1, IN2 and the first voltage V1 through the signal lines 202, 203, and 208. The sub-transistors N1-1, N2-2, N1-3, and N2-4 in the third column of the circuit block 20 can obtain the input signals IN1, IN2 and the second voltage V2 through the signal lines 202, 203, and 209. The sub-transistors N2-1, N1-2, N2-3, and N1-4 in the fourth column of the circuit block 20 can obtain the input signals IN1, IN2 and the second voltage V2 through the signal lines 204, 205, and 209.

In this way, when the crack CRK occurs in the circuit block 20, the transistors P1, P2, N1, and N2 can still receive the input signals IN1, IN2, the first voltage V1, and the second voltage V2 to operate without damaging the circuit block. Block 20 is completely disabled.

FIG. 3A is a schematic diagram of a circuit block 30a according to an embodiment of the present invention. Circuit block 30a has transistors N3, N4, P3, and P4. The transistors P3 and P4 may be P-type metal oxide semi-field effect transistors, and the transistors N3 and N4 may be N-type metal oxide semi-field effect transistors. Transistor P3 has sub-transistors P3-1 to P3-4, and transistor P4 has sub-transistors P4-1 to P4-4. Transistor N3 has sub-transistors N3-1 to N3-4, and transistor N4 has sub-transistors N4-1 to N4-4.

The sub-transistors P3-1~P3-4 and P4-1~P4-4 may have substantially the same length and width, and the sub-transistors N3-1~N3-4 and N4-1~N4-4 may have substantially the same length and width. Same length and width. Sub-transistors N3-1~N3-4 are sequentially arranged in the first column, first row, second The sub-transistors N4-1~N4-4 are sequentially arranged in the second row of the second column, the third row of the first column and the fourth row of the second column. The positions of the second column, third row and the first column, fourth row. Therefore, in each column and each row of the circuit block 30a, the sub-transistors N3-1~N3-4 of the transistor N3 and the sub-transistors N4-1~N4-4 of the transistor N4 are arranged staggered with each other. The sub-transistors N3-1~N3-4 of the transistor N3 and the sub-transistors N4-1~N4-4 of the transistor N4 are arranged staggeredly in the first column and the second column in a checkerboard pattern.

The sub-transistors P3-1~P3-4 are sequentially arranged at the fifth row of the first column, the sixth row of the second column, the seventh row of the first column and the eighth row of the second column. Sub-transistor P4-1 ~P4-4 is sequentially placed in the fifth row of the second column, the sixth row of the first column, the seventh row of the second column, and the eighth row of the first column. Therefore, in each column and each row of the circuit block 30a, the sub-transistors P3-1 to P3-4 of the transistor P3 and the sub-transistors P4-1 to P4-4 of the transistor P4 are arranged staggered with each other. The sub-transistors P3-1 to P3-4 of the transistor P3 and the sub-transistors P4-1 to P4-4 of the transistor P4 are arranged staggeredly in the first column and the second column in a checkerboard pattern.

The signal line 300a is disposed on the upper side of the circuit block 30a, and the signal line 302a is disposed on the lower side of the circuit block 30a. The signal line 301a is provided on the upper side of the circuit block 30a, and the signal line 303a is provided on the lower side of the circuit block 30a. The signal line 304a is connected to the signal lines 300a and 302a, and the signal line 305a is connected to the signal lines 301a and 303a. The signal line 306 completely surrounds the transistors P3 and P4, and the signal line 307 completely surrounds the transistors N3 and N4. The signal lines 300a and 302a can be used to provide the input signal IN1, the signal lines 301a and 303a can be used to provide the input signal IN2, and the signal line 306 can be used to provide the first voltage. V1, the signal line 307 can be used to provide the first voltage V1.

In addition, the signal lines 308, 309, 310, and 311 are arranged between the first column and the second column of the circuit block 30a. The signal lines 308 can be connected to the sub-transistors P3 that are staggered in the first column and the second column. -1 to the third end of P3-4, the signal line 309 can be connected to the third end of the sub-transistors P4-1 to P4-4 arranged staggered in the first column and the second column, and the signal line 310 can be connected to The third end of the sub-transistors N3-1~N3-4 arranged in the first column and the second column in a staggered manner, the signal line 311 can be connected to the sub-transistors N4- in the first column and the second column arranged in a staggered manner. 1~The third end of N4-4.

Therefore, the sub-transistors N3-1, N4-2, N3-3, N4-4, P3-1, P4-2, P3-3, and P4-4 in the first column of the circuit block 30a can pass through the signal line 300a, 301a, 306, and 307 obtain input signals IN1, IN2, first voltage V1, and second voltage V2. The sub-transistors N4-1, N3-2, N4-3, N3-4, P4-1, P3-2, P4-3, and P3-4 in the second column of the circuit block 30a can pass through the signal lines 302a, 303a, 306 and 307 obtain the first voltage V1 and the second voltage V2 of the input signals IN1 and IN2.

In this way, when the crack CRK occurs in the circuit block 30a, the transistors P3, P4, N3, and N4 can still receive the input signals IN1, IN2, the first voltage V1, and the second voltage V2 to operate without damaging the circuit area. Block 30a is completely disabled.

FIG. 3B is a schematic diagram of the circuit block 30b according to the first embodiment of the present invention. The circuit block 30b shown in FIG. 3B is similar to the circuit block 30a shown in FIG. 3A , so the same symbols are used for the same components. The difference between the circuit block 30a and the circuit block 30b is that the signal lines 300a, 301a, 302a, 303a, 304a, and 305a in the circuit block 30a are respectively connected by the signal lines 300b, 301b, 302b, 303b, 304b. 305b superseded.

The signal line 300b is disposed on the upper side of the circuit block 30b, and the signal line 302b is disposed on the lower side of the circuit block 30b. The signal line 301b is disposed on the upper side of the circuit block 30b, and the signal line 303b is disposed on the lower side of the circuit block 30b. The signal line 304b is connected to the signal lines 300b and 302b, and the signal line 305b is connected to the signal lines 301b and 303b. The signal lines 300b and 302b can be used to provide the input signal IN1, and the signal lines 301b and 303b can be used to provide the input signal IN2.

Therefore, the sub-transistors N3-1, N4-2, N3-3, N4-4, P3-1, P4-2, P3-3, and P4-4 in the first column of the circuit block 30b can pass through the signal line 300b, 301b, 306, and 307 obtain input signals IN1, IN2, first voltage V1, and second voltage V2. The sub-transistors N4-1, N3-2, N4-3, N3-4, P4-1, P3-2, P4-3, and P3-4 in the second column of the circuit block 30b can pass through the signal lines 302b, 303b, 306 and 307 obtain the first voltage V1 and the second voltage V2 of the input signals IN1 and IN2.

In this way, when the crack CRK occurs in the circuit block 30b, the transistors P3, P4, N3, and N4 can still receive the input signals IN1, IN2, the first voltage V1, and the second voltage V2 to operate without damaging the circuit area. Block 30b is completely disabled.

FIG. 4A is a schematic diagram of a wafer 40 according to an embodiment of the present invention. A plurality of circuit blocks 10/20/30, power rails 400, 401 and power circuits 402, 403 are provided in the chip 40. The power circuits 402, 403 may provide the first voltage V1 to the power rails 400, 401. The circuit block 10/20/30 is coupled to the power rails 400, 401 to receive the first voltage V1. In one embodiment, the chip 40 may be disposed on a flexible substrate. Due to the bending characteristics of the flexible substrate, cracking is more likely to occur in the signal lines 400 and 401 on the flexible substrate.

In detail, two ends of the power rail 400 are coupled to power circuits 402 and 403 . Two ends of the power rail 401 are coupled to power circuits 402 and 403 . In this way, the power traces 400 and 401 can jointly form a ring structure surrounding the wafer 40 . In this way, when a crack occurs in the power rail 400 or the power rail 401, the chip 40 can still stably transmit the first voltage V1 to all circuit blocks 10/20 through the ring structure of the power rails 400 and 401. /30, therefore, no circuit blocks 10/20/30 in the chip 40 will be disabled due to cracking.

In addition, by providing power circuits 402 and 403 in the chip 40, the first voltage V1 provided on the power rails 400 and 401 can also be stabilized, thereby further improving the power supply of the power rails 400 and 401 when transmitting the first voltage V1. The attenuation problem of the first voltage V1 is caused by the impedance of the tracks 400 and 401.

In addition, as circled in Figure 4A, the power rails 400, 401 may have various implementations. In one embodiment, the power rail 401a may be a linearly connected structure. In another embodiment, the power trace 401b can have a square wavy structure. In this way, when the chip 40 is disposed on the flexible substrate, the power trace 401b can provide power to the chip 40 through the square wavy structure. The overall flexibility is better when bending and the chip 40 is prevented from cracking.

FIG. 4B is a schematic diagram of a wafer 41 according to an embodiment of the present invention. The chip 41 is provided with a plurality of circuit blocks 10/20/30, power rails 410~413 and power circuits 414~417. The power circuits 414-417 can provide the first voltage V1 to the power rails 410-413. The circuit blocks 10/20/30 are coupled to the power rails 410~413 to receive the first voltage V1. In one embodiment, the chip 41 can be disposed on a flexible substrate, because the flexible substrate Due to the bendable characteristics, cracking is more likely to occur in the signal lines 410~413 on the flexible substrate.

In detail, two ends of the power rail 410 are coupled to the power circuits 414 and 415 . The two ends of the power rail 411 are coupled to the power circuits 415 and 416, the two ends of the power rail 412 are coupled to the power circuits 416 and 417, and the two ends of the power rail 413 are coupled to the power circuits 417 and 414. In this way, the power rails 410 ~ 413 can jointly form a ring structure surrounding the chip 41 . In this way, when a crack occurs in one or more of the power rails 410~413, the chip 41 can still stabilize the first voltage V1 through the ring structure of the power rails 410~413 and the power circuits 414~417. The ground is transmitted to all circuit blocks 10/20/30, therefore, no circuit block 10/20/30 in the chip 41 will be disabled due to cracking.

In addition, by providing power circuits 414~417 in the chip 41, the first voltage V1 provided on the power rails 410~413 can also be stabilized, thereby further improving the power supply of the power rails 410~413 when transmitting the first voltage V1. The attenuation problem of the first voltage V1 is caused by the impedance of the tracks 410~413.

To sum up, the present invention alternately arranges different transistors in the first and second columns of the circuit block, and provides input signals to the transistors in the first and second columns through different signal lines. In this way, when a crack occurs on the chip, the complete loss of the circuit block can be effectively avoided.

10:Circuit block

100~108: signal line

IN1, IN2: input signal

M1-1~M1-4, M2-1~M2-4: transistor

V1: first voltage

Claims (7)

A chip includes: a circuit block; a power rail coupled to the circuit block, wherein the power rail is divided into a plurality of sub-power rails connected in series, and the sub-power rails collectively surround the a chip; and a power circuit divided into a plurality of sub-power circuits, wherein the sub-power circuits are respectively coupled between the sub-power rails to respectively provide a first voltage to the sub-power rails, wherein The circuit block includes: a first transistor divided into a plurality of first sub-transistors connected in parallel; and a second transistor divided into a plurality of second sub-transistors connected in parallel, wherein the The first sub-transistors and the second sub-transistors are arranged alternately in a first column and a second column of the circuit block. The chip of claim 1, wherein the sub-power rails include a first sub-power rail and a second sub-power rail, and the sub-power circuits include a first sub-power circuit, a second Sub-power circuit and a third sub-power circuit, wherein the circuit block has a first circuit block and a second circuit block respectively coupled to the first sub-power rail and the second sub-power rail , the first circuit block is coupled to the first sub-power circuit and the second sub-power circuit at both ends of the first sub-power rail To receive the first voltage, the second circuit block receives the first voltage from the third sub-power circuit and the second sub-power circuit coupled at both ends of the second sub-power rail. The chip of claim 2, wherein when the first sub-power rail has a crack, the first circuit block and the first sub-power circuit connected to one end of the first sub-power rail are disconnected. At this time, the first circuit block receives the first voltage from the second sub-power circuit connected to the other end of the first sub-power rail. The wafer according to claim 1, wherein the power track has a square wavy structure. The wafer according to claim 1, wherein the wafer is disposed on a flexible substrate. The chip of claim 1, wherein the first sub-transistors and the second sub-transistors are arranged alternately in each row of the circuit block. The chip of claim 1, wherein the first transistor and the second transistor have the same conductivity type.

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