TWI684263B - Semiconductor device and power gate switching system - Google Patents

Abstract

A semiconductor device and a power gate switching system are provided. The semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

Description

Semiconductor device, power gate switching system [Cross-reference to related applications]

This application claims the priority of Korean Patent Application No. 10-2015-0120327 filed with the Korean Intellectual Property Office on August 26, 2015. The disclosure content of the Korean patent application is incorporated in this case for reference.

The concept of the present invention relates to a power gate switching system for supplying a virtual power voltage to a standard cell.

In general, to operate a standard cell of a semiconductor device, a power supply voltage is supplied to the standard cell from the outside of the semiconductor device via a power gate switch. The voltage output from the power gate switch may be referred to as a virtual power supply voltage. In order to achieve stable operation of the semiconductor device, the virtual power supply voltage should be equally applied to each of the standard cells. However, the semiconductor device may have a large voltage drop at a region relatively far from the power gate switch. For example, a standard cell far from the power gate switch may not receive a power supply voltage at the same level as a standard cell close to the power gate switch. In this case, the remote standard cell may fail.

According to an exemplary embodiment of the present inventive concept, there is provided a semiconductor device including: a virtual power line extending in a first direction; an n-well extending in the first direction, wherein the virtual power line and the n The wells are arranged in a column; the first power gate switch cell is arranged in the n-well; the second power gate switch cell is arranged in the n-well, wherein the first power gate switch cell and the first The second power gate switch cell is a first type cell; and a third power gate switch cell is disposed in the n well between the first power gate switch cell and the second power gate switch cell , Wherein the third power gate switch cell is a second type cell different from the first type cell.

According to an exemplary embodiment of the present inventive concept, a power gate switching system is provided, including: a first virtual power line extending in a first direction; a first power gate cell connected to the first virtual power line; Two power gate cells are connected to the first virtual power line, wherein the first power gate cells and the second power gate cells respectively include at least one tap; and the third power gate cells are connected to The first virtual power line is disposed between the first power gate cell and the second power gate cell, wherein the third power gate cell does not include a tap, and wherein the first power source The gate cells to the third power gate cells and the first virtual power line are arranged in the first row.

According to an exemplary embodiment of the present inventive concept, a power gate switching system is provided, including: a first column including a first virtual power line, a first power gate cell, and a second power gate cell, wherein the first power source The gate cell includes a first gate electrode disposed between the first diffusion area and the second diffusion area, and at least one tap, wherein the The second power gate cell includes a second gate electrode disposed between the third diffusion area and the fourth diffusion area and does not include a tap; and the second row includes the second virtual power line, the third power gate cell and the first Four power gate cells, wherein the third power gate cell includes a third gate electrode disposed between the fifth diffusion area and the sixth diffusion area, and at least one tap, and the fourth power gate cell includes The fourth gate electrode disposed between the seventh diffusion area and the eighth diffusion area does not include a tap, and wherein the fourth power gate cell is connected to the second power gate cell.

100, 200, 300, 400, 500, 1100, 1200

101, 201, 301, 401, 501‧‧‧ First diffusion zone

102, 202, 302, 402, 502

103, 203, 303, 403, 503

104, 204, 304, 404, 504

105, 205, 305, 405, 505

106, 206, 306, 406, 506

407, 507‧‧‧ seventh diffusion zone

408, 508‧‧‧Eighth diffusion zone

409, 509‧‧‧Ninth diffusion zone

410, 510‧‧‧ Tenth diffusion zone

411, 511‧‧‧Eleventh diffusion area

412、512‧‧‧The twelfth diffusion area

601, 701, 801 ‧‧‧ first cell

602, 702, 802 ‧‧‧ second cell

603, 703, 803 ‧‧‧ third cell

604, 704, 804 ‧‧‧ fourth cell

605, 705, 805 ‧‧‧ fifth cell

611, 711, 811‧‧‧ additional cell

612, 712, 812 ‧‧‧ additional cell

613, 713, 813‧‧‧ third additional cell

821‧‧‧ sixth cell

822‧‧‧The seventh cell

823‧‧‧The eighth cell

824‧‧‧ninth cell

825‧‧‧The tenth cell

1101, 1102, 1103, 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212 Diffusion zone

1300‧‧‧Semiconductor device

D1‧‧‧First direction

D2‧‧‧Second direction

D3‧‧‧third direction

DB‧‧‧Diffusion

G1‧‧‧First gate electrode

G2‧‧‧Second gate electrode

G3‧‧‧The third gate electrode

G4‧‧‧ fourth gate electrode

G5‧‧‧fifth gate electrode

G6‧‧‧Sixth gate electrode

Gate_CTRL‧‧‧ Gate voltage, voltage

N-tab‧‧‧n tap

N-tab1‧‧‧First n tap

N-tab2‧‧‧Second n tap

N-tab3‧‧‧Third n tap

N-tab4‧‧‧ fourth n tap

NT‧‧‧NMOS tap

NVSS‧‧‧Power cord

N-well‧‧‧N well

PMOS‧‧‧P channel metal oxide semiconductor

P-sub‧‧‧p-type substrate

P-tab1‧‧‧The first p-tap

P-tab2‧‧‧Second p tap

P-tab3‧‧‧third tap

P-tab4‧‧‧ fourth tap

PT‧‧‧PMOS tap

P-well‧‧‧P well

Region I‧‧‧Standard cell area

Region II

Row1‧‧‧First column

Row2‧‧‧Second row

Row3‧‧‧third column

Row4‧‧‧The fourth column

Row5‧‧‧Column 5

s1, s2, s3, W_pg2pg ‧‧‧ distance

Std1, Std2, Std3, Std4, Std5, Std6, STD Cells, Std.cells ‧‧‧ standard cells

STI‧‧‧device isolation layer

Vbias, Vbias2 ‧‧‧ bias voltage

V _DD ‧‧‧ Power supply voltage/power cord

V _SS ‧‧‧Ground voltage/ground wire

Virtual_V _DD ‧‧‧Virtual power supply voltage/Virtual power supply line

Virtual_V _SS ‧‧‧Virtual ground voltage/Virtual ground wire

The above and other features of the inventive concept will be more clearly understood by explaining exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 2 is a cross-sectional view taken along line AA′ shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

FIG. 3 is a cross-sectional view taken along line AA′ shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

4 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 5 is a cross-sectional view taken along line AA′ shown in FIG. 4 according to an exemplary embodiment of the inventive concept.

6 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

7 is a cross-sectional view taken along line BB′ shown in FIG. 6 according to an exemplary embodiment of the inventive concept.

FIG. 8 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

9 is a cross-sectional view taken along line BB′ shown in FIG. 8 according to an exemplary embodiment of the present inventive concept.

FIG. 10 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 11 is a cross-sectional view taken along line BB′ shown in FIG. 10 according to an exemplary embodiment of the inventive concept.

FIG. 12 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 13 is a cross-sectional view taken along line BB′ shown in FIG. 12 according to an exemplary embodiment of the present inventive concept.

14 is a plan view illustrating the layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept.

15 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept.

16 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept.

17A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

17B is a cross-sectional view taken along line AA′ shown in FIG. 17A according to an exemplary embodiment of the present inventive concept.

FIG. 17C is a cross-sectional view taken along line BB′ shown in FIG. 17A according to an exemplary embodiment of the inventive concept.

FIG. 18A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

18B is a cross-sectional view taken along line AA′ shown in FIG. 18A according to an exemplary embodiment of the present inventive concept.

18C is a cross-sectional view taken along line BB′ shown in FIG. 18A according to an exemplary embodiment of the inventive concept.

19 is a plan view illustrating the layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 1 is a plan view illustrating a power gate switching system 100 according to an exemplary embodiment of the inventive concept. FIG. 2 is a cross-sectional view taken along line AA′ shown in FIG. 1 according to an exemplary embodiment of the inventive concept.

1 and 2, the power gate switching system 100 may include: a p-type substrate P-sub; an N-well N-well formed in the p-type substrate P-sub; and a first to sixth diffusion regions 101 to 102 , 103, 104, 105, and 106 are formed in the N-well N-well; the first gate electrode G1 is formed on the N-well N-well and formed between the first diffusion region 101 and the second diffusion region 102; The second gate electrode G2 is formed on the N-well N-well and formed between the third diffusion region 103 and the fourth diffusion region 104; the third gate electrode G3, formed on the N-well N-well and formed between the fifth diffusion region 105 and the sixth diffusion region 106; the first p-tap P-tab1, formed in the N-well N-well adjacent to the first diffusion region 101; The second p-tap P-tab2 is formed in the N-well N-well adjacent to the second diffusion region 102; the third p-tap P-tab3 is formed in the N-well N-well adjacent to the third diffusion region 103; and the fourth p The tap P-tab4 is formed in the N-well N-well adjacent to the fourth diffusion region 104.

The N-well N-well may extend in the first direction D1. For example, the N-well N-well may be a region doped with n-type impurities.

The first to sixth diffusion regions 101 to 106 may be formed in the N-well N-well in the first direction D1. The first diffusion region 101 and the second diffusion region 102 may be spaced apart from each other, and the first gate electrode G1 may be disposed on the region between the first diffusion region 101 and the second diffusion region 102. The third diffusion region 103 and the fourth diffusion region 104 may be spaced apart from each other, and the second gate electrode G2 may be disposed on the region between the third diffusion region 103 and the fourth diffusion region 104. The fifth diffusion region 105 and the sixth diffusion region 106 may be formed between the second diffusion region 102 and the third diffusion region 103. The fifth diffusion region 105 and the sixth diffusion region 106 may be spaced apart from each other, and the third gate electrode G3 may be disposed on the region between the fifth diffusion region 105 and the sixth diffusion region 106. Each of the first to sixth diffusion regions 101 to 106 may be doped with p-type impurities.

For example, the size of each of the fifth and sixth diffusion regions 105 and 106 may be smaller than the size of each of the first to fourth diffusion regions 101 to 104. In addition, the size of the third gate electrode G3 (for example, the width in the first direction D1) may be smaller than the size of the first gate electrode G1 or the second gate electrode G2 (for example, in Width in the first direction D1).

The power supply voltage V _DD may be supplied to the first diffusion region 101. In the case where the gate voltage Gate_CTRL is applied to the first gate electrode G1 to form a first channel between the first diffusion region 101 and the second diffusion region 102, the power supply voltage V _DD applied to the first diffusion region 101 may pass The first channel and the second diffusion region 102 are output in the form of virtual power supply voltage Virtual_V _DD . The virtual power supply voltage Virtual_V _DD can be supplied to a standard cell for implementing a logic circuit.

The power supply voltage V _DD may be supplied to the third diffusion region 103. In the case where the gate voltage Gate_CTRL is applied to the second gate electrode G2 to form the second channel between the third diffusion region 103 and the fourth diffusion region 104, the power supply voltage V _DD applied to the third diffusion region 103 may pass The second channel and the fourth diffusion region 104 are output in the form of virtual power supply voltage Virtual_V _DD . The virtual power supply voltage Virtual_V _DD may be supplied to the standard cell for implementing the logic circuit.

The power supply voltage V _DD may be supplied to the fifth diffusion region 105. In the case where the gate voltage Gate_CTRL is applied to the third gate electrode G3 to form a third channel between the fifth diffusion region 105 and the sixth diffusion region 106, the power supply voltage V _DD applied to the fifth diffusion region 105 may pass The third channel and the sixth diffusion region 106 are output as the virtual power supply voltage Virtual_V _DD . The virtual power supply voltage Virtual_V _DD may be supplied to the standard cell for implementing the logic circuit.

An insulating layer may be further formed between the first gate electrode G1 and the N-well N-well, between the second gate electrode G2 and the N-well N-well, and between the third gate electrode G3 and the N-well N-well.

The first p-tap P-tab1 and the second p-tap P-tab2 may be formed adjacent to the first diffusion area 101 and the second diffusion area 102, respectively. The third p-tap P-tab3 and the fourth p-tap P-tab4 may be formed adjacent to the third diffusion region 103 and the fourth diffusion region 104, respectively. For example, each of the first p-tap P-tab1 to the fourth p-tap P-tab4 may be a region doped with n-type impurities. The first p-tap P-tab1 to the fourth p-tap P-tab4 may have a doping concentration different from that of the N-well N-well. The first p-tap P-tab1 to the fourth p-tap P-tab4 may extend in the second direction D2. In addition, although the first p-tap P-tab1 is shown not to directly contact the first diffusion region 101, the first p-tap P-tab1 may directly contact the first diffusion region 101. The second p-tap P-tab2 to the fourth p-tap P-tab4 may be formed in a manner similar to the first p-tap P-tab1.

The bias voltage Vbias may be applied to the first p-tap P-tab1 to the fourth p-tap P-tab4. The bias voltage Vbias can prevent a latch-up phenomenon in the power gate switching system 100. Although the bias voltage Vbias is shown as being applied separately to the first p-tap P-tab1 to the fourth p-tap P-tab4, the power supply voltage V _DD may be applied to the first p-tap P-tab1 to the first instead of the bias voltage Vbias Four p-tap P-tab4.

The distance between the second p-tap P-tab2 and the third p-tap P-tab3 can be determined in consideration of the N-well N-well doping concentration. For example, the second p-tap P-tab2 and the third p-tap P-tab3 may be adapted to prevent the latch-up phenomenon occurring in the power gate switching system 100 at a distance apart from each other. For example, in a 10 nanometer logic process, the distance between these taps may be about 50 microns. If the distance between the second p-tap P-tab2 and the third p-tap P-tab3 is greater than the critical distance (for example, a distance that can prevent the latch-up phenomenon), the fifth diffusion region 105 or the sixth diffusion region can be approached 106 Set at least one additional p-tap. Even when the distance between the second p-tap P-tab2 and the third p-tap P-tab3 is within a range suitable for preventing the latch-up phenomenon, the distance between the second diffusion region 102 and the third diffusion region 103 One of the standard cells may not receive enough power supply voltage V _DD . Therefore, by providing the fifth diffusion region 105, the sixth diffusion region 106, and the third gate electrode G3, the stable power supply voltage V _DD can be supplied to the standard between the second diffusion region 102 and the third diffusion region 103 Cells without setting additional p-tap.

1 and 2 again, the distance between the first gate electrode G1 and the third gate electrode G3 (for example, s1) is shown as the distance between the first gate electrode G1 and the second gate electrode G2 (for example, half of s2). However, in an exemplary embodiment of the present inventive concept, the distance between the first gate electrode G1 and the third gate electrode G3 (eg, s1) may be the distance between the first gate electrode G1 and the second gate electrode G2 (For example, s2) in the range of 1/4 times to 3/4 times. In an exemplary embodiment of the inventive concept, in order to enable the third channel to be formed at the overlapping region between the third gate electrode G3 and the N-well N-well, the fifth diffusion region 105 and the sixth diffusion region 106 It may be placed at a position appropriately adjusted in consideration of the position of the third gate electrode G3.

As shown in FIGS. 1 and 2, four p-tap can be formed in the power gate switching system 100. However, the inventive concept may not be limited to this; for example, as shown in FIG. 3, the power gate switching system 100 may include two p-tap. The same reference numbers in FIG. 3 as those in FIGS. 1 and 2 may indicate the same or similar elements. As an example, as shown in FIG. 3, a p-pump may be provided adjacent to the first diffusion region 101 The head P-tab1 may be provided with a p-tap P-tab4 adjacent to the fourth diffusion region 104. As another example, the p-tap P-tab1 may be disposed adjacent to the first diffusion area 101 and the p-tap P-tab3 may be disposed adjacent to the third diffusion area 103. As yet another example, p-tap P-tab2 may be disposed adjacent to the second diffusion region 102 and p-tap P-tab4 may be disposed adjacent to the fourth diffusion region 104.

FIG. 4 is a plan view illustrating a power gate switching system 100 according to an exemplary embodiment of the inventive concept. FIG. 5 is a cross-sectional view taken along line AA′ shown in FIG. 4 according to an exemplary embodiment of the inventive concept. The same reference numbers in FIGS. 4 and 5 as those in FIGS. 1 and 2 may indicate the same or similar elements.

The power gate switching system 100 may include a device isolation layer STI, which may be formed using shallow trench isolation technology. A device isolation layer STI may be provided to isolate standard cells located between the second p-tap P-tap2 and the fifth diffusion region 105 or between the sixth diffusion region 106 and the third p-tap P-tab3. Each of the device isolation layers STI may be adjacent to the corresponding one of the p-tap and extend in the second direction D2. The device isolation layer STI is shown not to directly contact the p-tap, however, in an exemplary embodiment of the inventive concept, the device isolation layer STI may directly contact the p-tap.

In an exemplary embodiment of the inventive concept, the device isolation layer STI may be formed of a silicon oxide layer or may include a silicon oxide layer. For example, the device isolation layer STI may be composed of high-density plasma (HDP) oxide, TetraEthylOrthoSilicate (TEOS), plasma-enhanced tetraethylorthosilicate , PE-TEOS), Ozone-Tetraethylorthosilicate (O ₃ -TEOS), Undoped Silicate Glass (USG), PhosphoSilicate Glass (PSG), Among Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG) At least one or any combination thereof is formed.

FIG. 6 is a plan view illustrating a power gate switching system 200 according to an exemplary embodiment of the inventive concept. 7 is a cross-sectional view taken along line BB′ shown in FIG. 6 according to an exemplary embodiment of the inventive concept. The cross-sectional view taken along line AA' shown in FIG. 6 will be omitted from FIG. 7 because it is substantially the same as that shown in FIG. 2.

6 and 7, the power gate switching system 200 may include a p-type substrate P-sub, and an N-well N-well may be formed in the p-type substrate P-sub.

The power gate switching system 200 may include a first diffusion region 201, a second diffusion region 202, a third diffusion region 203, a fourth diffusion region 204, a fifth diffusion region 205, and a sixth diffusion formed in the N-well N-well Area 206. The power gate switching system 200 may include: a first gate electrode G1 formed on the N-well N-well and formed between the first diffusion region 201 and the second diffusion region 202; a second gate electrode G2 formed on the N-well N -on the well and formed between the third diffusion region 203 and the fourth diffusion region 204; and the third gate electrode G3, formed on the N-well N-well and formed between the fifth diffusion region 205 and the sixth diffusion region 206 between.

For example, the distance between the first gate electrode G1 and the third gate electrode G3 (eg, s1) may be half the distance between the first gate electrode G1 and the second gate electrode G2 (eg, s2). However, the distance between the first gate electrode G1 and the third gate electrode G3 (for example, s1) may be between the first gate electrode G1 and the second gate electrode G2 The distance (for example, s2) is in the range of 1/4 to 3/4 times. In an exemplary embodiment of the inventive concept, in order to enable the third channel to be formed at the overlapping region between the third gate electrode G3 and the N-well N-well, the fifth diffusion region 205 and the sixth diffusion region 206 It may be placed at a position appropriately adjusted in consideration of the position of the third gate electrode G3.

For example, the first to sixth diffusion regions 201 to 206 may be doped with p-type impurities. The power supply voltage V _DD (for example, as shown in FIG. 2) may be supplied to the first diffusion region 201, the third diffusion region 203 and the fifth diffusion region 205. Depending on the voltage Gate_CTRL to be applied to the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3, the power sources applied to the first diffusion region 201, the third diffusion region 203, and the fifth diffusion region 205 The voltage V _DD can be used as the virtual power supply voltage Virtual_V _DD and output through the second diffusion region 202, the fourth diffusion region 204 and the sixth diffusion region 206.

For example, the size of each of the fifth and sixth diffusion regions 205 and 206 may be smaller than the size of each of the first to fourth diffusion regions 201 to 204. In addition, the size of the third gate electrode G3 (for example, the width in the first direction D1) may be smaller than the size of the first gate electrode G1 or the second gate electrode G2 (for example, the width in the first direction D1).

The power gate switching system 200 may include a first p-tap P-tab1 to a fourth p-tap P-tab4 provided in the N-well N-well. The first to fourth p-tabs P-tab1 to P-tab4 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The first p-tap P-tab1 may be adjacent to the first diffusion region 201. The second p-tap P-tab2 may be adjacent to the second diffusion region 202. The third p-tap P-tab3 may be adjacent to the third diffusion region 203. The fourth p-tap P-tab4 may be adjacent to the fourth diffusion region 204. The p-tap is It is shown not to be in direct contact with the diffusion regions, however, in exemplary embodiments of the inventive concept, the p-tap may be in direct contact with the diffusion regions.

For example, the first p-tap P-tab1 to the fourth p-tap P-tab4 may be doped with n-type impurities and may have a doping concentration different from that of the N-well N-well. A bias voltage Vbias (for example, the one shown in FIG. 2) may be applied to the first p-tap P-tab1 to the fourth p-tap P-tab4 to prevent the latch-up phenomenon from occurring.

The power gate switching system 200 may further include first n-tap N-tab1 to fourth n-tap N-tab4, and the first n-tap N-tab1 to fourth n-tap N-tab4 are formed in the p-type substrate P-sub as It extends in the second direction D2 and is formed to be spaced apart from each other in the first direction D1. In the p-type substrate P-sub, the first n-tap N-tab1 may be parallel to the second direction D2 and coaxial with the first p-tap P-tab1. In the p-type substrate P-sub, the second n-tap N-tab2 may be parallel to the second direction D2 and coaxial with the second p-tap P-tab2. In the p-type substrate P-sub, the third n-tap N-tab3 may be parallel to the second direction D2 and coaxial with the third p-tap P-tab3. In the p-type substrate P-sub, the fourth n-tap N-tab4 may be parallel to the second direction D2 and coaxial with the fourth p-tap P-tab4.

For example, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be doped with p-type impurities, and the first n-tap N-tab1 to the fourth n-tap N-tab4 may have a p-type substrate P -sub doping concentration is different. The bias voltage Vbias2 may be applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 to prevent the latch-up phenomenon. In an exemplary embodiment of the inventive concept, the bias voltage Vbias2 applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 may be a ground voltage.

As shown in FIG. 6, the first n-tap N-tab1 to the fourth n-tap N-tab4 It may be spaced apart from the first p-tap P-tab1 to the fourth p-tap P-tab4. However, each of the first n-tap N-tab1 to the fourth n-tap N-tab4 may be connected to the first p-tap P-tab1 to the boundary between the p-type substrate P-sub and the N-well N-well. The corresponding one of the fourth p-tap P-tab4 contacts.

The distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 can take into account the N-well N-well doping The concentration, the doping concentration of the p-substrate P-sub, or a combination thereof is determined. For example, the distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 may be such as to prevent Within the range in which the latch-up phenomenon occurs in the switching system 200.

Similar to those described with reference to FIG. 3, the p-tap may be composed of only the first p-tap P-tab1 and the third p-tap P-tab3 or only the first p-tap P-tab1 and the fourth p-tap P-tab4 . Furthermore, the n-tap may be composed of only the first n-tap N-tab1 and the third n-tap N-tab3 or only the first n-tap N-tab1 and the fourth n-tap N-tab4. In addition, the power gate switching system 200 may further include multiple device isolation layers STI as shown in FIGS. 4 and 5.

Referring back to FIG. 6, a plurality of standard cell STD Cells can be disposed between the second p-tap P-tab2 and the third p-tap P-tab3 and between the second n-tap N-tab2 and the third n-tap N-tab3 . The virtual power supply voltage Virtual_V _DD and the ground voltage V _SS can be supplied to a plurality of standard cells STD Cells. In the case of virtual power voltage Virtual_V _DD via the output 202 and the fourth diffusion region of the second diffusion region 204, the virtual power voltage Virtual_V _DD can be sufficiently supplied to the plurality of standard cells in membered STD Cells adjacent to the second diffusion region 202 and the second Four standard cell STD Cells placed in the diffusion area 204. However, the virtual power supply voltage Virtual_V _DD may not be sufficiently supplied to some standard cell STD Cells located between the second diffusion region 202 and the fourth diffusion region 204. For a standard cell that is not sufficiently supplied with the virtual power supply voltage Virtual_V _DD , a fifth diffusion region 205 and a sixth diffusion region 206 and a third gate electrode G3 may be further provided. In this case, the virtual power voltage Virtual_V _DD output through the sixth diffusion region 206 can be supplied to adjacent standard cells, and therefore, the positions are closer to the second diffusion region 202 and the fourth diffusion region 204 The standard cell at the midpoint can be operated stably.

According to an exemplary embodiment of the present inventive concept, by providing the fifth and sixth diffusion regions 205 and 206 and the third gate electrode G3, additional supply of the virtual power supply voltage Virtual_V _DD can be achieved without any additional p-tap. Therefore, the virtual power supply voltage Virtual_V _DD can be efficiently and stably supplied to the standard cell STD Cells without increasing the chip size.

FIG. 8 is a plan view illustrating a power gate switching system 300 according to an exemplary embodiment of the inventive concept. 9 is a cross-sectional view taken along line BB′ shown in FIG. 8 according to an exemplary embodiment of the present inventive concept. The cross-sectional view taken along line AA' shown in FIG. 8 is omitted from FIG. 9 because it is substantially the same as that shown in FIG. 2.

Referring to FIGS. 8 and 9, the N-well N-well may be formed to extend in the first direction D1 in the p-type substrate P-sub. The P well P-well extending in the first direction may be formed adjacent to the N well N-well in the second direction D2. As shown in FIG. 8, N-well N-well and P-well P-well may be spaced apart from each other in the second direction D2, however, in the present invention In an exemplary embodiment, the N-well N-well and the P-well P-well may contact each other in the second direction D2.

The first diffusion region 301 to the sixth diffusion region 306 and the first p-tap P-tab1 to the fourth p-tap P-tab4 may be formed in the N-well N-well, and the first gate electrode G1 to the third gate electrode G3 may be Formed on N-well N-well. For example, the first diffusion region 301 to the sixth diffusion region 306, the first p-tap P-tab1 to the fourth p-tap P-tab4, and the first gate electrode G1 to the third gate electrode G3 may be configured to have The features explained with reference to FIGS. 6 to 7 are substantially the same features, and therefore, they will not be described in detail.

As shown in FIGS. 8 and 9, the first n-tap N-tab1 to the fourth n-tap N-tab4 extending in the second direction D2 and spaced apart from each other in the first direction D1 may be disposed in the P well P- well. In the P-well P-well, the first n-tap N-tab1 may be parallel to the second direction D2 and coaxial with the first p-tap P-tab1. In the P-well P-well, the second n-tap N-tab2 may be parallel to the second direction D2 and coaxial with the second p-tap P-tab2. In the P-well P-well, the third n-tap N-tab3 may be parallel to the second direction D2 and coaxial with the third p-tap P-tab3. In the P-well P-well, the fourth n-tap N-tab4 may be parallel to the second direction D2 and coaxial with the fourth p-tap P-tab4.

In an exemplary embodiment of the inventive concept, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be doped with p-type impurities, and the first n-tap N-tab1 to the fourth n-tap N-tab4 The doping concentration may be different from that of P-well P-well. The bias voltage Vbias2 may be applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 to prevent the latch-up phenomenon. In an exemplary embodiment of the inventive concept, the The bias voltage Vbias2 applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 may be a ground voltage.

As shown in FIG. 8, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be spaced apart from the first p-tap P-tab1 to the fourth p-tap P-tab4. However, the N-well N-well and the P-well P-well may contact each other, and each of the first n-tap N-tab1 to the fourth n-tap N-tab4 may be in the N-well N-well and P-well P- The boundary between wells is in contact with the corresponding one of the first p-tap P-tab1 to the fourth p-tap P-tab4.

The distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 can take into account the N-well N-well doping The concentration, P-well P-well doping concentration or a combination thereof is determined. For example, the distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 may be such as to prevent Within the range in which the latch-up phenomenon occurs in the switching system 300.

Similar to those described with reference to FIG. 3, the p-tap may be composed of only the first p-tap P-tab1 and the third p-tap P-tab3 or only the first p-tap P-tab1 and the fourth p-tap P-tab4 . Furthermore, the n-tap may be composed of only the first n-tap N-tab1 and the third n-tap N-tab3 or only the first n-tap N-tab1 and the fourth n-tap N-tab4. In addition, the power gate switching system 300 may further include multiple device isolation layers STI as shown in FIGS. 4 and 5.

FIG. 10 is a plan view illustrating a power gate switching system 400 according to an exemplary embodiment of the inventive concept. FIG. 11 is a cross-sectional view taken along line BB′ shown in FIG. 10 according to an exemplary embodiment of the inventive concept. Will be omitted from FIG. 11 as shown in FIG. 10 The cross-sectional view taken along line AA' is because it is substantially the same as that shown in FIG. 2.

10 and 11, the power gate switching system 400 will be described in detail below. The power gate switching system 400 may include: an N-well N-well formed to extend in the first direction D1; a first diffusion region 401 to a sixth diffusion region 406 and a first p-tap P-tab1 to a fourth p-tap P- Tab4 is formed in the N-well N-well; and the first gate electrode G1 to the third gate electrode G3 are formed on the N-well N-well. The first to sixth diffusion regions 401 to 406 may be doped with p-type impurities, and the first to fourth p-tabs P-tab1 to P-tab4 may be doped with n-type impurities. The first p-tap P-tab1 to the fourth p-tap P-tab4 may have a doping concentration different from that of the N-well N-well.

The distance between the first gate electrode G1 and the second gate electrode G2 can be determined in consideration of the doping concentration of the N-well N-well. In other words, the first gate electrode G1 and the second gate electrode G2 may be able to prevent the latch phenomenon from occurring in the power gate switching system 400 at a distance apart from each other. For example, the distance s1 between the first gate electrode G1 and the third gate electrode G3 may be in the range of 1/4 times to 3/4 times the distance s2 between the first gate electrode G1 and the second gate electrode G2 Inside.

The elements disposed in or on the N-well may have substantially the same characteristics as those explained with reference to FIGS. 1, 2, and 6, and therefore, they will not be described in detail.

The power gate switching system 400 may include seventh diffusion regions 407 to twelfth diffusion regions 412 formed in the p-type substrate P-sub to extend in the second direction D2 And is formed to be spaced apart from each other in the first direction D1. The first diffusion region 401 and the seventh diffusion region 407 may be formed to be the same as each other The axis, thereby forming a row. The seventh diffusion region 407 may be doped with n-type impurities. Similarly, each of the eighth diffusion region 408 to the twelfth diffusion region 412 may be formed to be coaxial with the corresponding one of the second diffusion region 402 to the sixth diffusion region 406, thereby forming individual rows.

The fourth gate electrode G4 may be formed on the p-type substrate P-sub and between the seventh diffusion area 407 and the eighth diffusion area 408. The fifth gate electrode G5 may be formed on the p-type substrate P-sub and between the ninth diffusion area 409 and the tenth diffusion area 410. The sixth gate electrode G6 may be formed on the p-type substrate P-sub and between the eleventh diffusion area 411 and the twelfth diffusion area 412. An insulating layer may be further provided between the fourth gate electrode G4, the fifth gate electrode G5, the sixth gate electrode G6, and the p-type substrate P-sub. For example, the seventh to twelfth diffusion regions 407 to 412 may be doped with n-type impurities.

The first n-tap N-tab1 and the second n-tap N-tab2 may be formed in the p-type substrate P-sub adjacent to the seventh diffusion area 407 and the eighth diffusion area 408, respectively. Although the first n-tap N-tab1 and the second n-tap N-tab2 are shown not in direct contact with the seventh and eighth diffusion regions 407 and 408, the first n-tap N-tab1 and the second n-tap N -tab2 may directly contact the seventh diffusion area 407 and the eighth diffusion area 408, respectively. The first n-tap N-tab1 to the fourth n-tap N-tab4 may be doped with p-type impurities. The first n-tap N-tab1 to the fourth n-tap N-tab4 may have a doping concentration different from that of the p-type substrate P-sub.

The ground voltage V _SS may be applied to the seventh diffusion region 407. Depending on the voltage Gate_CTRL applied to the fourth gate electrode G4, the ground voltage V _SS may be used as the virtual ground voltage Virtual_V _SS to be output through the eighth diffusion region 408. The virtual ground voltage Virtual_V _SS may be supplied to at least one standard cell located adjacent thereto. The ground voltage V _SS may also be supplied to at least one standard cell located adjacent thereto.

To prevent the latch-up phenomenon in the power gate switching system 400, the bias voltage Vbias2 may be applied to the first n-tap N-tab1 and the second n-tap N-tab2. Although the bias voltage Vbias2 is shown as being applied separately to the first n-tap N-tab1 and the second n-tap N-tab2, the ground voltage V _SS may be applied to the first n-tap N-tab1 and the second n-tap1 instead of the bias voltage Vbias2. Two n-tap N-tab2.

The third n-tap N-tab3 and the fourth n-tap N-tab4 may be formed in the p-type substrate P-sub adjacent to the ninth diffusion area 409 and the tenth diffusion area 410, respectively. Although the third n-tap N-tab3 and the fourth n-tap N-tab4 are shown as not in direct contact with the ninth diffusion area 409 and the tenth diffusion area 410, respectively, the third n-tap N-tab3 and the fourth n-tap N-tab4 may be formed to directly contact the ninth diffusion region 409 and the tenth diffusion region 410, respectively.

The ground voltage V _SS may be applied to the ninth diffusion region 409. Depending on the voltage Gate_CTRL applied to the fifth gate electrode G5, the ground voltage V _SS may be used as the virtual ground voltage Virtual_V _SS to be output through the tenth diffusion region 410. The virtual ground voltage Virtual_V _SS may be supplied to at least one standard cell located adjacent thereto. The ground voltage V _SS may also be supplied to at least one standard cell located adjacent thereto.

The bias voltage Vbias2 may be applied to the third n-tap N-tab3 and the fourth n-tap N-tab4. Although the bias voltage Vbias2 is shown as being applied separately to the third n-tap N-tab3 and the fourth n-tap N-tab4, the ground voltage V _SS may be applied to the third n-tap N-tab3 and the third instead of the bias voltage Vbias2. Four n-tap N-tab4.

In the case of a virtual ground voltage via the output Virtual_V _SS eighth or tenth diffusion region 408 in the diffusion region 410, the virtual ground voltage Virtual_V _SS can be sufficiently supplied to the standard cell adjacent to the eighth or tenth diffusion region 408 of the element diffusion region 410 . However, the virtual ground voltage Virtual_V _SS may not be sufficiently supplied to other standard cells between the eighth diffusion region 408 and the tenth diffusion region 410. For such standard cells that are not sufficiently supplied with the virtual ground voltage Virtual_V _SS , the eleventh diffusion region 411 and the twelfth diffusion region 412 and the sixth gate electrode G6 may be further provided.

For example, the sizes of the eleventh diffusion region 411 and the twelfth diffusion region 412 (eg, the width in the first direction D1) may be smaller than the sizes of the seventh diffusion region 407 to the tenth diffusion region 410 (eg, at Width in the first direction D1). The size of the sixth gate electrode G6 (for example, the width in the first direction D1) may also be smaller than the size of the fourth gate electrode G4 or the fifth gate electrode G5 (for example, the width in the first direction D1).

According to an exemplary embodiment of the inventive concept, since the fifth diffusion region 405 and the sixth diffusion region 406, the third gate electrode G3, the eleventh diffusion region 411 and the twelfth diffusion region 412, and the sixth gate electrode G6 are provided Therefore, the virtual power voltage Virtual_V _DD can be stably supplied to the virtual ground voltage Virtual_V that is not sufficiently supplied on the weak region (for example, between the diffusion region 402 and the diffusion region 404 or between the diffusion region 408 and the diffusion region 410) Standard cell of _SS . In addition, by adding relatively small components without p-tap or n-tap, the size of the semiconductor wafer can be reduced.

FIG. 12 is a plan view illustrating a power gate switching system 500 according to an exemplary embodiment of the inventive concept. FIG. 13 is an exemplary embodiment according to the inventive concept A cross-sectional view taken along line BB′ shown in FIG. 12. The cross-sectional view taken along line AA' shown in FIG. 12 is omitted from FIG. 13 because it is substantially the same as that shown in FIG. 2.

12 and 13, the power gate switching system 500 will be described in detail below. The power gate switching system 500 shown in FIGS. 12 and 13 may include a p-type substrate P-sub, and an N-well N-well and a P-well P-well are formed in the p-type substrate P-sub. The N-well N-well and the P-well P-well may be adjacent to each other in the second direction D2 and may extend in the first direction D1.

The power gate switching system 500 may include: a seventh diffusion region 507 to a twelfth diffusion region 512 and a first n-tap N-tab1 to a fourth n-tap N-tab4 formed in the P-well P-well, and formed in P The fourth gate electrode G4 to the sixth gate electrode G6 on the well P-well. Otherwise, the power gate switching system 500 may be similar to those shown in FIGS. 10 and 11. For example, the power gate switching system 500 may include first to sixth diffusion regions 501 to 506 and first to fourth p-tab1 to fourth p-tab4 formed in N-well N-well, and formed The first gate electrode G1 to the third gate electrode G3 on the N-well N-well. Therefore, it will not be repeated here.

In an exemplary embodiment of the present inventive concept, the distance s1 between the first gate electrode G1 and the third gate electrode G3 may be 1/4 times the distance s2 between the first gate electrode G1 and the second gate electrode G2 To a range of 3/4 times, and the distance s1 between the fourth gate electrode G4 and the sixth gate electrode G6 may be 1/4 times the distance s2 between the fourth gate electrode G4 and the fifth gate electrode G5 to Within 3/4 times the range. The size of each of the diffusion regions 505, 506, 511, and 512 (eg, the width in the first direction D1) may be smaller than the size of each of the diffusion regions 501 to 504 or 507 to 510 (eg, Width in the first direction D1). The size of each of the gate electrode G3 and the gate electrode G6 (for example, the width in the first direction D1) may also be smaller than the size of each of the gate electrodes G1, G2, G4, and G5 (for example, in the first Width in one direction D1).

14 is a plan view illustrating the layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept. For simplicity, the device isolation layer (eg, STI shown in FIG. 4) is omitted from FIG.

Referring to FIG. 14, a plurality of N-well N-wells extending in the first direction D1 and spaced apart from each other in the second direction D2 may be formed in the p-type substrate P-sub. For example, the N-well N-well may extend parallel to the first row Row1, the third row Row3, and the fifth row Row5. In FIG. 14, the N-well N-well is shown by cross hatching. As shown in FIG. 14, the virtual power line Virtual_V _DD may be arranged to cross the N-well N-well in the first direction D1, and the ground line V _SS may be arranged to cross the p-type substrate P- in the first direction D1 sub. The distance between the virtual power line Virtual_V _DD and the ground line V _SS measured in the second direction D2 is called 1H.

The various standard cells constituting the semiconductor logic circuit and the power gate switch system for supplying the virtual power voltage Virtual_V _DD to the standard cells can be placed on the p-type substrate P-sub and the N-well N-well. The power gate cell and its adjacent p-tap can be evenly arranged by using a layout design tool.

For example, the first cell 601 may overlap the N-well N-well located on the first row Row1. The first cell 601 may include at least one gate electrode and at least one diffusion region. At least two diffusion regions of the first cell 601 may be regions doped with p-type impurities. Two p-tap may be provided adjacent to the first cell 601. As shown in Figure 14, the The two p-tap may directly contact the first cell 601 or not. Although two p-tap are shown, as described above, the p-tap may be formed individually. For example, the p-tap may be doped with n-type impurities, and the doping concentration of the p-tap may be different from that of N-well N-well.

The second cell 602 may be spaced apart from the first cell 601 by a distance s3 and may overlap the N-well N-well located on the first row Row. Similar to the first cell 601, the second cell 602 may include at least one gate electrode and at least two diffusion regions. The distance between the first cell 601 and the second cell 602 (for example, s3) may be determined in consideration of the N-well N-well doping concentration. For example, the first cell 601 and the second cell 602 may be able to prevent the latch-up phenomenon from being spaced apart from each other. The second cell 602 and the first cell 601 may be configured to have substantially the same characteristics except for their positions, and therefore, they will not be described in detail.

The third cell 603 may overlap the N-well N-well located on the third row Row3. As shown in FIG. 14, the third cell 603 may be positioned between the first cell 601 and the second cell 602. The third cell 603 and the first cell 601 may be configured to have substantially the same characteristics except for their positions, and therefore, they will not be described in detail.

The fourth cell 604 and the fifth cell 605 may overlap the N-well N-well located on the fifth row Row5. The fourth cell 604, the fifth cell 605, and the first cell 601 may be configured to have substantially the same characteristics except for their positions, and therefore, they will not be described in detail.

As shown in FIG. 14, even if the first cell 601 to the fifth cell 605 are evenly arranged, at least one standard cell arranged between the respective cells may have a shortage or voltage of the virtual power supply voltage Virtual_V _DD drop. In such a situation where the pressure drop is large, at least one standard cell placed between each cell may operate abnormally. By providing the first additional cell 611 to the third additional cell 613, it is possible to prevent at least one standard cell in which a large pressure drop occurs from operating abnormally. For example, the pressure drop at the location of the additional cell 611 to the additional cell 613 may not be large.

The first additional cell 611 may overlap the N-well N-well located on the first row Row1. The first additional cell 611 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions of the first additional cell 611 may be doped with p-type impurities. However, unlike the first cell 601 to the fifth cell 605, the p-tap may not be provided in the first additional cell 611. The size of the first additional cell 611 may be smaller than the size of at least one of the first cell 601 to the fifth cell 605. For example, the size (eg, the width in the first direction D1) of the gate electrode of the first additional cell 611 may be equal to or smaller than that of at least one of the first cell 601 to the fifth cell 605 size. In addition, the size (eg, the width in the first direction D1) of the diffusion region of the first additional cell 611 may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. In addition, the distance s1 between the first cell 601 and the first additional cell 611 may be in the range of 1/4 to 3/4 times the distance s3 between the first cell 601 and the second cell 602 .

The second additional cell 612 may overlap the N-well N-well located on the third row Row3 and the fifth row Row5. The second additional cell 612 may include at least one gate electrode and at least four diffusion regions. In other words, the diffusion regions of the third row Row3 and the fifth row Row5 may be configured to share the gate electrode. The at least four of the second additional cell 612 Each diffusion region may be doped with p-type impurities. Unlike the first cell 601 to the fifth cell 605, the p-tap may not be provided in the second additional cell 612. The size of the second additional cell 612 may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. In other words, the size (eg, the width in the first direction D1) of the gate electrode of the second additional cell 612 may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. The size (eg, the width in the first direction D1) of the diffusion region of the second additional cell 612 may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. Although the second additional cell 612 is shown as having a length of 3H in the second direction D2, the inventive concept is not limited to this.

The third additional cell 613 may overlap the N-well N-well located on the third row Row3. The third additional cell 613 may include at least one gate electrode and at least two diffusion regions. The third additional cell 613 and the second cell 602 may be configured to share the same gate electrode (eg, the at least one gate electrode). The third additional cell 613 and the fifth cell 605 may be configured to share the same gate electrode (eg, the at least one gate electrode).

The at least two diffusion regions of the third additional cell 613 may be doped with p-type impurities. Unlike the first cell 601 to the fifth cell 605, the p-tap may not be provided in the third additional cell 613. The third additional cell 613 may have a size equal to or smaller than at least one of the first cell 601 to the fifth cell 605. In other words, the size of the gate electrode of the third additional cell 613 (for example, the width in the first direction D1) may be equal to or smaller than the size of the first cell 601 to the fifth cell 605. Third accessory cell The size of the diffusion region of the cell 613 (for example, the width in the first direction D1) may be equal to or smaller than the sizes of the first cell 601 to the fifth cell 605.

As explained with reference to FIG. 14, by arranging a plurality of cells 601 to 605 and a plurality of additional cells 611 to 613, the virtual power supply voltage Virtual_V _DD can be sufficiently supplied to a region disposed at a region where a large voltage drop can exist Standard cell. In addition, since each of the additional cell 611 to the additional cell 613 has a smaller size than each of the cell 601 to 605, the size of the semiconductor chip can be reduced and the place can be strategically placed Describe the standard cell.

15 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept. For simplicity, the device isolation layer (eg, STI shown in FIG. 4) is omitted from FIG. The layout of the semiconductor device shown in FIG. 15 may be configured to have features that are substantially the same as or similar to those shown in FIG. 14 except that a plurality of n-tap is provided, and therefore, the previous The explanation will be made with reference to the elements explained in FIG. 14. For example, FIG. 15 shows the first cell 701 to the fifth cell 705 similar to the first cell 601 to the fifth cell 605 shown in FIG. 14 and the additional cell 611 shown in FIG. 14 The additional cell 711 to the additional cell 713 are similar to the additional cell 613.

A plurality of n-tap may be arranged to overlap the p-type substrate P-sub. For example, each of the n-tap may be arranged to extend in the second direction D2, and at least one of the n-tap may be adjacent to a corresponding one of the p-tap. Although the adjacent pair of p-tap and n-tap are shown as being spaced apart from each other, they may directly contact each other at the boundary between the N-well N-well and the p-type substrate P-sub. Said much The n-tap may be doped with p-type impurities, and the doping concentration of the n-tap may be different from the doping concentration of the p-substrate P-sub. In addition, the P-well P-well doped with p-type impurities may overlap with the p-type substrate P-sub. In this case, the n-tap may overlap with the P-well P-well.

16 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept. For simplicity, the device isolation layer (eg, STI shown in FIG. 4) is omitted from FIG. 16.

The semiconductor device shown in FIG. 16 may include elements overlapping N-well N-well and have substantially the same characteristics as those shown in FIGS. 14 and 15, and therefore, for simplicity, it will not be provided Repeat. In addition, the semiconductor device shown in FIG. 16 may include an n-tap that overlaps with the p-type substrate P-sub or P-well P-well and has substantially the same characteristics as those shown in FIG. 15, and therefore, For brevity, they will not be repeated here. For example, FIG. 16 shows the first cell 801 to the fifth cell 805 similar to the first cell 601 to the fifth cell 605 shown in FIG. 14.

Referring to FIG. 16, the sixth cell 821 to the tenth cell 825 may be disposed on the p-type substrate P-sub. Each of the sixth cell 821 to the tenth cell 825 may include at least one gate electrode and at least two diffusion regions. As shown in FIG. 16, each of the sixth cell 821 to the tenth cell 825 may be disposed between two n-tap.

The first additional cell 811 may be configured to have substantially the same characteristics as the first additional cell 711 shown in FIG. 15, and therefore, for the sake of brevity, they will not be described in detail.

The second additional cell 812 may extend from the second row Row2 to the fourth row Row4 in the second direction D2. For example, as shown in FIG. 16, the second additional cell 812 may have a length of 2H. The second additional cell 812 may include at least two diffusion regions formed in the p-type substrate P-sub of the second row Row2, and at least two diffusion regions formed in the N-well N-well of the third row Row3. At least two diffusion regions and at least one gate electrode in the p-type substrate P-sub in the third row Row3. In this case, the diffusion region may be configured to share the at least one gate electrode. However, in the case where two or more gate electrodes are provided, the diffusion region may not share a single gate electrode. For example, the diffusion region formed in the N-well N-well may be doped with p-type impurities, and the diffusion region formed in the p-type substrate P-sub may be doped with n-type impurities.

The third additional cell 813 may extend from the second row Row2 to the fourth row Row4 in the second direction D2. For example, as shown in FIG. 16, the second additional cell 812 may have a length of 2H. The third additional cell 813 may include at least two diffusion regions formed in the p-type substrate P-sub of the second row Row2, and at least two diffusion regions formed in the N-well N-well of the third row Row3. At least two diffusion regions and at least one gate electrode in the p-type substrate P-sub in the third row Row3.

For example, the diffusion region of the third additional cell 813 in the second row Row2 may be configured to share the diffusion region of the seventh cell 822 and the gate electrode. Furthermore, the diffusion region of the third additional cell 813 in the fourth row Row4 may be configured to share the diffusion region of the tenth cell 825 and the gate electrode. In other words, at least a part or all of the diffusion region of the third additional cell 813 may be configured to share the gate electrode of at least one of the seventh cell 822 and the tenth cell 825.

17A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept. The plan view shown in FIG. 17A is similar to the plan view shown in FIG. 10. Therefore, the difference between the two schemes will be mainly explained.

For example, as shown in FIG. 17A, the power gate switching system 1100 may include an upper column, a middle column, and a bottom column.

The upper column may include those disposed between the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) and connected to the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) First power gate cell (first p-tap P-tab1, diffusion area 1101, first gate electrode G1, diffusion area 1102, second p-tap P-tab2), second power gate cell (diffusion area 1105, first Three gate electrode G3, diffusion region 1106) and a third power gate cell (third p-tap P-tab3, diffusion region 1103, second gate electrode G2, diffusion region 1104, fourth p-tap P-tab4). In other words, the upper column shows a P-channel metal oxide semi-conductor (PMOS) power gate cell connected between the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) yuan. The upper column may further include a circuit disposed between the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) and connected to the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) Multiple standard cells (Std). The plurality of standard cells (Std) may be arranged between the PMOS power gate cells in the upper column. Each of the plurality of standard cells (Std) may include a PMOS transistor on the N-well N-well and an n-channel metal oxide semiconductor on the p-type substrate P-sub conductor, NMOS) transistor. As shown in FIG. 17A, the N-well N-well of the PMOS transistor of each of the plurality of standard cells may be merged with the N-well N-well of the PMOS power gate cell in the upper column. The shape of the merged N-well N-well with PMOS gate cells may be different from the shape of the N-well N-well in FIG. 10 because of the arrangement between the first to third power gate cells of the PMOS One of the multiple standard cells includes an NMOS transistor on the p-type substrate P-sub.

The bottom column may include those disposed between the virtual ground line Virtual_V _SS and the power line V _DD (or virtual power line Virtual_V _DD ) and connected to the virtual ground line Virtual_V _SS and the power line V _DD (or virtual power line Virtual_V _DD ) Fourth power gate cell (first n-tap N-tab1, diffusion area 1107, fourth gate electrode G4, diffusion area 1108, second n-tap N-tab2), fifth power gate cell (diffusion area 1111, first Six gate electrodes G6, diffusion area 1112) and a sixth power gate cell (third n-tap N-tab3, diffusion area 1109, fifth gate electrode G5, diffusion area 1110, fourth n-tap N-tab4). In other words, the bottom column shows the NMOS power gate cells connected between the virtual ground line Virtual_V _SS and the virtual power line Virtual_V _DD (or power line V _DD ). The bottom column may further include a power line V _DD (or virtual power line Virtual_V _DD ) and a virtual ground line Virtual_V _SS connected to the power line V _DD (or virtual power line Virtual_V _DD ) and a virtual ground line Virtual_V _SS Multiple standard cells (Std). The plurality of standard cells (Std) may be arranged between the NMOS power supply gate cells in the bottom column. Each of the plurality of standard cells (Std) may include a PMOS transistor on the N-well N-well and an NMOS transistor on the p-type substrate P-sub. Therefore, the N-well N-well of the PMOS transistor of the standard cell placed between the NMOS power gate cells in the bottom row can be placed on the p-type substrate P-sub in the bottom row. As shown in FIG. 17A, the N-well N-well of the PMOS transistor of each of the plurality of standard cells may be merged with the N-well N-well of the plurality of standard cells in the middle column.

The middle column may include a pair of virtual ground lines Virtual_V _SS and the power line V _DD , a pair of virtual power lines Virtual_V _DD and the ground line V _SS , or a pair of virtual power lines Virtual_V _DD and the virtual ground line Virtual_V Standard cells between _SS and connected to a pair of virtual ground lines Virtual_V _SS and power lines V _DD , a pair of virtual power lines Virtual_V _DD and ground lines V _SS or a pair of virtual power lines Virtual_V _DD and virtual ground lines Virtual_V _SS Std).

The power gate switching system 1100 may further include a plurality of intermediate columns connected to the virtual ground line Virtual_V _SS or the virtual power line Virtual_V _DD . One of the plurality of middle columns may be connected to the virtual ground line Virtual_V _SS connected to the NMOS power gate cell or may be connected to the ground line V _SS . The other middle columns of the plurality of middle columns may be connected to the virtual power line Virtual_V _DD connected to the PMOS power gate cell or may be connected to the power line V _DD . Here, one of the first to sixth power gate cells can be extended to at least one of the middle columns to provide a virtual power line Virtual_V _DD node or a virtual ground line Virtual_V _SS node into the middle column The plurality of standard cells in at least one of.

17B is a cross-sectional view taken along line AA′ shown in FIG. 17A according to an exemplary embodiment of the present inventive concept. The element shown in FIG. 17B corresponds to the element shown in FIG. 12. Therefore, the difference between the two schemes will be mainly explained. Examples In particular, FIG. 17B shows an N-well N-well discontinuous in the D1 direction on the p-type substrate P-sub. The NMOS transistor of the standard cell can be disposed on the p-type substrate P-sub between the first to third power gate cells.

FIG. 17C is a cross-sectional view taken along line BB′ shown in FIG. 17A according to an exemplary embodiment of the inventive concept. The element shown in FIG. 17C corresponds to the element shown in FIG. 11. Therefore, the difference between the two schemes will be mainly explained. For example, FIG. 17B shows an NMOS power gate cell connected to the ground line V _SS and the virtual ground line Virtual_V _SS . The N-well N-well of the PMOS transistor of the standard cell can be disposed on the p-type substrate P-sub between the fourth to sixth power gate cells.

FIG. 18A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept. The plan view shown in FIG. 18A is similar to the plan view shown in FIG. Therefore, the difference between the two schemes will be mainly explained.

For example, as shown in FIG. 18A, the power gate switching system 1200 may include an upper column, a middle column, and a bottom column.

The upper column includes the first row disposed between the virtual power line Virtual_V _DD and the virtual ground line Virtual_V _SS (or ground line V _SS ) and connected to the virtual power line Virtual_V _DD and the virtual ground line Virtual_V _SS (or ground line V _SS ) A power gate cell (first p-tap P-tab1, diffusion area 1201, first gate electrode G1, diffusion area 1202, second p-tap P-tab2), a second power gate cell (diffusion area 1205, third Gate electrode G3, diffusion region 1206) and the third power gate cell (third p-tap P-tab3, diffusion region 1203, second gate electrode G2, diffusion region 1204, fourth p-tap P-tab4). In other words, the upper column shows the PMOS power gate cells connected between the virtual power line Virtual_V _DD and the virtual ground line Virtual_V _SS (or ground line V _SS ). The upper column may further include a circuit disposed between the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) and connected to the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) Multiple standard cells (Std). The plurality of standard cells (Std) may be arranged between the PMOS power gate cells in the upper column. Each of the plurality of standard cells (Std) may include a PMOS transistor on N-well N-well and an NMOS transistor on P-well P-well. As shown in FIG. 18A, the N-well N-well of the PMOS transistor of each of the plurality of standard cells in the upper column may be merged with the N-well N-well of the PMOS power gate cell in the upper column. The shape of the merged N-well with PMOS gate cells may be different from the shape of the N-well N-well in FIG. 12 because of the multiple standard cells placed between the first to third power gate cells of PMOS One of them includes the NMOS transistor on P-well P-well.

The bottom column includes the first row disposed between the virtual ground line Virtual_V _SS and the power line V _DD (or virtual power line Virtual_V _DD ) and connected to the virtual ground line Virtual_V _SS and the power line V _DD (or virtual power line Virtual_V _DD ) Four power gate cells (first n-tap N-tab1, diffusion area 1207, fourth gate electrode G4, diffusion area 1208, second n-tap N-tab2), fifth power gate cell (diffusion area 1211, sixth Gate electrode G6, diffusion area 1212) and sixth power gate cell (third n-tap N-tab3, diffusion area 1209, fifth gate electrode G5, diffusion area 1210, fourth n-tap N-tab4). In other words, the bottom column shows the NMOS power gate cells connected between the virtual ground line Virtual_V _SS and the virtual power line Virtual_V _DD (or power line V _DD ). The bottom column further includes the one disposed between the power line V _DD (or virtual power line Virtual_V _DD ) and the virtual ground line Virtual_V _SS and connected to the power line V _DD (or virtual power line Virtual_V _DD ) and the virtual ground line Virtual_V _SS Multiple standard cells (Std). The plurality of standard cells (Std) may be arranged between the NMOS power supply gate cells in the bottom column. Each of the plurality of standard cells (Std) may include a PMOS transistor on N-well N-well and an NMOS transistor on P-well P-well. Therefore, the N-well N-well of the PMOS transistor of the standard cell placed between the NMOS fourth to sixth power gate cells in the bottom row can be placed on the p-type substrate away from the P-well P-well in the bottom row P-sub. As shown in FIG. 18A, the N-well N-well of the PMOS transistor of each of the plurality of standard cells in the bottom column may be merged with the N-well N-well of the plurality of standard cells in the middle column.

The middle column may include a pair of virtual ground lines Virtual_V _SS and the power line V _DD , a pair of virtual power lines Virtual_V _DD and the ground line V _SS , or a pair of virtual power lines Virtual_V _DD and the virtual ground line Virtual_V Standard cells between _SS and connected to a pair of virtual ground lines Virtual_V _SS and power lines V _DD , a pair of virtual power lines Virtual_V _DD and ground lines V _SS or a pair of virtual power lines Virtual_V _DD and virtual ground lines Virtual_V _SS Std). The power gate switching system 1200 may further include a plurality of intermediate columns connected to the virtual ground line Virtual_V _SS or the virtual power line Virtual_V _DD . One of the plurality of middle columns may be connected to the virtual ground line Virtual_V _SS connected to the NMOS power gate cell or may be connected to the ground line V _SS . The other middle columns of the plurality of middle columns may be connected to the virtual power line Virtual_V _DD connected to the PMOS power gate cell or may be connected to the power line V _DD . Here, one of the first to sixth power gate cells can be extended to at least one of the middle columns to provide a virtual power line Virtual_V _DD node or a virtual ground line Virtual_V _SS node into the middle column The plurality of standard cells in at least one of.

18B is a cross-sectional view taken along line AA′ shown in FIG. 18A according to an exemplary embodiment of the present inventive concept. The element shown in FIG. 18B corresponds to the element shown in FIG. 12. Therefore, the difference between these two drawings will be mainly explained with reference to FIGS. 2 and 12. For example, FIG. 18B shows a cross-sectional view of a discontinuous N-well N-well of the PMOS first to third power gate cells on the p-type substrate P-sub in the D1 direction and the standard cell One of the NMOS transistors is placed in the P-well P-well between the discontinuous N-well N-wells. The standard cell NMOS transistor can be formed on the P-well P-well.

18C is a cross-sectional view taken along line BB′ shown in FIG. 18A according to an exemplary embodiment of the inventive concept. The element shown in FIG. 18C corresponds to the element shown in FIG. 13. Therefore, the difference between these two drawings will be mainly explained with reference to FIGS. 18A and 13. For example, FIG. 18C shows one of the P-well P-well and the standard cell which are discontinuous in the direction D1 of the NMOS fourth to sixth power gate cells on the p-type substrate P-sub in a cross-sectional view. The PMOS transistor is placed between the discontinuous P-well P-well and the N-well N-well. Standard cell PMOS transistors can be formed on N-well N-well.

19 is a plan view illustrating the layout of a semiconductor device applied to a power gate switching system according to an exemplary embodiment of the inventive concept.

Specifically, FIG. 19 shows a plurality of PMOS power gate cells connected to a plurality of virtual power lines Virtual_V _DD and a ground line V _SS (or virtual ground line Virtual_V _SS ). Each of the PMOS power gate cells may have at least one p-tap on both sides and may have at least one n-tap on both sides. This can be seen in Figure 19. In Figure 19, the PMOS tap (or tap) is identified as "PT", the NMOS tap (or tap) is identified as "NT", the diffusion break (diffusion break) is identified as "DB" and the The standard cell identification is "Std. Cells". FIG. 19 further shows the ground line V _SS (or virtual ground line Virtual_V _SS ) extending longitudinally along the top and bottom of the column of PMOS power gate cells. In addition, one of the virtual power line Virtual_V _DD and the ground line V _SS (or virtual ground line Virtual_V _SS ) extends longitudinally through the middle of each column of the PMOS power gate cells. The distance W_pg2pg may be the minimum distance required between the power supply cells.

It should be further understood that there may be P wells in the standard cell region (for example, the standard cell region Region I in FIG. 19). In addition, there may be N wells in the region Region II adjacent to the standard cell region Region I. The N well in Region II can be penetrated by the virtual power line Virtual_V _DD . In addition, the line disposed between the NMOS taps NT may be the power supply line NVSS to connect the NMOS taps NT to each other.

Referring to FIG. 19, the semiconductor device 1300 may include various types of power gate cells. For example, the first type of PMOS power gate cell may include p-tap PT on both sides of the PMOS power gate transistor in the PMOS power gate cell. The PMOS power gate cell of the first type may include n-tap NT on both ends of the PMOS power gate cell. The PMOS power gate cell may include one or more PMOS transistors connected in parallel between the virtual power line Virtual_V _DD and the virtual ground line Virtual_V _SS (or ground line V _SS ). The second type of PMOS power gate cell may include one or more PMOS transistors connected in parallel between the virtual power line Virtual_V _DD and the virtual ground line Virtual_V _SS (or ground line V _SS ) without the PMOS power gate cell Both ends include p-tap PT or n-tap NT. The number of PMOS transistors can be proportional to the current driving capability of the PMOS power gate cells.

The first type of PMOS power gate cells may be aligned in a vertical area including a plurality of virtual power lines Virtual_V _DD and the second type of PMOS power gate cells may be aligned in a vertical area including a plurality of virtual power lines Virtual_V _DD Align. The position, type, or number of PMOS power gate cells in the plan layout of the semiconductor device 1300 may vary according to the power supplied by the PMOS power gate cells.

According to an exemplary embodiment of the present inventive concept, it is possible to provide a power gate switching system to efficiently supply a virtual power supply voltage to a region of a semiconductor device where a large voltage drop can occur.

According to an exemplary embodiment of the inventive concept, a power gate switching system can be realized with improved regional efficiency.

Although the inventive concept has been specifically illustrated and explained with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art should understand that it can be made without departing from the spirit and scope of the accompanying patent application scope Various changes in form and detail.

100‧‧‧Power switch system

101‧‧‧The first diffusion zone

102‧‧‧Second diffusion area

103‧‧‧The third diffusion zone

104‧‧‧Diffusion area

105‧‧‧ fifth diffusion zone

106‧‧‧Sixth diffusion area

D1‧‧‧First direction

D2‧‧‧Second direction

D3‧‧‧third direction

G1‧‧‧First gate electrode

G2‧‧‧Second gate electrode

G3‧‧‧The third gate electrode

N-well‧‧‧N well

P-sub‧‧‧p-type substrate

P-tab1‧‧‧The first p-tap

P-tab2‧‧‧Second p tap

P-tab3‧‧‧third tap

P-tab4‧‧‧ fourth tap

s1, s2‧‧‧ distance

Virtual_V _DD ‧‧‧Virtual power supply voltage/Virtual power supply line

Claims (31)

A semiconductor device includes: a virtual power line extending in a first direction; an n-well extending in the first direction, wherein the virtual power line and the n-well are arranged in a row; a first power gate switch A cell is arranged in the n well; a second power gate switch cell is arranged in the n well, wherein the first power gate switch cell and the second power gate switch cell are the first type cells Element; and a third power gate switch cell, disposed in the n-well between the first power gate switch cell and the second power gate switch cell, wherein the third power gate switch cell It is a second type cell different from the first type cell. The semiconductor device according to item 1 of the patent application scope, wherein the third power gate switch cell is closer to the first power gate switch cell than the second power gate switch cell. The semiconductor device according to item 1 of the patent application range, wherein the third power gate switch cell is located closer to the second power gate switch cell than the first power gate switch cell. The semiconductor device according to item 1 of the patent application range, wherein each of the first type cells includes a gate electrode disposed between a pair of diffusion regions and one disposed adjacent to one of the diffusion regions Tap. The semiconductor device according to item 4 of the patent application range, wherein the tap is a p-tap, and in a column adjacent to the column of the n-well, the p-tap The n-tap is placed on the same axis, and the n-tap is connected to the ground line. The semiconductor device according to item 4 of the patent application range, wherein the second-type cell includes a gate electrode disposed between a pair of diffusion regions, and wherein the second-type cell does not include a tap. The semiconductor device according to item 1 of the patent application range, wherein the size of the second type cell is smaller than the size of each of the first type cell. The semiconductor device according to item 1 of the patent application scope, wherein the n-well is disposed in a p-type substrate. The semiconductor device according to item 1 of the patent application range, wherein the n-well is doped with n-type impurities. The semiconductor device according to item 1 of the patent application range, wherein the first power gate switch cell includes a gate electrode disposed between the first diffusion region and the second diffusion region, and the first diffusion region or The first tap arranged in the second diffusion area. The semiconductor device of claim 10, wherein the first diffusion region and the second diffusion region are doped with p-type impurities and the first tap is doped with n-type impurities. The semiconductor device of claim 10, wherein the first tap is connected to the virtual power line, the first diffusion area is connected to the real power line, and the second diffusion area is connected to the virtual power cable. The semiconductor device according to item 12 of the patent application scope, wherein the third power gate switch cell includes a cell disposed between the third diffusion region and the fourth diffusion region A gate electrode, and wherein the second type cell does not include a tap, and wherein the third diffusion region is connected to the real power line and the fourth diffusion region is connected to the virtual power line. A power gate switching system includes: a first virtual power line extending in a first direction; a first power gate cell connected to the first virtual power line; a second power gate cell connected to the first A virtual power line, wherein the first power gate cell and the second power gate cell each include at least one tap; and a third power gate cell, connected to the first virtual power line and disposed on the Between the first power gate cell and the second power gate cell, wherein the third power gate cell does not include a tap, and wherein the first power gate cell to the third power gate cell The cells and the first virtual power line are arranged in the first column. The power gate switching system as described in item 14 of the patent scope further includes: a second virtual power line extending in the first direction; a fourth power gate cell connected to the second virtual power line; And a fifth power gate cell connected to the second virtual power line, wherein each of the fourth power gate cell and the fifth power gate cell includes at least one tap, wherein the first Four power gate cells and the fifth power gate cells and the first The two virtual power lines are arranged in the second column. The power gate switching system according to item 14 of the patent application scope, wherein the first column includes a plurality of logic cells arranged between the first power gate cell and the third power gate cell, And a plurality of logic cells arranged between the second power gate cell and the third power gate cell. The power gate switching system according to item 14 of the patent application scope, wherein the first column includes: an n-well area disposed on the first side and the second side of the first virtual power line; the first ground line , Placed on the first side of the first virtual power line; and a second ground line, placed on the second side of the first virtual power line. The power gate switching system as described in item 17 of the patent application scope further includes: a first p-well area extending in the first direction and disposed on the first side of the first virtual power line Between the first ground line and the n-well area; and a second p-well area, extending in the first direction and disposed on the second side of the first virtual power line on the Between the second ground line and the n-well area. The power gate switching system according to item 17 of the patent application scope, wherein the first power gate cell includes a p-tap connected to the first virtual power line and a first n connected to the first ground line Tap. The power gate switching system as described in item 19 of the patent application scope, in which The first power gate cell includes a second n-tap connected to the second ground line. The power gate switching system according to item 20 of the patent application range, wherein the first n-tap, the p-tap, and the second n-tap are arranged in sequence. A power gate switching system includes: a first row including a first virtual power line, a first power gate cell and a second power gate cell, wherein the first power gate cell includes a first diffusion area and A first gate electrode and at least one tap between the second diffusion regions, wherein the second power gate cell includes a second gate electrode disposed between the third diffusion region and the fourth diffusion region and the second power source The gate cell does not include taps; and the second row includes the second virtual power line, the third power gate cell and the fourth power gate cell, wherein the third power gate cell includes the fifth diffusion region and A third gate electrode between the sixth diffusion region and at least one tap, and the fourth power gate cell includes a fourth gate electrode disposed between the seventh diffusion region and the eighth diffusion region and the fourth power source The gate cell does not include taps, and wherein the fourth power gate cell is connected to the second power gate cell. The power gate switching system according to item 22 of the patent application scope, wherein the first row and the second row extend in the first direction, and the gate control line and the position of the second power gate cell The gate control line of the fourth power gate cell extends in a second direction that is substantially perpendicular to the first direction. The power gate switching system of claim 22, wherein the first power gate cell includes a device isolation layer adjacent to the at least one tap, and the second power gate cell includes adjacent to the first Three diffusion regions and the fourth diffusion A device isolation layer for each of the zones. The power gate switching system as described in Item 22 of the patent application scope further includes: a third row, including a third virtual power line, a fifth power gate cell and a sixth power gate cell, wherein the fifth power gate The cell includes a fifth gate electrode and at least one tap disposed between the ninth diffusion region and the tenth diffusion region, and the sixth power gate cell includes one disposed between the eleventh diffusion region and the twelfth diffusion region Between the sixth gate electrode and the sixth power gate cell does not include a tap, and wherein the sixth power gate cell is connected to the fourth power gate cell. The power gate switching system according to item 25 of the patent application scope, wherein the first power gate cell, the third power gate cell and the fifth power gate cell are arranged in the first row, and The second power gate cell, the fourth power gate cell and the sixth power gate cell are arranged in the second row. The power gate switching system according to item 26 of the patent application range, wherein the first column to the third column extend in the first direction, and the first row and the second row are substantially vertical Extending in a second direction of the first direction. The power gate switching system according to item 22 of the patent application range, wherein the width of the channel of the first power gate cell in the column direction is greater than the width of the channel of the second power gate cell in the column direction width. The power gate switching system according to item 22 of the patent application scope, wherein the size of the first power gate cell is larger than the size of the second power gate cell. The power gate switching system as described in item 25 of the patent application scope, in which The gate control signal line of the second power gate cell, the gate control signal line of the fourth power gate cell and the gate control signal line of the sixth power gate cell cross the first virtual The power line, the second virtual power line, and the third virtual power line extend. The power gate switching system of claim 22, wherein the first power gate cell extends across the first virtual power line.

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