KR102533244B1 - Power gate switching system - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes a virtual power line extending in a first direction, an N-well extending in the first direction, a first power gate cell disposed in the N-well, and disposed in the N-well. and a third power gate cell disposed in the N-well between the first and second power gate cells. The virtual power line and the N-well may be disposed in a row, the first and second power gate cells may be cells of a first type, and the third power gate cell may be cells of a first type. It may be a cell of a second type different from

Description

Power gate switching system {POWER GATE SWITCHING SYSTEM}

The present invention relates to a power gate switching system for supplying a virtual voltage to a standard cell.

A power supply voltage supplied from the outside of the semiconductor device to drive standard cells constituting the semiconductor device is generally supplied to the standard cells through a power gate switch. At this time, the voltage output from the power gate switch is also referred to as a virtual voltage. In order to stably drive a semiconductor device, sufficient virtual voltage must be supplied to each standard cell. In particular, a relatively large voltage drop occurs at a location relatively far from the power gate switch. That is, the virtual voltage is not sufficiently supplied to the standard cells disposed in such places, and as a result, the standard cells are not normally driven. Therefore, it is very important to design a power gate switch capable of improving area effectiveness as well as supplying sufficient virtual voltage to standard cells.

The technical idea of the present invention is to provide a power gate switching system capable of efficiently supplying a virtual voltage to a region with a large voltage drop in a layout of a semiconductor device.

The technical idea of the present invention provides a power gate switching system with improved area efficiency.

A semiconductor device according to an embodiment of the present invention includes a virtual power line extending in a first direction, an N-well extending in the first direction, a first power gate cell disposed in the N-well, and disposed in the N-well. and a third power gate cell disposed in the N-well between the first and second power gate cells. The virtual power line and the N-well may be disposed in a row, the first and second power gate cells may be cells of a first type, and the third power gate cell may be cells of a first type. It may be a cell of a second type different from

A power gate switching system according to an embodiment of the present invention includes a first virtual power line extending in a first direction, a first power gate cell connected to the first virtual power line, and a second power gate cell connected to the first virtual power line. A power gate cell, and a third power gate cell connected to the first virtual power line and disposed between the first and second power gate cells. Each of the first and second power gate cells may include at least one tap, and the third power gate cell may not include a tap. The first to third power gate cells and the first virtual power line may be arranged in a first row.

A power gate switching system according to an embodiment of the present invention includes a first row including a first virtual power line, first power gate cells, and second power gate cells, and second virtual power lines, third power gate cells, and a second row including a fourth power gate cell. The first power gate cell includes a second gate electrode disposed between first and second diffusion regions and at least one tab, the second power gate cell between third and fourth diffusion regions. The disposed second gate electrode may be included but may not include a tab. The third power gate cell includes a third gate electrode disposed between fifth and sixth diffusion regions and at least one tab, and the fourth power gate cell is between seventh and eighth diffusion regions. A fourth gate electrode may be disposed but may not include a tab. The fourth power gate cell may be connected to the second power gate cell.

According to an embodiment of the present invention, a power gate switching system capable of efficiently supplying a virtual voltage to a region in which a voltage drop is large in a layout of a semiconductor device may be provided.

According to an embodiment of the present invention, it is possible to provide a power gate switching system having improved area effectiveness.

1 is a plan view showing a power gate switching system according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line AA′ of FIG. 1 .
FIG. 3 is another cross-sectional view taken along line AA′ of FIG. 1 .
4 is a plan view showing a power gate switching system according to an embodiment of the present invention.
5 is a cross-sectional view taken along line AA′ of FIG. 4 .
6 is a plan view showing a power gate switching system according to an embodiment of the present invention.
7 is a cross-sectional view taken along line BB′ of FIG. 6 .
8 is a plan view showing a power gate switching system according to an embodiment of the present invention.
9 is a cross-sectional view taken along line BB′ of FIG. 8 .
10 is a plan view showing a power gate switching system according to an embodiment of the present invention.
FIG. 11 is a cross-sectional view along line BB′ of FIG. 10 .
12 is a plan view showing a power gate switching system according to an embodiment of the present invention.
FIG. 13 is a cross-sectional view taken along line BB′ of FIG. 12 .
14 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.
15 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.
16 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.
17A is a plan view showing a power gate switching system according to an embodiment of the present invention.
Fig. 17B is a sectional view taken along A-A' of Fig. 17A.
Fig. 17c is a sectional view taken along line BB' of Fig. 17a;
18A is a plan view showing a power gate switching system according to an embodiment of the present invention.
Fig. 18B is a sectional view taken along A-A' of Fig. 18A.
Fig. 18C is a sectional view taken along line BB' of Fig. 18A;
19 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.

In the following, embodiments of the present invention will be described clearly and in detail with reference to the accompanying drawings so that those skilled in the art (hereinafter, those skilled in the art) can easily practice the present invention. will be explained

1 is a plan view showing a power gate switching system 100 according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1 .

1 and 2, the power gate switching system 100 includes a P-type substrate (P-sub), an N-well formed on the P-type substrate, and a first diffusion region formed on the N-well ( 101), the second diffusion region 102, the third diffusion region 103, the fourth diffusion region 104, the fifth diffusion region 105, the sixth diffusion region 106, and the first diffusion region 101 and a first gate electrode G1 formed on the N well between the second diffusion region 102 and a second gate formed on the N well between the third diffusion region 103 and the fourth diffusion region 104. Electrode G2, a third gate electrode G3 formed on the N well between the fifth diffusion region 105 and the sixth diffusion region 106, and formed adjacent to the first diffusion region 101 in the N well a first P-tap (P-tab1), a second P-tap (P-tab2) formed adjacent to the second diffusion region 102 in the N well, and adjacent to the third diffusion region 103 in the N well. and a fourth P-tap P-tab4 formed adjacent to the fourth diffusion region 104 in the N well.

An N well may be formed to extend along the first direction D1. For example, the N well may be a region doped with N-type impurities.

The first diffusion region 101 to the sixth diffusion region 106 may be formed along the first direction D1 in the N well. The first diffusion region 101 and the second diffusion region 102 may be spaced apart from each other so that the first gate electrode G1 may be disposed thereon. The third diffusion region 103 and the fourth diffusion region 104 may be spaced apart from each other so that the second gate electrode G2 may be disposed thereon. The fifth diffusion region 105 and the sixth diffusion region 106 may be formed between the second diffusion region 102 and the third diffusion region 103 . Also, the fifth diffusion region 105 and the sixth diffusion region 106 may be spaced apart from each other so that the third gate electrode G3 may be disposed thereon. For example, the first diffusion region 101 to the sixth diffusion region 106 may be doped with P-type impurities.

For example, the size of each of the fifth diffusion region 105 and the sixth diffusion region 106 may be smaller than that of each of the first diffusion region 101 to the fourth diffusion region 104 . The size (eg, thickness in the direction D1) of the third gate electrode G3 is the size (eg, thickness in the direction D1) of the first gate electrode G1 or the second gate electrode G2. ) can be smaller than

A power voltage V _DD may be supplied to the first diffusion region 101 . When a first channel (not shown) is formed between the first diffusion region 101 and the second diffusion region 102 according to the gate voltage Gate_CTRL applied to the first gate electrode G1, the first diffusion The power supply voltage (V _DD ) applied to the region 101 may be output in the form of a virtual power voltage (Virtual_V _DD ) through the first channel (not shown) and the second diffusion region 102 . The virtual power supply voltage (Virtual_V _DD ) may be provided to a standard cell (not shown) for constituting a logic circuit.

A power supply voltage (V _DD ) may be supplied to the third diffusion region 103 . When a second channel (not shown) is formed between the third diffusion region 103 and the fourth diffusion region 104 according to the gate voltage Gate_CTRL applied to the second gate electrode G2, the fourth diffusion region The power voltage V _DD applied to the region 104 may be output in the form of a virtual power voltage Virtual_V _DD through a second channel (not shown) and the fourth diffusion region 104 . The virtual power supply voltage (Virtual_V _DD ) may be provided to a standard cell (not shown) for constituting a logic circuit.

The power voltage V _DD may also be supplied to the fifth diffusion region 105 . When a third channel (not shown) is formed between the fifth diffusion region 105 and the sixth diffusion region 106 according to the gate voltage Gate_CTRL applied to the third gate electrode G3, the fifth diffusion region The power voltage V _DD applied to the region 105 may be output in the form of a virtual power voltage Virtual_V _DD through a third channel (not shown) and the sixth diffusion region 106 . The virtual power supply voltage (Virtual_V _DD ) may be provided to a standard cell (not shown) for constituting a logic circuit.

Although not shown in the drawing, an insulating film may be formed between the first gate electrode G1 and the N well, between the second gate electrode G2 and the N well, and between the third gate electrode G3 and the N well. .

The first P-tap P-tab1 and the second P-tab P-tab2 may be formed adjacent to the first diffusion region 101 and the second diffusion region 102 , respectively. The third P-tap P-tab3 and the fourth P-tab P-tab4 may be formed adjacent to the third diffusion region 103 and the fourth diffusion region 104 , respectively. For example, the first P-tap P-tab1 to the fourth P-tab P-tab4 may be regions doped with N-type impurities. For example, the doping concentration of the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be different from that of the N well. The first P-tap P-tab1 to the fourth P-tab P-tab4 may be disposed to extend in the second direction D2. And, although the drawing shows that the first P-tap (P-tab1) does not directly contact the first diffusion region 101, the first P-tap (P-tab1) is the first diffusion region 101. It can be formed directly adjacent. The same applies to the second P-tap (P-tab2) to the fourth P-tap (P-tab4).

A bias voltage Vbias may be applied to the first P-tap P-tab1 to the fourth P-tab P-tab4 . The bias voltage Vbias may prevent a latch-up phenomenon that may occur in the power gate switching system 100 . Although the figure shows that a separate bias voltage (Vbias) is applied to the first P-tap (P-tab1) to the fourth P-tap (P-tab4), the first P-tap (P-tab1) Instead of the bias voltage Vbias, the power supply voltage V _DD may be applied to the through fourth P-tap P-tab4 .

A distance between the second P-tap (P-tab2) and the third P-tab (P-tab3) may be determined according to the doping concentration of the N well. That is, the distance between the second P-tap P-tab2 and the third P-tab P-tab3 may be an appropriate distance to prevent a latch-up phenomenon from occurring in the power gate switching system 100 . For example, the distance between these tabs may be about 50 μm in a 10 nm process, but is not limited thereto. If the distance between the second P-tap (P-tab2) and the third P-tap (P-tab3) exceeds a threshold distance (eg, a distance capable of preventing latch-up), the fifth diffusion An additional P-tab (not shown) may be provided near region 105 or sixth diffusion region 106 . Meanwhile, even if the distance between the second P-tap (P-tab2) and the third P-tap (P-tab3) is such that a latch-up does not occur, the second diffusion region 102 and the third diffusion region 102 A power supply voltage (V _DD ) to be supplied to a standard cell (not shown) disposed at any point between (103) may be insufficient. Accordingly, the second diffusion region 102 and the third diffusion region are formed by providing the fifth diffusion region 105, the sixth diffusion region 106, and the third gate electrode G3 without providing an additional P-tab. The power supply voltage (V _DD ) can be stably supplied to a standard cell (not shown) to be disposed at any point between (103).

Continuing to refer to FIGS. 1 and 2 , the distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 is the first gate electrode G1 and the second gate electrode G1. It is shown to be 1/2 of the distance (eg, s2) between (G2). However, the distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 is the distance between the first gate electrode G1 and the second gate electrode G2 (eg, s1). , s2) may be 1/4 to 3/4. Of course, according to the arrangement of the third gate electrode G3, the fifth diffusion region 105 and the third channel (not shown) can be formed in the region where the third gate electrode G3 and the N well overlap. The sixth diffusion region 106 will have to be properly positioned.

It is shown that four P-taps are formed in the power gate switching system 100 shown in FIGS. 1 and 2 . However, it is not limited thereto, and as shown in FIG. 3 , the power gate switching system 100 may include two P-taps. The same reference numerals shown in FIG. 3 as those shown in FIGS. 1 and 2 may denote the same or similar elements. For example, as shown in FIG. 3 , a P-tap (P-tab1) may be provided adjacent to the first diffusion region 101, and a P-tap (P-tab4) may be provided adjacent to the fourth diffusion region ( 104) may be provided adjacent to. As another example, the P-tap P-tab1 may be provided adjacent to the first diffusion region 101, and the P-tap P-tab4 may be provided adjacent to the third diffusion region 103. there is. As another example, the P-tap P-tab2 may be provided adjacent to the second diffusion region 102 and the P-tap P-tab4 may be provided adjacent to the fourth diffusion region 104 . there is.

4 is a plan view showing a power gate switching system 100 according to an embodiment of the present invention. 5 is a cross-sectional view taken along the line A-A' of FIG. 4 .

The power gate switching system 100 may include shallow trench isolation (STI). The element isolation layers (STI) are standard cells (not shown) disposed in the space between the second P-tap (P-tab2) and the fifth diffusion region 105 or the sixth diffusion region 106 and the third P-tap. It may be provided to isolate a standard cell (not shown) to be disposed in the space between (P-tap3). Each device isolation layer STI may be disposed to extend in the second direction D2 adjacent to each P-tap. Although the device isolation layer STI is shown as being disposed without directly contacting the P-tap in the drawings, the device isolation layer STI may be disposed directly adjacent to the P-tap.

For example, device isolation layers (STI) may include a silicon oxide layer. For example, element isolation films (STIs) include high-density plasma (HDP) oxide film, TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O3-TEOS (O3-Tetra Ethyl Ortho Silicate), USG (Undoped Silicate Glass), PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG), or a combination thereof.

6 is a plan view showing a power gate switching system 200 according to an embodiment of the present invention. FIG. 7 is a cross-sectional view taken along line BB′ of FIG. 6 . Since the cross-sectional view taken along the line AA' of FIG. 6 is substantially the same as that of FIG. 2, the cross-sectional view taken along the line AA' of FIG. 6 will be omitted.

Referring to FIGS. 6 and 7 , the power gate switching system 200 may include a P-type substrate (P-sub) on which an N-well is formed.

The power gate switching system 200 includes a first diffusion region 201, a second diffusion region 202, a third diffusion region 203, a fourth diffusion region 204, and a fifth diffusion region ( 205) and a sixth diffusion region 206. The power gate switching system 200 includes a first gate electrode G1 formed on an N well between a first diffusion region 201 and a second diffusion region 202, a third diffusion region 203 and a fourth diffusion region 203. A second gate electrode G2 formed on the N well between the regions 204 and a third gate electrode G3 formed on the N well between the fifth diffusion region 205 and the sixth diffusion region 206. ) may be included.

For example, the distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 is the distance between the first gate electrode G1 and the second gate electrode G2 (eg, s1). For example, it may be 1/2 of s2). However, the distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 is the distance between the first gate electrode G1 and the second gate electrode G2 (eg, s1). , s2) may be 1/4 to 3/4. Of course, according to the arrangement of the third gate electrode G3, the fifth diffusion region 205 and the third channel (not shown) can be formed in the region where the third gate electrode G3 and the N well overlap. The sixth diffusion region 206 will have to be properly positioned.

For example, the first diffusion region 201 to the sixth diffusion region 206 may be doped with P-type impurities. A power voltage (V _DD in FIG. 2 ) may be supplied to the first diffusion region 201 , the third diffusion region 203 , and the fifth diffusion region 205 . According to the voltage (Gate_CTRL) applied to the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3, the first diffusion region 201, the third diffusion region 203, and The power supply voltage (V _DD ) applied to the fifth diffusion region 205 passes through the second diffusion region 202, the fourth diffusion region 204, and the sixth diffusion region 206, respectively, to obtain a virtual power supply voltage (Virtual_V _DD) . ) can be output in the form of

For example, the size of each of the fifth diffusion region 205 and the sixth diffusion region 206 may be smaller than that of each of the first diffusion region 201 to the fourth diffusion region 204 . The size (eg, thickness in the direction D1) of the third gate electrode G3 is the size (eg, thickness in the direction D1) of the first gate electrode G1 or the second gate electrode G2. ) can be smaller than

The power gate switching system 200 includes a first P-tap (P-tab1) to a fourth P-tab (P-tab4) formed along a first direction to extend in a second direction (D2) in an N well. can do. The first P-tap P-tab1 may be adjacent to the first diffusion region 201 . The second P-tap P-tab2 may be adjacent to the second diffusion region 202 . The third P-tap P-tab3 may be adjacent to the third diffusion region 203 . Also, the fourth P-tap P-tab4 may be adjacent to the fourth diffusion region 204 . Although P-taps are shown as not directly contacting the diffusion region in the drawing, P-taps may directly contact the diffusion region according to embodiments.

For example, the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be doped with an N-type impurity, and the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be doped with an N-type impurity. The doping concentration of the tab (P-tab4) may be different from that of the N well. A bias voltage (Vbias in FIG. 2 ) for preventing a latch-up phenomenon may be applied to the first P-tap P-tab1 to the fourth P-tab P-tab4 .

The power gate switching system 200 includes first N-tab N-tab1 to fourth N-tab N-tap formed along the first direction D1 to extend in the second direction D2 on the P-type substrate. tab4) may be further included. The first N-tab N-tab1 may be formed on the P-type substrate to extend in the second direction D2 along the column in which the first P-tab P-tab1 is disposed. The second N-tab N-tab2 may be formed on the P-type substrate to extend in the second direction D2 along a column in which the second P-tab P-tab2 is disposed. The third N-tab N-tab3 may be formed on the P-type substrate to extend in the second direction D2 along the column in which the third P-tab P-tab3 is disposed. Also, the fourth N-tab N-tab4 may be formed on the P-type substrate to extend in the second direction D2 along the column in which the fourth P-tab P-tab4 is disposed.

For example, the first N-tab (N-tab1) to the fourth N-tab (N-tab4) may be doped with a P-type impurity, and the first N-tab (N-tab1) to the fourth N-tab (N-tab4) may be doped with a P-type impurity. The doping concentration of the tab N-tab4 may be different from that of the P-type substrate. A bias voltage Vbias2 for preventing a latch-up phenomenon may be applied to the first N-tap N-tab1 to the fourth N-tab N-tab4 . For example, the bias voltage Vbias2 applied to the first N-tap N-tab1 to the fourth N-tap N-tab4 may be a ground voltage.

Illustratively, in FIG. 6, the first N-tap (N-tab1) to the fourth N-tap (N-tab4) are the first P-tap (P-tab1) to the fourth P-tab (P-tab4). is shown to be away from However, the first N-tab (N-tab1) to the fourth N-tab (N-tab4) and the first P-tab (P-tab1) to the fourth P-tab (P-tab4) are connected to the P-type substrate and They may be in contact with each other at the boundary of the N well.

The distance between the second P-tap (P-tab2) and the third P-tap (P-tab3) and the distance between the second N-tap (N-tab2) and the third N-tab (N-tab3) It may be determined according to the doping concentration of the N well or the doping concentration of the P-type substrate. For example, the distance between the second P-tap (P-tab2) and the third P-tab (P-tab3), and the second N-tap (N-tab2) and the third N-tap (N-tab3). ) may be a distance that prevents a latch-up phenomenon from occurring in the power gate switching system 200 .

Similarly, similarly to that described in FIG. 3 above, only the first P-tap (P-tab1) and the third P-tap (P-tab3) among the P-taps are provided, or one P-tap (P-tab1 ) and the fourth P-tab (P-tab4) may be provided. Furthermore, among the N-taps, only the first N-tap (N-tab1) and the third N-tap (N-tab3) are provided, or one N-tap (N-tab1) and the fourth N-tap (N-tab3) are provided. tab4) can be provided. Also, the power gate switching system 200 may further include a plurality of device isolation layers (refer to FIGS. 4 and 5 , STI).

Continuing to refer to FIG. 6 , the space between the second P-tap (P-tab2) and the third P-tab (P-tab3), and the second N-tap (N-tab2) and the third N-tab (P-tab2). A plurality of standard cells (STD Cells) may be disposed in the space between the tabs N-tab3. A virtual power voltage (Virtual_V _DD ) and a ground voltage (V _SS ) may be supplied to the plurality of standard cells (STD Cells). Among the plurality of standard cells (STD Cells), standard cells disposed close to the second diffusion region 202 and the fourth diffusion region 204 to which the virtual power voltage (Virtual_V _DD ) is output have a relatively sufficient virtual power voltage ( Virtual_V _DD ) will be supplied. On the other hand, the virtual power supply voltage (Virtual_V _DD ) supplied to the standard cell disposed in the middle between the second diffusion region 202 and the fourth diffusion region 204 from which the virtual power supply voltage (Virtual_V _DD ) is output may not be sufficient. there is. A fifth diffusion region 205 , a sixth diffusion region 206 , and a third gate electrode G3 are further provided for standard cells that are not sufficiently supplied with the virtual power supply voltage Virtual_V _DD . At this time, the virtual power supply voltage (Virtual_V _DD ) output through the sixth diffusion region 206 may be supplied to the surrounding standard cells, and thus, a voltage disposed between the second and fourth diffusion regions 202 and 204 Standard cells can be stably driven.

According to an embodiment of the present invention, in providing the fifth diffusion region 205, the sixth diffusion region 206, and the third gate electrode G3 for supplying an additional virtual power supply voltage (Virtual_V _DD ), additional It does not require P-taps. Accordingly, the virtual power voltage (Virtual_V _DD ) can be efficiently supplied to the standard cells without increasing the chip size.

8 is a plan view showing a power gate switching system 300 according to an embodiment of the present invention. 9 is a cross-sectional view taken along line BB′ of FIG. 8 . Since the cross-sectional view taken along the line AA' of FIG. 8 is substantially the same as that of FIG. 2, the cross-sectional view taken along the line AA' of FIG. 8 will be omitted.

Referring to FIGS. 8 and 9 , an N well extending in the first direction D1 may be formed on the P-type substrate. Also, a P-well may be formed adjacent to the N-well in the second direction D2 and extending in the first direction D1. Although the drawings show that the N well and the P well are separated from each other along the second direction D2, the N well and the P well may be in contact with each other along the second direction D2. Meanwhile, unlike the embodiment shown in FIG. 8 , the N well and the P well may be configured as pocket wells. For example, a P well may surround an N well. In more detail, a P-well may be formed on a P-type substrate, and an N-well may be formed within the P-well. However, it should be understood that such a pocket well can be exemplarily applied in this embodiment.

The first diffusion region 301 to the sixth diffusion region 306 formed in the N well, the first gate electrode G1 to the third gate electrode G3, and the first P-tab P-tab1 to the fourth Since the P-tap (P-tab4) is substantially the same as that previously described with reference to FIGS. 6 and 7 , duplicate descriptions will be omitted.

As shown in FIGS. 8 and 9 , first N-tab N-tab1 to fourth N-tap (which are formed along the first direction D1 so as to extend in the second direction D2 in the P-well) N-tab4) may be further formed. The first N-tab N-tab1 may extend in the second direction D2 along a column in which the first P-tab P-tab1 is disposed in the P well. The second N-tab N-tab2 may extend in the second direction D2 along the row in which the second P-tab P-tab2 is disposed in the P well. The third N-tab N-tab3 may extend in the second direction D2 along a column in which the third P-tab P-tab3 is disposed in the P well. Also, the fourth N-tab N-tab4 may extend in the second direction D2 along a column in which the fourth P-tab P-tab4 is disposed in the P well.

For example, the first N-tab (N-tab1) to the fourth N-tab (N-tab4) may be doped with a P-type impurity, and the first N-tab (N-tab1) to the fourth N-tab (N-tab4) may be doped with a P-type impurity. The doping concentration of the tab (N-tab4) may be different from that of the P well. A bias voltage Vbias2 for preventing a latch-up phenomenon may be applied to the first N-tap N-tab1 to the fourth N-tab N-tab4 . For example, the bias voltage Vbias2 applied to the first N-tap N-tab1 to the fourth N-tap N-tab4 may be a ground voltage.

Illustratively, in FIG. 8, the first N-tap (N-tab1) to the fourth N-tap (N-tab4) are the first P-tap (P-tab1) to the fourth P-tab (P-tab4). is shown to be away from However, the N well and the P well may be in contact with each other, and the first N-tab (N-tab1) to the fourth N-tab (N-tab4) and the first P-tab (P-tab1) to the fourth The P-tab (P-tab4) may be in contact with each other at the boundary between the N-well and the P-well.

Similarly, the distance between the second P-tap (P-tab2) and the third P-tap (P-tab3), and the distance between the second N-tap (N-tab2) and the third N-tab (N-tab3). The distance of may be determined according to the doping concentration of the N well or the doping concentration of the P well. For example, the distance between the second P-tap (P-tab2) and the third P-tab (P-tab3), and the second N-tap (N-tab2) and the third N-tap (N-tab3). ) may be a distance that prevents a latch-up phenomenon from occurring in the power gate switching system 300 .

Similarly, similarly to that described in FIG. 3 above, only the first P-tap (P-tab1) and the third P-tap (P-tab3) among the P-taps are provided, or one P-tap (P-tab1 ) and the fourth P-tab (P-tab4) may be provided. Furthermore, among the N-taps, only the first N-tap (N-tab1) and the third N-tap (N-tab3) are provided, or one N-tap (N-tab1) and the fourth N-tap (N-tab3) are provided. tab4) can be provided. Also, the power gate switching system 300 may further include a plurality of device isolation layers (refer to FIGS. 4 and 5 , STI).

10 is a plan view showing a power gate switching system 400 according to an embodiment of the present invention. FIG. 11 is a cross-sectional view taken along line BB' of FIG. 10 . Since the cross-sectional view along the line AA' of FIG. 10 is substantially the same as that of FIG. 2, the cross-sectional view along the line AA' of FIG. 10 will be omitted.

The power gate switching system 400 will be described in detail with reference to FIGS. 10 and 11 . The power gate switching system 400 includes an N well formed to extend in a first direction D1, a first diffusion region 401 to a sixth diffusion region 406 formed in the N well, and a first gate electrode G1. to the third gate electrode G3, and the first P-tap P-tab1 to the fourth P-tab P-tab4. The first diffusion region 401 to the sixth diffusion region 406 may be doped with a P-type powder, and the first P-tap (P-tab1) to the fourth P-tap (P-tab4) are N-type. It can be doped with impurities. For example, the doping concentration of the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be different from that of the N well.

A distance between the first gate electrode G1 and the second gate electrode G2 may be set in consideration of the doping concentration of the N well. That is, the first gate electrode G1 and the second gate electrode G2 may be separated by a distance that prevents latch-up from occurring in the power gate switching system 400 . The distance s1 between the first gate electrode G1 and the third gate electrode G3 is 1/4 to 3 the distance s2 between the first gate electrode G1 and the second gate electrode G2. It could be /4.

Since these components formed in the N well are substantially the same as those previously described with reference to FIGS. 1, 2, and 6, a detailed description thereof will be omitted.

The power gate switching system 400 may include a seventh diffusion region 407 to a twelfth diffusion region 412 extending in the second direction D2 and formed along the first direction D1 on the P-type substrate. there is. The seventh diffusion region 407 may be formed along a column in which the first diffusion region 401 is formed. For example, the seventh diffusion region 407 may be doped with N-type impurities. Similarly, the eighth diffusion region 408 to the twelfth diffusion region 412 may be formed along the columns in which the second diffusion region 402 to the sixth diffusion region 406 are formed.

A fourth gate electrode G4 may be formed on the P-type substrate between the seventh diffusion region 407 and the eighth diffusion region 408 . A fifth gate electrode G5 may be formed on the P-type substrate between the ninth diffusion region 409 and the tenth diffusion region 410 . A sixth gate electrode G6 may be formed on the P-type substrate between the 11th diffusion region 411 and the 12th diffusion region 412 . Although not shown in the drawing, insulating films are formed between the fourth gate electrode G4 and the P-type substrate, between the fifth gate electrode G5 and the P-type substrate, and between the sixth gate electrode G6 and the P-type substrate. can be provided. For example, the seventh diffusion region 407 to the twelfth diffusion region 412 may be doped with an N-type powder.

A first N-tab (N-tab1) and a second N-tab (N-tab2) may be formed adjacent to the seventh diffusion region 407 and the eighth diffusion region 408, respectively, on the P-type substrate. Although the figure shows that the first N-tap (N-tab1) and the second N-tap (N-tab2) are not in direct contact with the seventh diffusion region 407 and the eighth diffusion region 408, respectively, , the first N-tap (N-tab1) and the second N-tap (N-tab2) may directly contact the seventh diffusion region 407 and the eighth diffusion region 408, respectively. The first N-tab N-tab1 to the fourth N-tab N-tab4 may be doped with P-type impurities. For example, the doping concentration of the first N-tab (N-tab1) to the fourth N-tab (N-tab4) may be different from that of the P-type substrate.

A ground voltage V _SS may be applied to the seventh diffusion region 407 . According to the voltage Gate_CTRL input to the fourth gate electrode G4 , the ground voltage V _SS may be output in the form of a virtual ground voltage Virtual_V _SS through the eighth diffusion region 408 . The virtual ground voltage (Virtual_V _SS ) may be supplied to a nearby standard cell (not shown). And, the ground voltage (V _SS ) may also be supplied to a nearby standard cell (not shown).

In order to prevent a latch-up from occurring in the power gate switching system 400, a bias voltage Vbias2 may be applied to the first N-tap N-tab1 and the second N-tab N-tab2. there is. Although it is shown in the figure that separate bias voltages Vbias2 are applied to the first N-tap N-tab1 and the second N-tab N-tab2, The ground voltage V _SS may be applied to the second N-tap N-tab2 .

A third N-tab (N-tab3) and a fourth N-tab (N-tab4) may be formed adjacent to the ninth diffusion region 409 and the tenth diffusion region 410, respectively, on the P-type substrate. Although the drawing shows that the third N-tap (N-tab3) and the fourth N-tap (N-tab4) do not directly contact the ninth diffusion region 409 and the tenth diffusion region 410, respectively, , the third N-tap N-tab3 and the fourth N-tab N-tab4 may be formed to directly contact the ninth diffusion region 409 and the tenth diffusion region 410, respectively.

A ground voltage V _SS may be applied to the ninth diffusion region 409 . According to the voltage Gate_CTRL input to the fifth gate electrode G5 , the ground voltage V _SS may be output in the form of a virtual ground voltage Virtual_V _SS through the tenth diffusion region 410 . The virtual ground voltage (Virtual_V _SS ) may be supplied to a nearby standard cell (not shown). And, the ground voltage (V _SS ) may also be supplied to a nearby standard cell (not shown).

A bias voltage Vbias2 may be applied to the third N-tap N-tab3 and the fourth N-tap N-tab4 . Although the figure shows that a separate bias voltage Vbias2 is applied to the third N-tap (N-tab3) and the fourth N-tab (N-tab4), the third N-tap (N-tab3) and The ground voltage V _SS may be applied to the fourth N-tap N-tab4 .

Standard cells arranged relatively adjacent to the eighth diffusion region 408 or the tenth diffusion region 410 from which the virtual ground voltage (Virtual_V _SS ) is output can be relatively sufficiently supplied with the virtual ground voltage (Virtual_V _SS ). . On the other hand, standard cells disposed in the middle of the eighth diffusion region 408 and the tenth diffusion region 410 from which the virtual ground voltage Virtual_V _SS is output may not be sufficiently supplied with the virtual ground voltage Virtual_V _SS . can An 11th diffusion region 411, a 12th diffusion region 412, and a 6th gate electrode G6 are further provided for standard cells not receiving such a sufficient supply of the virtual ground voltage (Virtual_V _SS ).

For example, the size (eg, width in the D1 direction) of the 11th diffusion region 411 and the 12th diffusion region 412 is the size of the 7th diffusion region 407 to the 10th diffusion region 410. (eg, the width in the D1 direction). Also, the size of the sixth gate electrode G6 (eg, the width in the D1 direction) is also the size of the fourth gate electrode G4 or the fifth gate electrode G5 (eg, the width in the D1 direction). ) can be smaller than

According to an embodiment of the present invention, the fifth and sixth diffusion regions 405 and 406 and the third gate electrode G3, and the eleventh and twelfth diffusion regions 411 and 412 and the sixth gate electrode G6 are formed. By providing virtual power to a standard cell deployed in an area that is not sufficiently supplied with a virtual power supply voltage (Virtual_V _DD ) or a virtual ground voltage (Virtual_V _SS ) (eg, any point between 402 and 404 or 408 and 410) A voltage (Virtual_V _DD ) or a virtual ground voltage (Virtual_V _SS ) can be stably supplied. In addition, the chip size can be reduced by additionally providing relatively small-sized components without an additional P-tap or N-tap.

12 is a plan view showing a power gate switching system 500 according to an embodiment of the present invention. FIG. 13 is a cross-sectional view taken along line BB' of FIG. 12 . Since the cross-sectional view along the line AA' of FIG. 12 is substantially the same as that of FIG. 2, the cross-sectional view along the line AA' of FIG. 12 will be omitted.

The power gate switching system 500 will be described in detail with reference to FIGS. 12 and 13 . In the power gate switching system 500, an N well is formed on the surface along a first direction D1, and a P well is formed on the surface along the first direction D1 adjacent to the N well in a second direction D2. It may include a P-type substrate on which a well is formed. Meanwhile, the N well and the P well may be configured as pocket wells. For example, the P-well may be formed to surround the N-well.

The power gate switching system 500 includes a seventh diffusion region 507 to twelfth diffusion regions 512 and a first N-tap (N-tab1) to a fourth N-tap (N-tab4) formed in a P-well. ), and a fourth gate electrode G4 to a sixth gate electrode G6 formed in the P well. Other than that, power gate switching system 500 is similar to that shown in FIGS. 10 and 11 . For example, the power gate switching system 500 includes a first diffusion region 501 to sixth diffusion regions 506 and a first P-tap (P-tab1) to a fourth P-tap formed in an N well. (P-tab4), and the first gate electrode G1 to the third gate electrode G3 formed in the N well. Therefore, detailed description will be omitted.

For example, the distance s1 between the first gate electrode G1 and the third gate electrode G3 is 1/1 of the distance s2 between the first gate electrode G1 and the second gate electrode G2. It may be 4 to 3/4, and the distance s1 between the fourth gate electrode G4 and the sixth gate electrode G6 is the distance between the fourth gate electrode G4 and the fifth gate electrode G5 ( It may be 1/4 to 3/4 of s2). And, the size (eg, width in the D1 direction) of the diffusion regions 505, 506, 511, and 512 is the size (eg, the width in the D1 direction) of the diffusion regions 501 to 504 or 507 to 510. width) may be smaller than The size of the gate electrodes G3 and G6 (eg, the width in the D1 direction) may be smaller than the size (eg, the width in the D1 direction) of the gate electrodes G1, G2, G4 and G5. there is.

14 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention. For simplicity of description, an element isolation layer (refer to FIG. 4 , STI) is not shown.

Referring to FIG. 14 , a plurality of N-wells extending in a first direction D1 are formed along a second direction D2 on a P-type substrate. Specifically, N wells are formed along the first row (Row1), the third row (Row3), and the fifth row (Row5). And, as shown in the drawing, virtual power lines (Virtual_V _DD ) crossing the N wells along the first direction D1 are disposed, and the ground line crossing the P-type substrate along the first direction D1 ( V _SS ) were placed. A distance between the virtual power line Virtual_V _DD and the ground line V _SS in the second direction D2 may be referred to as 1H (1height).

Various standard cells (not shown) will be disposed on the P-type substrate and the N-well to form a semiconductor logic circuit, and a power gate switch system for supplying virtual power (Virtual_V _DD ) to the standard cells (not shown) is disposed. It will be. First, according to the layout design tool, power gate cells and P-tabs adjacent to the power gate cells may be uniformly arranged.

For example, the first cells 601 may be formed in N wells of the first row Row1. The first cell 601 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions formed in the first cell may be doped with P-type impurities. Also, two P-tabs may be formed adjacent to the first cell 601 . As shown in FIG. 14 , two P-tabs may or may not directly contact the first cell 601 . Although two P-taps are shown in the drawing, one P-tap may be formed as described above. For example, the P-tap may be doped with an N-type impurity, and the doping concentration of the P-tap may be different from that of the N-well.

The second cell 602 may be spaced apart from the first cell 601 by s3 and formed in the N well of the first row Row1. Like the first cell 601, the second cell 602 may include at least one gate electrode and at least two diffusion regions. The distance (eg, s3) between the first cell 601 and the second cell 602 may be set in consideration of the doping concentration of the N well. That is, the first cell 601 and the second cell 602 may be spaced apart by a distance that prevents a latch-up phenomenon from occurring. Since the second cell 602 and the first cell 601 are substantially identical to each other except for their positions, detailed descriptions thereof will be omitted.

A third cell 603 may be formed in the N well of the third row Row3. As shown in FIG. 14 , the third cell 603 may be positioned in the middle of the first cell 601 and the second cell 602 . Since the third cell 603 and the first cell 601 are substantially identical to each other except for their positions, detailed descriptions thereof will be omitted.

The fourth cell 604 and the fifth cell 605 may be formed in N wells of the fifth row Row5. Since the fourth cell 604 and the fifth cell 605 and the first cell 601 are substantially identical to each other except for their positions, detailed descriptions thereof will be omitted.

Even if the first cells 601 to the fifth cells 605 are uniformly arranged as shown in FIG. 14, the standard cells (not shown) disposed in a specific area between the cells have a virtual power supply voltage (Virtual_V). _DD ) may not be sufficiently supplied. That is, the voltage drop in a specific region between each cell may be so great that the standard cell cannot operate normally. First to third additional cells 611 to 613 may be disposed for a standard cell disposed in an area having a large voltage drop. The additional cells 611 to 613 shown in the drawing are exemplary, and do not mean that the voltage drop in that area is actually large.

A first additional cell 611 may be formed in the N well of the first row Row1. The first additional cell 611 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions formed in the first additional cell 611 may be doped with P-type impurities. However, unlike the first cell 601 to the fifth cell 605, the first additional cell 611 is not provided with a P-tap. Also, the size of the first additional cell 611 may be smaller than at least one of the first cell 601 to the fifth cell 605 . That is, the size (eg, width in the D1 direction) of the gate electrode of the first additional cell 611 may be the same as or smaller than that of the first cell 601 to the fifth cell 605 . Also, the size of the diffusion region of the first additional cell 611 (eg, the width in the D1 direction) may be the same as or smaller than that of the first cell 601 to the fifth cell 605 . And, the distance s1 between the first cell 601 and the first additional cell 611 is 1/4 to 3/4 of the distance s3 between the first cell 601 and the second cell 602 can be

The second additional cells 612 may be formed in the N wells of the third row Row3 and the fifth row Row5. The second additional cell 612 may include at least one gate electrode and at least four diffusion regions. That is, the diffusion regions formed in the third row Row3 and the diffusion regions formed in the fifth row Row5 may share a gate electrode. At least four diffusion regions formed in the second additional cell 612 may be doped with P-type impurities. Similarly, unlike the first cell 601 to the fifth cell 605, the second additional cell 612 is not provided with a P-tap. Also, the size of the second additional cell 612 may be equal to or smaller than at least one of the first cell 601 to the fifth cell 605 . That is, the size (eg, width in the D1 direction) of the gate electrode of the second additional cell 612 may be the same as or smaller than that of the first cell 601 to the fifth cell 605 . Also, the size of the diffusion region of the second additional cell 612 (eg, the width in the D1 direction) may be the same as or smaller than that of the first cell 601 to the fifth cell 605 . Although the drawing shows that the second additional cell 612 has a length of 3H in the second direction D2, it is not limited thereto.

A third additional cell 613 may be formed in the N well of the third row Row3. The third additional cell 613 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions of the third additional cell 613 and at least two diffusion regions of the second cell 602 may share a gate electrode. Alternatively, at least two diffusion regions of the third additional cell 613 and at least two diffusion regions of the fifth cell 605 may share a gate electrode.

At least two diffusion regions formed in the third additional cell 613 may be doped with P-type impurities. However, unlike the first cell 601 to the fifth cell 605, the third additional cell 611 is not provided with a P-tap. Also, the size of the third additional cell 613 may be equal to or smaller than at least one of the first cell 601 to the fifth cell 605 . That is, the size (eg, width in the D1 direction) of the gate electrode of the third additional cell 613 may be the same as or smaller than that of the first cell 601 to the fifth cell 605 . Also, the size of the diffusion region of the third additional cell 613 (that is, the width in the D1 direction) may be the same as or smaller than that of the first cell 601 to the fifth cell 605 .

By arranging the plurality of cells 601 to 605 and the additional cells 611 to 613 according to the embodiment described in FIG. 14, a virtual power supply voltage (Virtual_V _DD ) sufficient for standard cells disposed in an area where a relatively large voltage drop occurs ) can be supplied. In addition, since the plurality of additional cells 611 to 613 have a relatively smaller size than the plurality of cells 601 to 605, there are advantages in terms of reducing the chip size and disposing of standard cells.

15 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention. For simplicity of description, an element isolation layer (refer to FIG. 4 , STI) is not shown. And, the layout of the semiconductor device shown in FIG. 15 is similar to that of the semiconductor device shown in FIG. 14 except that a plurality of N-taps are provided. For example, the first to fifth cells 701 to 705 may be similar to the first to fifth cells 601 to 605 of FIG. 14, and the additional cells 711 to 713 may be the additional cells ( 611 to 613) may be similar.

A plurality of N-taps may be formed on the P-type substrate. For example, the N-tap may be disposed to extend in the second direction D2 and may be adjacent to the P-tap. Although P-tap and N-tap are shown as being spaced apart from each other in the drawing, the P-tap and N-tap may be in contact with each other at the boundary between the N-well and the P-type substrate. For example, the plurality of N-tabs may be doped with P-type impurities, and the doping concentration of the N-taps may be different from that of the P-type substrate. Also, a P-well doped with P-type impurities may be formed in the P-type substrate. In this case, N-taps may be formed in the P-well.

16 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention. For simplicity of description, an element isolation layer (refer to FIG. 4 , STI) is not shown.

In the layout of the semiconductor device shown in this drawing, components formed in the N well are substantially the same as those described in FIGS. 14 and 15, and therefore, duplicate descriptions will be omitted. Also, N-taps formed on the P-type substrate (or P-well formed on the P-type substrate) are similar to those previously described with reference to FIG. 15 . For example, the first to fifth cells 801 to 805 may be similar to the first to fifth cells 601 to 605 of FIG. 14, and the additional cells 811 to 813 may be the additional cells ( 611 to 613) may be similar.

Continuing to refer to FIG. 16 , sixth cells 821 to tenth cells 825 may be formed on a P-type substrate. Each of the sixth cell 821 to tenth cells 825 may include at least one gate electrode and at least two diffusion regions. As shown in FIG. 16 , each of the sixth cell 821 to the tenth cells 825 may be formed between two N-taps.

Since the first additional cell 811 is substantially the same as the first additional cell 711 previously described with reference to FIG. 15 , duplicate descriptions will be omitted.

The second additional cells 812 may be formed to extend in the second direction D2 across the second row Row2 to the fourth row Row4 . Illustratively, the second additional cell 812 is shown as having 2H. The second cell 812 includes at least two diffusion regions formed in the P-type substrate of the second row Row2, at least two diffusion regions formed in the N-well of the third row Row3, and the third row (Row3). Row 3) may include at least two diffusion regions formed on the P-type substrate, and at least one gate electrode. That is, these diffusion regions may share at least one gate electrode with each other. However, when two or more gate electrodes are provided, these diffusion regions may not share the gate electrode. For example, diffusion regions formed in the N well may be doped with P-type impurities, and diffusion regions formed in the P-type substrate may be doped with N-type impurities.

The third additional cells 813 may extend in the second direction D2 across the second row Row2 to the fourth row Row4. Illustratively, the second additional cell 812 is shown as having 2H. The second cell 812 includes at least two diffusion regions formed in the P-type substrate of the second row Row2, at least two diffusion regions formed in the N-well of the third row Row3, and the third row (Row3). Row 3) may include at least two diffusion regions formed on the P-type substrate, and at least one gate electrode.

For example, diffusion regions formed in the second row Row2 among elements of the third additional cell 813 may share a gate electrode with diffusion regions of the cell 822 . Also, among the components of the third additional cell 813 , the diffusion regions formed in the fourth row Row4 may share a gate electrode with the diffusion regions of the cell 825 . That is, at least some or all of the diffusion regions of the third additional cell 813 may share a gate electrode with the cells 822 and/or 825 .

17A is a plan view showing a power gate switching system according to an embodiment of the present invention. FIG. 17A is similar to FIG. 10 . Therefore, the differences between these embodiments will be mainly described.

For example, power gate switching system 1100 may include a top row, a middle row, and a bottom row.

The top row is placed between the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _DD ), and the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _DD , the first power gate cells P-tab1, 1101, G1, 1102, and P-tab2, the second power gate cells 1105, G3, and 1106, and the third power gate cell P-tab3 , 1103, G2, 1104, P-tab4). That is, the upper row shows PMOS power gate cells connected between the virtual power supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _SS ). The upper row is placed between the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _SS ), and the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, A plurality of standard cells (Std1, Std2) connected to Virtual_V _SS may be further included. A plurality of standard cells Std1 and Std2 may be disposed between the PMOS power gate cells of the upper row. Each of the plurality of standard cells Std1 and Std2 may include a PMOS transistor on the N-well and an NMOS transistor on the substrate P-sub. The N-well of each PMOS transistor of the plurality of standard cells Std1 and Std2 may be merged with the N-well of the PMOS power gate cells in the upper row shown in FIG. 17A. Since one of the plurality of standard cells (Std1, Std2) disposed between the PMOS power gate cells in the upper row includes an NMOS transistor on the substrate (P-sub), the combined N-well where the PMOS power gate cells are disposed The shape of may be different from the shape of the N-well shown in FIG. 10 .

The lower row is placed between the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, Virtual_V _DD ), and the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, The fourth power gate cells N-tab1, 1107, G4, 1108, and N-tab2, the sixth power gate cells 1111, G6, and 1112, and the fifth power gate cell N-tab3 connected to Virtual_V _DD . , 1109, G5, 1110, N-tab4). That is, the lower row shows NMOS power gate cells connected between the virtual ground voltage (Virtual_V _SS ) and the power supply voltage (V _DD ) (or virtual power supply voltage, Virtual_V _DD ). The lower row is placed between the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, Virtual_V _DD ), and the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, A plurality of standard cells (Std5, Std6) connected to Virtual_V _DD may be further included. A plurality of standard cells Std5 and Std6 may be disposed between NMOS power gate cells in a lower row. Each of the plurality of standard cells Std5 and Std6 may include a PMOS transistor on the N-well and an NMOS transistor on the substrate P-sub. Accordingly, the N-wells of the PMOS transistors of the standard cells Std5 and Std6 disposed between the NMOS power gate cells in the lower row may be disposed on the substrate P-sub in the lower row. The N-well of each PMOS transistor of the plurality of standard cells Std5 and Std6 may be combined with the N-well of the plurality of standard cells Std3 and Std4 of the middle row shown in FIG. 17A .

The middle row is the voltage between the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ), the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ), or the virtual supply voltage (Virtual_V _DD ) and the virtual ground voltage (Virtual_V _SS ). It may include standard cells (Std3, Std4) connected to.

The power gate switching system 1100 may further include a plurality of middle rows connected between the virtual ground voltage (Virtual_V _SS ) and the virtual power supply voltage (Virtual_V _DD ). One of the plurality of middle rows may be connected to a virtual ground voltage (Virtual_V _SS ) or a ground voltage (V _SS ) connected to the NMOS power gate cell. The rest of the middle rows may be connected to a virtual power supply voltage (Virtual_V _DD ) or a power supply voltage (V _DD ) connected to the PMOS power gate cell. And, power gate cells can be shown using their gate electrodes. Here, one of the first to sixth power gate cells extends into at least one of the middle rows to apply a virtual power supply voltage (Virtual_V _DD ) or a virtual ground voltage (Virtual_V _SS ) node to a plurality of standard cells in at least one of the middle rows. can provide

Fig. 17B is a sectional view taken along A-A' of Fig. 17A. Components of FIG. 17B may correspond to components of FIG. 12 . Therefore, the differences between the two embodiments will be mainly described. For example, FIG. 17B shows discontinuous N-wells extending in the D1 direction on the substrate (P-sub). That is, a break was shown in the N-well. NMOS transistors of the standard cells may be disposed between the first to third power gate cells on the substrate P-sub.

Fig. 17c is a sectional view taken along BB' of Fig. 17a; Components of FIG. 17C may correspond to components of FIG. 11 . Therefore, the differences between the two embodiments will be mainly described. For example, FIG. 17C shows NMOS power gate cells coupled to ground voltage (V _SS ) and virtual ground voltage (Virtual_V _SS ). The N-well for the PMOS transistor of the standard cell may be disposed between the fourth to sixth power gate cells on the substrate P-sub. For example, the N-well may be disposed between the fifth power gate cell and the sixth power gate cell.

18A is a plan view showing a power gate switching system according to an embodiment of the present invention. Figure 18A is similar to Figure 12. Therefore, differences between the two embodiments will be mainly described. In some embodiments, unlike those shown in the drawings, P-wells may be formed to surround N-wells. As a result, pocket wells may be formed.

For example, power gate switching system 1200 may include a top row, a middle row, and a bottom row.

The top row is placed between the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _DD ), and the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _DD ), the first power gate cells P-tab1, 1201, G1, 1202, and P-tab2, the second power gate cells 1205, G3, and 1206, and the third power gate cell P-tab3 , 1203, G2, 1204, P-tab4). That is, the upper row shows PMOS power gate cells connected between the virtual power supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _SS ). The upper row is placed between the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, Virtual_V _SS ), and the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ) (or virtual ground voltage, A plurality of standard cells (Std1, Std2) connected to Virtual_V _SS may be further included. A plurality of standard cells Std1 and Std2 may be disposed between the PMOS power gate cells of the upper row. Each of the plurality of standard cells Std1 and Std2 may include an N-well PMOS transistor and a P-well NMOS transistor. The N-well of the PMOS transistor of each of the plurality of standard cells Std1 and Std2 may be combined with the N-well of the PMOS power gate cells in the upper row shown in FIG. 18A. Since one of the plurality of standard cells Std1 and Std2 disposed between the first to third PMOS power gate cells includes an NMOS transistor on the P-well, the combined N-well where the PMOS power gate cells are disposed The shape may be different from the shape of the N-well shown in FIG. 12 .

The lower row is placed between the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, Virtual_V _DD ), and the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, The fourth power gate cell (N-tab1, 1207, G4, 1208, and N-tab2), the sixth power gate cell (1211, G6, and 1212), and the fifth power gate cell (N-tab3) are connected to Virtual_V _DD . , 1209, G5, 1210, N-tab4). That is, the lower row shows NMOS power gate cells connected between the virtual ground voltage (Virtual_V _SS ) and the power supply voltage (V _DD ) (or virtual power supply voltage, Virtual_V _DD ). The lower row is placed between the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, Virtual_V _DD ), and the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ) (or virtual supply voltage, A plurality of standard cells (Std5, Std6) connected to Virtual_V _DD may be further included. The plurality of standard cells Std5 and Std6 may be arranged between the fourth to sixth NMOS power gate cells in the lower row. Each of the plurality of standard cells Std5 and Std6 may include a PMOS transistor on the N-well and an NMOS transistor on the substrate P-sub. Accordingly, the N-well of the PMOS transistor of the standard cells Std5 and Std6 disposed between the NMOS power gate cells in the lower row may be disposed in the P-well of the lower row. As shown in FIG. 18A , the N-well of each PMOS transistor of the plurality of standard cells Std5 and Std6 in the lower row may be merged with the N-well of the plurality of standard cells Std3 and Std4 in the middle row.

The middle row is the voltage between the virtual ground voltage (Virtual_V _SS ) and the supply voltage (V _DD ), the virtual supply voltage (Virtual_V _DD ) and the ground voltage (V _SS ), or the virtual supply voltage (Virtual_V _DD ) and the virtual ground voltage (Virtual_V _SS ). It may include standard cells (Std3, Std4) connected to. The power gate switching system 1200 may further include a plurality of middle rows connected between the virtual ground voltage (Virtual_V _SS ) and the virtual power supply voltage (Virtual_V _DD ). One of the plurality of middle rows may be connected to a virtual ground voltage (Virtual_V _SS ) or a ground voltage (V _SS ) connected to the NMOS power gate cell. The rest of the middle rows may be connected to a virtual power supply voltage (Virtual_V _DD ) or a power supply voltage (V _DD ) connected to the PMOS power gate cell. And, power gate cells can be shown using their gate electrodes. Here, one of the first to sixth power gate cells extends into at least one of the middle rows to apply a virtual power supply voltage (Virtual_V _DD ) or a virtual ground voltage (Virtual_V _SS ) node to a plurality of standard cells in at least one of the middle rows. can provide

Fig. 18B is a sectional view taken along A-A' of Fig. 18A. Components of FIG. 18B may correspond to components of FIG. 12 . Therefore, the differences between the two embodiments will be mainly described. For example, FIG. 18B shows discontinuous N-wells for the first to third PMOS power gate cells along the D1 direction and one of standard cells disposed between the discontinuous N-wells on the substrate P-sub. Shows a P-well for an NMOS transistor. Among the standard cells, MMOS transistors may be formed on the P-well.

Fig. 18C is a sectional view taken along BB' of Fig. 18A; Components of FIG. 18C may correspond to components of FIG. 13 . Therefore, the differences between the two embodiments will be mainly described. For example, FIG. 18C shows discontinuous P-wells for the fourth to sixth NMOS power gate cells along the D1 direction and one of standard cells disposed between the discontinuous P-wells on the substrate P-sub. Shows an N-well for a PMOS transistor. Among the standard cells, a PMOS transistor may be formed on an N-well.

19 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.

In particular, FIG. 19 shows a plurality of PMOS power gate cells connected to a plurality of metal power lines (Virtual V _DD and V _SS (or Virtual V _SS )). Each of the PMOS power gate cells may have at least one of P-tab and N-tab on both sides thereof. In FIG. 19, the PMOS tap is shown as "PT", the NMOS tap is shown as "NT", the diffusion break region is shown as "DB", and the standard cells are shown as "Std Cells". 19 shows metal power lines (V _SS or Virtual V _SS ) extending in the longitudinal direction along upper and lower portions of a row of PMOS power gate cells. In addition, one of the metal power lines Virtual V _DD and V _SS (or Virtual V _SS ) may extend longitudinally through the center of each row of PMOS power gate cells. The distance W_pg2pg may be a required minimum distance between power gate cells.

For example, a P-well may exist in the standard cell region where the first region (Region I) is located. Also, there may be an N-well in the second region (Region II) adjacent to the first region. The metal power line (Virtual V _DD ) may cross the second region. Also, a line disposed between the NMOS taps NT may be a power line NVSS connecting the NMOS taps NT to each other.

Referring to FIG. 19 , the semiconductor device 1300 may include a plurality of types of power gate cells. For example, a PMOS power gate cell of the first type may include P-taps (PTs) on both sides of a PMOS power gate transistor in the PMOS power gate cell. A PMOS power gate cell of the first type may include N-taps (NT) on both sides of the PMOS power gate cell. PMOS power gate cells may include one or more PMOS transistors coupled between metal power lines (Virtual V _DD and Virtual V _SS (or V _SS )). A PMOS power gate cell of the second type may not have P-taps (PTs) or N-taps (NTs) on both sides of the PMOS power gate cell, and metal power lines (Virtual V _DD and Virtual V _SS (or V _SS )) may include one or more PMOS transistors coupled thereto. The number of PMOS transistors may be proportional to the current drive capability of the PMOS power gate cell.

PMOS power gate cells of the first type may be aligned along a vertical region including a plurality of virtual power supply lines (Virtual V _DD ), and PMOS power gate cells of the second type may be arranged along a plurality of virtual power supply lines (Virtual V _DD ). It can be aligned along a vertical region containing. The location or number of PMOS power gate cells shown in the plan view of the semiconductor device 1300 may vary depending on the power provided by the PMOS power gate cells.

What has been described above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced in the future using the above-described embodiments.

101, 102, 103, 104, 105, 106: diffusion area

Claims (10)

a virtual power line extending in a first direction;
an N-well extending in the first direction, wherein the virtual power line and the N-well are disposed in a row;
a first power gate cell disposed in the N-well;
a second power gate cell disposed in the N-well, wherein the first and second power gate cells are cells of a first type; and
a third power gate cell disposed in the N-well between the first and second power gate cells, wherein the third power gate cell is a cell of a second type different from cells of the first type; Device. According to claim 1,
the third power gate cell is disposed closer to the first power gate cell than the second power gate cell; or
The third power gate cell is disposed closer to the second power gate cell than the first power gate cell. According to claim 1,
The semiconductor device of claim 1 , wherein each of the cells of the first type includes a gate electrode disposed between a pair of diffusion regions and a tab adjacent to one of the diffusion regions. According to claim 3,
wherein the tap is a P-tap, and in a row adjacent to the row of the N-well, an N-tap is disposed on the same axis as the P-tap, and the N-tap is connected to a ground line. According to claim 3,
The semiconductor device of claim 1 , wherein the cell of the second type includes a gate electrode disposed between a pair of diffusion regions, and the cell of the second type does not include a tab. a first virtual power line extending in a first direction;
a first power gate cell connected to the first virtual power line;
a second power gate cell coupled to the first virtual power line, each of the first and second power gate cells including at least one tap; and
a third power gate cell connected to the first virtual power supply line and disposed between the first and second power gate cells, wherein the third power gate cell does not include a tap;
The power gate switching system of claim 1 , wherein the first to third power gate cells and the first virtual power line are arranged in a first row. According to claim 6,
a second virtual power line extending in the first direction;
a fourth power gate cell connected to the second virtual power line; and
A fifth power gate cell connected to the second virtual power line, wherein the fourth and fifth power gate cells further include at least one tap;
The fourth and fifth power gate cells and the second virtual power line are arranged in a second row. According to claim 6,
The first row above is:
an N-well region disposed on first and second side surfaces of the first virtual power line;
a first ground line disposed on the first side of the first virtual power line; and
and a second ground line disposed on the second side of the first virtual power line. a first row including first virtual power lines, first power gate cells, and second power gate cells; and
a second row comprising a second virtual power supply line, a third power gate cell, and a fourth power gate cell;
The first power gate cell includes a second gate electrode disposed between first and second diffusion regions and at least one tab, the second power gate cell between third and fourth diffusion regions. Including a second gate electrode disposed but not including a tab,
The third power gate cell includes a third gate electrode disposed between fifth and sixth diffusion regions and at least one tab, and the fourth power gate cell is between seventh and eighth diffusion regions. A fourth gate electrode disposed but not including a tab,
The fourth power gate cell is connected to the second power gate cell. According to claim 9,
a third row comprising a third virtual power line, a fifth power gate cell, and a sixth power gate cell;
The fifth power gate cell includes a fifth gate electrode disposed between ninth and tenth diffusion regions and at least one tab, and the sixth power gate cell is disposed between eleventh and twelfth diffusion regions. A sixth gate electrode disposed but not including a tab,
The sixth power gate cell is connected to the fourth power gate cell.

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