KR20170026077A - Power gate switching system - Google Patents

Abstract

A power gate switching system of the present invention includes a first gate electrode formed on the well of a substrate, a second gate electrode, and a third gate electrode disposed between the first gate electrode and the second gate electrode. A first diffusion region and a second diffusion region are formed in the wells on both sides of a first gate, a third diffusion region and a fourth diffusion region are formed in the wells on both sides of a second gate, and a fifth diffusion region and a sixth diffusion region are formed in the wells on both sides of a third gate. A first P-tab is formed in the well adjacent to the first diffusion region, a second P-tab is formed in the well adjacent to the fourth diffusion region. A power voltage is supplied to the first diffusion region, the third diffusion region, and the fifth diffusion region, and a virtual voltage is output through the second diffusion region, the fourth diffusion region, and the sixth diffusion region according to the gate voltage applied to the first to third gate electrodes.

Description

[0001] POWER GATE SWITCHING SYSTEM [0002]

The present invention relates to a power gate switching system for supplying a virtual voltage to a standard cell.

The power supply voltage supplied from the outside for driving the standard cells constituting the semiconductor device is generally supplied to the standard cell through the power gate switch. At this time, the voltage output from the power gate switch may be referred to as a virtual voltage. In order to stably drive the semiconductor device, a sufficient virtual voltage must be supplied to each of the standard cells. In particular, the voltage drop is relatively large at a relatively far distance from the power gate switch. That is, a virtual voltage is not sufficiently supplied to the standard cell disposed at such a place, and as a result, the standard cell is not normally driven. Therefore, it is very important to design power gate switches that not only provide sufficient virtual voltages for standard cells, but also improve area effectiveness.

The technical idea of the present invention provides a power gate switching system capable of efficiently supplying a virtual voltage to a region where a voltage drop is large in a layout of a semiconductor device.

The technical idea of the present invention provides a power gate switching system with improved area efficiency.

A power gate switching system according to an embodiment of the present invention is a substrate doped with a first type wherein a well is formed in the substrate extending in a first direction and doped with a second type, And a first diffusion region and a second diffusion region formed in the wells on both sides of the first gate electrode, the first diffusion region being supplied with a power supply voltage Wherein the second diffusion region includes a second gate electrode that extends in the second direction on the well, a second gate electrode that extends in the second direction on both sides of the second gate electrode, A third diffusion region and a fourth diffusion region formed in the well, wherein the third diffusion region is supplied with the power source voltage and the fourth diffusion region is provided with the second gate electrode A third gate electrode disposed between the first gate electrode and the second gate electrode and extending in the second direction on the well, a second gate electrode disposed on both sides of the third gate electrode, Wherein the fifth diffusion region is supplied with the power supply voltage and the sixth diffusion region is supplied with the virtual voltage < RTI ID = 0.0 > A first P-tap formed in the well adjacent to the first diffusion region and extending in the second direction, the first P-tap being supplied with a first bias voltage, and a second P- And a second P-tap formed in the well to extend in two directions and being supplied with the first bias voltage, wherein the first diffusion region to the sixth diffusion region And the first P-taps and the second P-taps may be doped with the second type.

For example, the distance between the first P-tap and the second P-tap may be set according to the doping concentration of the well.

For example, the power gate switching system may further include a plurality of element isolation films adjacent to each of the first P-tap to the fourth P-tap.

For example, the distance between the first gate electrode and the third gate electrode in the first direction may be 1/4 to 3/4 of the distance between the first gate electrode and the second gate electrode.

For example, the power gate switching system may include a third P-tap formed in the well adjacent to the second diffusion region, and a fourth P-tap formed in the well adjacent to the third diffusion region .

For example, the doping concentration of the first P-tap to the fourth P-tap and the doping concentration of the N-well may be different from each other.

For example, the level of the first bias voltage may be equal to the level of the power supply voltage.

For example, the power gate switching system may include a first N-tap receiving a second bias voltage, the first N-tap being formed in the substrate adjacent to the first P-tap in the second direction and extending in the second direction, And a second N-tap formed on the substrate adjacent to the second P-tap in the second direction and extending in the second direction, the second N-tap being supplied with the second bias voltage.

For example, the first N-taps and the second N-taps are doped with the first type, and the doping concentration of the substrate and the doping densities of the first N- can be different.

For example, the second bias voltage may be a ground voltage.

For example, the power gate switching system may include a fourth gate electrode adjacent to the first gate electrode in the second direction and extending in the second direction on the substrate, a fourth gate electrode extending in the second direction on both sides of the fourth gate electrode, Wherein the seventh diffusion region is supplied with the power source voltage and the eighth diffusion region is supplied with the virtual voltage according to a gate voltage applied to the fourth gate electrode as a seventh diffusion region and an eighth diffusion region formed in the well, A fifth gate electrode adjacent to the second gate electrode in the second direction and extending in the second direction on the substrate, a ninth diffusion region formed in the well on both sides of the fifth gate electrode, And a tenth diffusion region, wherein the ninth diffusion region is supplied with the power source voltage and the tenth diffusion region is subjected to a gate voltage applied to the fifth gate electrode A sixth gate electrode that is adjacent to the third gate electrode in the second direction and that extends in the second direction on the substrate, and a second gate electrode that is formed on the wells on both sides of the sixth gate electrode Wherein the tenth diffusion region is supplied with the power supply voltage and the twelfth diffusion region is configured to output the virtual voltage according to a gate voltage applied to the sixth gate electrode as an eleventh diffusion region and a twelfth diffusion region, .

A power gate switching system according to an embodiment of the present invention is a substrate doped with a first type, wherein a plurality of wells doped with a second type are formed in the substrate, the plurality of wells extending in a first direction, A first cell formed in a first well of the plurality of wells, the first cell comprising a first gate electrode, a first cell formed on a first side of the first gate electrode, And a second cell formed in the second well adjacent to the first well in the second direction, wherein the second cell includes a first gate electrode and a second gate electrode, A third diffusion region formed in the second well on both sides of the second gate electrode and a fourth diffusion region, the second cell being spaced apart from the first cell in the first direction, Between the cell and the second cell An additional cell formed in the first well, the additional cell including a first additional diffusion region and a second additional diffusion region formed in the first well on both sides of the additional gate electrode and the additional gate electrode; At least one first P-tab formed in the first well adjacent to the first cell, and at least one second P-tab formed in the second well adjacent to the second cell.

For example, the first diffusion region to the fourth diffusion region, the first additional diffusion region, and the second additional diffusion region are doped with the first type, and the first P-tap and the second P- The taps may be doped with the second type.

For example, a power supply voltage is supplied to the first diffusion region, the third diffusion region, and the first additional diffusion region, and the first gate electrode, the second gate electrode, and the additional gate electrode are supplied with a gate voltage And a virtual voltage may be output to the second diffusion region, the fourth diffusion region, and the second additional diffusion region according to the application of the gate voltage.

For example, a bias voltage may be applied to the first P-tap and the second P-tap.

For example, the level of the bias voltage may be equal to the level of the power supply voltage.

For example, the power gate switching system may include at least one first N-tap formed adjacent to the at least one first P-tap on a substrate between the first well and the second well, Tap and at least one second N-tap formed adjacent to the at least one second P-tab on a substrate between the first well and the second well, wherein the first N- The taps may be doped with the first type.

For example, a ground voltage may be applied to the first N-tap and the second N-tap.

For example, the power gate switching system may be a third cell formed adjacent to the first cell and the at least one first N-tap on a substrate between the first well and the second well, 3 cell includes a third gate electrode, a fifth diffusion region and a sixth diffusion region formed on the substrate on both sides of the third gate electrode, and a second diffusion region formed on the substrate between the first well and the second well, And a fourth cell formed adjacent to the at least one second N-tap, wherein the fourth cell comprises a fourth gate electrode, a seventh diffusion region formed on the substrate on both sides of the fourth gate electrode, And a diffusion region.

For example, the fifth to eighth diffusion regions may be doped with the second type.

According to the embodiment of the present invention, it is possible to provide a power gate switching system capable of efficiently supplying a virtual voltage to a region where a voltage drop is large in a layout of a semiconductor device.

According to embodiments of the present invention, it is possible to provide a power gate switching system with improved area effectiveness.

1 is a plan view showing a power gate switching system according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line AA 'in FIG.
3 is another cross-sectional view along the line AA 'in Fig.
4 is a plan view showing a power gate switching system according to an embodiment of the present invention.
5 is a cross-sectional view taken along line AA 'of FIG.
6 is a plan view showing a power gate switching system according to an embodiment of the present invention.
7 is a cross-sectional view taken along line BB 'of Fig.
8 is a plan view showing a power gate switching system 300 according to an embodiment of the present invention.
9 is a cross-sectional view taken along the line BB 'in Fig.
10 is a plan view showing a power gate switching system according to an embodiment of the present invention.
11 is a cross-sectional view taken along line BB 'of Fig.
12 is a plan view showing a power gate switching system according to an embodiment of the present invention.
13 is a sectional view taken along the line BB 'in Fig.
14 is a plan view showing a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.
15 is a plan view showing a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.
16 is a plan view showing a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

When an element or layer is referred to as being "connected ", or" adjacent "to another element or layer, it is to be understood that other elements or layers may be directly connected, Mean, or may be indirectly connected, joined, or contiguous, with another element or layer in between. As used herein, the term "and / or" will include one or more possible combinations of the listed elements.

Although the terms "first "," second "and the like can be used herein to describe various elements, these elements are not limited by these terms. These terms may only be used to distinguish one element from the other. Accordingly, terms such as first element, section, and layer used in this specification may be used as a second element, section, layer, etc. without departing from the spirit of the present invention.

The terminology described herein is used for the purpose of describing a specific embodiment only, and is not limited thereto. Terms such as "one" should be understood to include plural forms unless explicitly referred to as " one ". The terms "comprising" or "comprising" are used to specify the presence of stated features, steps, operations, components, and / or components and may include additional features, steps, operations, components, And / or does not exclude the presence of their group.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical idea of the present invention.

1 is a plan view showing a power gate switching system 100 according to an embodiment of the present invention. 2 is a cross-sectional view taken along line A-A 'in Fig.

1 and 2, the power gate switching system 100 includes a P-type substrate (P-sub), an N-well formed in the P-type substrate, a first diffusion region The first diffusion region 101, the second diffusion region 102, the third diffusion region 103, the fourth diffusion region 104, the fifth diffusion region 105, the sixth diffusion region 106, Formed on the N well between the third diffusion region 103 and the fourth diffusion region 104. The first gate electrode G1 formed on the N well between the second diffusion region 102 and the second diffusion region 102, A third gate electrode G3 formed on the N well between the fifth diffusion region 105 and the sixth diffusion region 106, a third gate electrode G3 formed on the N well adjacent to the first diffusion region 101, A second P-tab (P-tab2) formed adjacent to the second diffusion region 102 in the N well, a second P-tab (P-tab2) formed adjacent to the third diffusion region 103 in the N well, (P-tab 3) formed adjacent to the fourth diffusion region 104 in the N-well, and a third P-tab P- tab4).

The N well may be formed to extend along the first direction D1. For example, the N-well may be a region doped with an N-type impurity.

The first diffusion region 101 to the sixth diffusion region 106 may be formed in the N well along the first direction D1. The first diffusion region 101 and the second diffusion region 102 may be spaced apart so that the first gate electrode G1 may be disposed thereon. The third diffusion region 103 and the fourth diffusion region 104 may be spaced apart so that the second gate electrode G2 may be disposed thereon. A fifth diffusion region 105 and a sixth diffusion region 106 may be formed between the second diffusion region 102 and the third diffusion region 103. The fifth diffusion region 105 and the sixth diffusion region 106 may be spaced apart from each other so that the third gate electrode G3 may be disposed thereon. For example, the first diffusion region 101 to the sixth diffusion region 106 may be a region doped with a P-type impurity.

For example, the sizes of the fifth diffusion region 105 and the sixth diffusion region 106 may be smaller than the sizes of the first diffusion region 101 to the fourth diffusion region 104, respectively. The size (for example, the thickness in the direction D1) of the third gate electrode G3 is set to be equal to the size (for example, the thickness in the direction D1) of the first gate electrode G1 or the second gate electrode G2 ).

The power source voltage V _DD may be supplied to the first diffusion region 101. [ When a first channel (not shown) is formed between the first diffusion region 101 and the second diffusion region 102 according to the gate voltage Gate_CTRL applied to the first gate electrode G1, the power supply voltage (V _DD) is applied to the area 101 may be output in the form of the virtual voltage (Virtual_V _DD) through a first channel (not shown) and a second diffusion region (102). The virtual voltage (Virtual_V _DD ) may be provided in a standard cell (not shown) for constituting a logic circuit.

The power supply voltage V _DD may be supplied to the third diffusion region 103. When a second channel (not shown) is formed between the third diffusion region 103 and the fourth diffusion region 104 according to the gate voltage Gate_CTRL applied to the second gate electrode G2, the power supply voltage (V _DD) is applied to the area 104 may be output in the form of the virtual voltage (Virtual_V _DD) via a second channel (not shown) and the fourth diffusion region 104. The virtual voltage (Virtual_V _DD ) may be provided in a standard cell (not shown) for constituting a logic circuit.

The power source voltage V _DD may be supplied to the fifth diffusion region 105 as well. When a third channel (not shown) is formed between the fifth diffusion region 105 and the sixth diffusion region 106 according to the gate voltage Gate_CTRL applied to the third gate electrode G3, region with the power supply voltage (V _DD) is applied to 105 may be output in the form of the virtual voltage (Virtual_V _DD) via a third channel (not shown), and a sixth diffusion region 106. The virtual voltage (Virtual_V _DD ) may be provided in a standard cell (not shown) for constituting a logic circuit.

Although not shown in the drawing, an insulating film may be formed between the first gate electrode G1 and the N well, between the second gate electrode G2 and the N well, and between the third gate electrode G3 and the N well .

The first P-tab (P-tab1) and the second P-tab (P-tab2) may be formed adjacent to the first diffusion region 101 and the second diffusion region 102, respectively. The third P-tab (P-tab3) and the fourth P-tab (P-tab4) may be formed adjacent to the third diffusion region 103 and the fourth diffusion region 104, respectively. For example, the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be regions doped with N-type impurities. For example, the doping concentrations of the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be different from the doping concentration of the N well. The first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be arranged to extend in the second direction (D2). Although the first P-tab P-tab1 is shown as not directly contacting the first diffusion region 101, the first P-tab P- They may be formed directly adjacent to each other. The same applies to the second P-tab (P-tab2) to the fourth P-tab (P-tab4).

In order to prevent a latch-up phenomenon that may occur in the power gate switching system 100, bias voltages Vbias (Vbias) and Vbias are applied to the first to fourth P-tabs ) May be applied. Although a separate bias voltage Vbias is shown to be applied to the first P-tab P-tab1 through the fourth P-tab P-tab4 in the figure, the first P-tab P- The power supply voltage V _DD may be applied to the fourth P-tab (P-tab4).

The distance between the second P-tab (P-tab2) and the third P-tab (P-tab3) can be determined according to the doping concentration of the N well. That is, the distance between the second P-tab (P-tab2) and the third P-tab (P-tab3) may be a distance such that latch-up phenomenon does not occur in the power gate switching system 100. If the distance between the second P-tab (P-tab2) and the third P-tab (P-tab3) exceeds the allowable distance to avoid latch-up, 6 P-tab (not shown) near the diffusion region 106 may be provided. On the other hand, although the distance between the second P-tab (P-tab2) and the third P-tab (P-tab3) does not cause latch-up, The power supply voltage V _{DD to} be supplied to the standard cell (not shown) to be disposed at any point between the power supply voltage V _{DD and the} power supply voltage V _DD may be insufficient. Thus, by providing the fifth diffusion region 105, the sixth diffusion region 106, and the third gate electrode G3, without providing additional P-tabs, the second diffusion region 102 and the third diffusion region 102 The power supply voltage V _DD can be stably supplied to a standard cell (not shown) to be disposed at any point between the power supply voltage V _DD .

1 and 2, the distance (i.e., s1) between the first gate electrode G1 and the third gate electrode G3 is larger than the distance between the first gate electrode G1 and the second gate electrode G2 (I.e., s2) between the first and second electrodes. However, the distance between the first gate electrode G1 and the third gate electrode G3 (i.e., s1) is smaller than the distance between the first gate electrode G1 and the second gate electrode G2 (i.e., s2) 1/4 to 3/4. Of course, according to the arrangement of the third gate electrode G3, the fifth diffusion region 105 and the fifth diffusion region 105 may be formed so that a third channel (not shown) may be formed in the region where the third gate electrode G3 and the N well overlap. The sixth diffusion region 106 should be appropriately disposed.

It is shown that four P-taps are formed in the power gate switching system 100 shown in FIGS. 1 and 2. However, it is not so limited, and as shown in FIG. 3, the power gate switching system 100 may include two P-taps. Illustratively, in FIG. 3, one P-tap is shown disposed adjacent to the first diffusion region 101 and the fourth diffusion region 104, respectively. However, according to the embodiment, one P-tap may be disposed adjacent to each of the first diffusion region 101 and the third diffusion region 103, and the second diffusion region 102 and the fourth diffusion region 104 may be arranged in one P-tap.

4 is a top plan view of a power gate switching system 100 in accordance with an embodiment of the present invention. 5 is a cross-sectional view taken along the line A-A 'in FIG.

The power gate switching system 100 may include shallow trench isolation (STI). The device isolation films (STIs) may include a standard cell (not shown) or a sixth diffusion region 106 to be disposed in a space between the second P-tap (P-tap2) and the fifth diffusion region 105, (Not shown) to be disposed in a space between the P-tap 3 and the P-tap 3. Each device isolation film (STI) may be arranged to extend in the second direction (D2) adjacent to each P-tap. Although the device isolation film (STI) is shown as being disposed without directly contacting the P-tab, the device isolation film (STI) may be disposed directly adjacent to the P-tab.

For example, the device isolation films (STIs) may include a silicon oxide film. For example, the device isolation films (STIs) may be formed using a high density plasma (HDP) oxide film, TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O 3 -TeOS (O 3 -Tetra Ethyl Ortho Silicate) Phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin on glass (SOG) or a combination thereof.

6 is a plan view showing a power gate switching system 200 according to an embodiment of the present invention. 7 is a cross-sectional view taken along the line B-B 'in Fig. 6 is substantially the same as that of FIG. 2, so that a cross-sectional view taken along the line A-A 'of FIG. 6 is omitted.

Referring to FIGS. 6 and 7, the power gate switching system 200 may include a P-type substrate in which an N-well is formed.

The power gate switching system 200 includes a first diffusion region 201, a second diffusion region 202, a third diffusion region 203, a fourth diffusion region 204, a fifth diffusion region 205 and a sixth diffusion region 206. The power gate switching system 200 includes a first gate electrode G1 formed on an N-well between a first diffusion region 201 and a second diffusion region 202, a third diffusion region 203, A second gate electrode G2 formed on the N well between the fifth diffusion region 205 and the fourth diffusion region 206 and a third gate electrode G3 formed on the N well between the fifth diffusion region 205 and the sixth diffusion region 206 ).

For example, the distance between the first gate electrode G1 and the third gate electrode G3 (i.e., s1) is the distance between the first gate electrode G1 and the second gate electrode G2 (that is, s2 ). ≪ / RTI > However, the distance between the first gate electrode G1 and the third gate electrode G3 (i.e., s1) is smaller than the distance between the first gate electrode G1 and the second gate electrode G2 (i.e., s2) 1/4 to 3/4. Of course, the fifth diffusion region 205 and the fifth diffusion region 205 may be formed so that a third channel (not shown) may be formed in the region where the third gate electrode G3 and the N well overlap, The sixth diffusion region 206 should be appropriately disposed.

For example, the first diffusion region 201 to the sixth diffusion region 206 may be doped with a P-type impurity. The power source voltage (see FIG. 2, V _DD ) may be supplied to the first diffusion region 201, the third diffusion region 203, and the fifth diffusion region 205. The first diffusion region 201, the third diffusion region 203, and the third diffusion region 203 are formed in accordance with the voltage (Gate_CTRL) applied to the first gate electrode G1, the second gate electrode G2 and the third gate electrode G3, The power supply voltage V _DD applied to the fifth diffusion region 205 is set to a virtual voltage V DD_V _DD through the second diffusion region 202, the fourth diffusion region 204, and the sixth diffusion region 206, Can be output.

For example, the size of each of the fifth diffusion region 205 and the sixth diffusion region 206 may be smaller than the size of each of the first diffusion region 201 to the fourth diffusion region 204. The size (for example, the thickness in the direction D1) of the third gate electrode G3 is set to be equal to the size (for example, the thickness in the direction D1) of the first gate electrode G1 or the second gate electrode G2 ).

The power gate switching system 200 includes first P-tabs (P-tab1) to fourth P-tabs (P-tab4) formed along the first direction to extend in the second direction (D2) can do. The first P-tab (P-tab1) may be formed adjacent to the first diffusion region 201. [ The second P-tab (P-tab2) may be formed adjacent to the second diffusion region 202. [ The third P-tab (P-tab3) may be formed adjacent to the third diffusion region 203. [ And a fourth P-tab (P-tab4) may be formed adjacent to the fourth diffusion region 204. [ Although the figure shows that the P-tab does not directly touch the diffusion area, the P-tab can directly contact the diffusion area.

For example, the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be doped with N-type impurities, and the first P- The doping concentration of the tap (P-tab4) may be different from the doping concentration of the N-well. A bias voltage (see FIG. 2, Vbias) for preventing the latch-up phenomenon may be applied to the first P-tab (P-tab1) to the fourth P-tab (P-tab4).

The power gate switching system 200 includes a first N-tab N-tab1 through a fourth N-tab N-tab1 formed along the first direction D1 to extend in the second direction D2 to the P- tab4). The first N-tab1 may be formed on the P-type substrate to extend in the second direction D2 along the row in which the first P-tab (P-tab1) is disposed. The second N-tab2 may be formed on the P-type substrate to extend in the second direction D2 along the row where the second P-tab P-tab2 is disposed. The third N-tab 3 may be formed on the P-type substrate to extend in the second direction D2 along the row where the third P-tab P-tab 3 is disposed. The fourth N-tab 4 may be formed on the P-type substrate so as to extend in the second direction D2 along the row in which the fourth P-tab P-tab4 is disposed.

For example, the first N-tab1 through the fourth N-tab4 may be doped with a P-type impurity, and the first N- The doping concentration of the tab (N-tab4) may be different from the doping concentration of the P-type substrate. A bias voltage Vbias2 for preventing a latch-up phenomenon may be applied to the first N-tab1 through the fourth N-tab N4. For example, the bias voltage Vbias2 applied to the first N-tab1 to the fourth N-tab4 may be a ground voltage.

6 illustrates an example in which the first N-tab1 through the fourth N-tab4 are divided into a first P-tab 1 to a fourth P-tab 4, ≪ / RTI > However, the first N-tab1 to the fourth N-tab4 and the first P-tab P-tab1 to the fourth P-tab P- Lt; RTI ID = 0.0 > N-well. ≪ / RTI >

The distance between the second P-tab (P-tab2) and the third P-tab (P-tab3) and the distance between the second N- tab (N-tab2) and the third N- The doping concentration of the N-well or the doping concentration of the P-type substrate. For example, the distance between the second P-tab P-tab2 and the third P-tab P-tab3, and the distance between the second N-tab2 and the third N- May be a distance such that latch-up phenomenon does not occur in the power gate switching system 200. [

Likewise, similar to that described previously in Figures 3-5, only the first P-tab (P-tab1) and the third P-tab (P-tab3) of the P- P-tab1) and a fourth P-tab (P-tab4) may be provided. Similarly, only the first N-tab (N-tab1) and the third N-tab (N-tab3) of the N-tabs are provided, or only the first N- -tab4) may be provided. Further, the power gate switching system 200 may further include a plurality of element isolation films (see FIGS. 4 and 5, STIs).

6, a space between the second P-tab P-tab 2 and the third P-tab P-tab 3, and a space between the second N-tab 2 and the third N- A plurality of standard cells (STD cells) may be disposed in a space between the tabs (N-tab3). A virtual voltage (Virtual_V _DD ) and a ground voltage (V _SS ) can be supplied to a plurality of standard cells (STD cells). Among the plurality of standard cells (STD Cells), the standard cell arranged close to the second diffusion region 202 and the fourth diffusion region 204 from which the virtual voltage (Virtual_V _DD ) is outputted has a relatively sufficient virtual voltage (Virtual_V _DD ) Will be supplied. On the other hand, the virtual voltage (Virtual_V _DD) received standard cell is supplied is arranged in the middle between the second diffusion region 202 and the fourth diffusion region 204 to be output, the virtual voltage (Virtual_V _DD) may be insufficient. The fifth diffusion region 205, the sixth diffusion region 206, and the third gate electrode G3 are further provided for the standard cell which is not sufficiently supplied with the virtual voltage V _DD . The virtual voltage (Virtual_V _DD ) output through the sixth diffusion region 206 is sufficiently supplied to neighboring standard cells so that the standard cells can be stably driven.

According to an embodiment of the present invention, in providing a fifth diffusion region 205, a sixth diffusion region 206, and a third gate electrode G3 for supplying an additional virtual voltage (Virtual_V _DD ), an additional P - It does not need taps. Therefore, it is possible to efficiently supply the virtual voltage (Virtual_V _DD ) to the standard cells without increasing the chip size.

8 is a plan view showing a power gate switching system 300 according to an embodiment of the present invention. 9 is a cross-sectional view taken along the line B-B 'in Fig. A sectional view taken along the line A-A 'in FIG. 8 is substantially the same as that shown in FIG. 2, and thus a sectional view taken along the line A-A' in FIG. 8 is omitted.

8 and 9, an N well extending in a first direction D1 may be formed on a P-type substrate. P wells that are adjacent to the N well in the second direction D2 and extend in the first direction D1 may be formed. Although the figure shows that the N well and the P well are separated from each other along the second direction D2, the N well and the P well may be in contact with each other along the second direction D2.

The first to fifth diffusion regions 301 to 306, the first gate electrode G1 to the third gate electrode G3, the first P-tab (P-tab1) to the fourth The P-tab (P-tab4) is substantially the same as that described above with reference to FIG. 6 to FIG. 7, and thus a duplicated description will be omitted.

(N-tab1) to a fourth N-tab (N-tab4) formed along the first direction D1 so as to extend in the second direction D2 may be further formed in the P well. The first N-tab1 may be formed in the P-well to extend in the second direction D2 along the row in which the first P-tab P-tab1 is disposed. The second N-tab2 may be formed in the P-well so as to extend in the second direction D2 along the row in which the second P-tab P-tab2 is disposed. The third N-tab 3 may be formed in the P-well so as to extend in the second direction D2 along the row in which the third P-tab P-tab3 is disposed. The fourth N-tab 4 may be formed in the P-well so as to extend in the second direction D2 along the row in which the fourth P-tab P-tab4 is disposed.

For example, the first N-tab1 through the fourth N-tab4 may be doped with a P-type impurity, and the first N- The doping concentration of the N-tab (N-tab4) may be different from the doping concentration of the P-well. A bias voltage Vbias2 for preventing a latch-up phenomenon may be applied to the first N-tab1 through the fourth N-tab N4. For example, the bias voltage Vbias2 applied to the first N-tab1 to the fourth N-tab4 may be a ground voltage.

6 illustrates an example in which the first N-tab1 through the fourth N-tab4 are divided into a first P-tab 1 to a fourth P-tab 4, ≪ / RTI > However, the N-well and the P-well may be in contact with each other, and the first N-tabs N-tab1 through N-tab4 and the first P-tabs P- The P-tab (P-tab4) may be in contact with each other at the boundary between the N-well and the P-well.

Similarly, the distance between the second P-tab P-tab2 and the third P-tab P-tab3 and the distance between the second N- tap N-tab2 and the third N- May be determined according to the doping concentration of the N well or the doping concentration of the P well. For example, the distance between the second P-tab P-tab2 and the third P-tab P-tab3, and the distance between the second N-tab2 and the third N- May be a distance such that latch-up phenomenon does not occur in the power gate switching system 300. [

Likewise, similar to that described previously in Figures 3-5, only the first P-tab (P-tab1) and the third P-tab (P-tab3) of the P- P-tab1) and a fourth P-tab (P-tab4) may be provided. Similarly, only the first N-tab (N-tab1) and the third N-tab (N-tab3) of the N-tabs are provided, or only the first N- -tab4) may be provided. The power gate switching system 300 may further include a plurality of device isolation films (see FIGS. 4 and 5, STIs).

10 is a plan view showing a power gate switching system 400 according to an embodiment of the present invention. 11 is a cross-sectional view taken along the line B-B 'in FIG. 10 is substantially the same as that of FIG. 2, and therefore, a sectional view taken along the line A-A 'of FIG. 10 is omitted.

The power gate switching system 400 includes an N well formed to extend in the first direction D1, a first diffusion region 401 to a sixth diffusion region 406 formed in the N well, a first gate electrode G1, A third gate electrode G3, and a first P-tab P-tab1 through a fourth P-tab P-tab4. The first to sixth diffusion regions 401 to 406 may be doped with a P-type impurity, and the first to fourth P-tabs to P-tabs 4 may be doped with N-type Can be doped with impurities. For example, the doping concentrations of the first P-tab (P-tab1) to the fourth P-tab (P-tab4) may be different from the doping concentration of the N well.

The distance between the first gate electrode G1 and the second gate electrode G2 may be set in consideration of the doping concentration of the N well. That is, the first gate electrode G1 and the second gate electrode G2 may be spaced apart by a distance such that latch-up does not occur in the power gate switching system 400. The distance s1 between the first gate electrode G1 and the third gate electrode G3 is set to a distance s2 between 1/4 and 3 mm between the first gate electrode G1 and the second gate electrode G2 / 4.

Since these elements formed in the N well are substantially the same as those described with reference to FIGS. 1, 2, and 6, detailed description thereof will be omitted.

The power gate switching system 400 may include a seventh diffusion region 407 to a twelfth diffusion region 412 extending in the second direction D2 and along the first direction D1 to the P- have. The seventh diffusion region 407 may be formed along the row in which the first diffusion region 401 is formed. For example, the seventh diffusion region 407 may be doped with an N-type impurity. Likewise, the eighth diffusion region 408 to the twelfth diffusion region 412 may be formed along the rows in which the second diffusion region 402 to the sixth diffusion region 406 are formed, respectively.

A fourth gate electrode G4 may be formed on the P-type substrate between the seventh diffusion region 407 and the eighth diffusion region 408. [ A fifth gate electrode G5 may be formed on the P-type substrate between the ninth diffusion region 409 and the tenth diffusion region 410. [ A sixth gate electrode G6 may be formed on the P-type substrate between the eleventh diffusion region 411 and the twelfth diffusion region 412. [ Although not shown in the drawing, insulating films are formed between the fourth gate electrode G4 and the P-type substrate, between the fifth gate electrode G5 and the P-type substrate, and between the sixth gate electrode G6 and the P- Can be provided. For example, the seventh diffusion region 407 to the twelfth diffusion region 412 may be doped with an N-type impurity.

The first N-tab1 and the second N-tab2 may be formed on the P-type substrate adjacent to the seventh diffusion region 407 and the eighth diffusion region 408, respectively. Although the figure shows that the first N-tab1 and the second N-tab N-tab2 are not in direct contact with the seventh diffusion region 407 and the eighth diffusion region 408, respectively The first N-tab1 and the second N-tab2 may be formed to directly contact the seventh diffusion region 407 and the eighth diffusion region 408, respectively. The first N-tabs (N-tab1) to the fourth N-tabs (N-tab4) may be doped with P-type impurities. For example, the doping concentrations of the first N-tabs N-tabl to the fourth N-tabs may differ from the doping concentration of the P-type substrate.

The power source voltage V _DD may be applied to the seventh diffusion region 407. According to the voltage (Gate_CTRL) input to the fourth gate electrode (G4), a power supply voltage (V _DD) can be output in the form of the virtual voltage (Virtual_V _DD) through the eighth diffusion region 408. The virtual voltage (Virtual_V _DD ) can be supplied to a nearby standard cell (not shown). The ground voltage V _SS can also be supplied to a nearby standard cell (not shown).

To prevent latch-up from occurring in the power gate switching system 400, a bias voltage Vbias2 may be applied to the first N-tab1 and the second N-tab N-tab2 have. Although a separate bias voltage Vbias2 is applied to the first N-tab1 and the second N-tab2, the first N-tab1 and the second N- And a ground voltage (V _SS ) may be applied to the second N-tab (N-tab2).

The third N-tab 3 and the fourth N-tab 4 may be formed on the P-type substrate adjacent to the ninth diffusion region 409 and the tenth diffusion region 410, respectively. Although the figure shows that the third N-tab 3 and the fourth N-tab 4 are not in direct contact with the ninth diffusion region 409 and the tenth diffusion region 410, respectively The third N-tab 3 and the fourth N-tab 4 may be formed to directly contact the ninth diffusion region 409 and the tenth diffusion region 410, respectively.

The power source voltage V _DD may be applied to the eighth diffusion region 408. Claim 5 according to the gate electrode (G5) a voltage (Gate_CTRL) input to the power supply voltage (V _DD) can be output in the form of the virtual voltage (Virtual_V _DD) via a second diffusion region 10 (410). The virtual voltage (Virtual_V _DD ) can be supplied to a nearby standard cell (not shown). The ground voltage V _SS can also be supplied to a nearby standard cell (not shown).

Similarly, a bias voltage Vbias2 may be applied to the third N-tab N3 and the fourth N-tab N4. Although a separate bias voltage Vbias2 is applied to the third N-tab3 and the fourth N-tab4, the third N-tab3 and the fourth N- And the fourth N-tab (N-tab4) may be applied with the ground voltage (V _SS ).

Virtual voltage (Virtual_V _DD) eighth diffusion region 408 or 10, the diffusion region 410 and the standard cell are arranged relatively adjacent the output will be able to be sufficiently supplied relative to a virtual voltage (Virtual_V _DD). On the other hand, the standard cells disposed midway between the eighth diffusion region 408 and the tenth diffusion region 410 where the virtual voltage (Virtual_V _DD ) is output may not be sufficiently supplied with the virtual voltage (Virtual_V _DD ) . An eleventh diffusion region 411, a twelfth diffusion region 412, and a sixth gate electrode G6 are further provided for a standard cell which is not sufficiently supplied with the virtual voltage V _DD .

For example, the sizes (for example, the width in the direction D1) of the eleventh diffusion region 411 and the twelfth diffusion region 412 are set to be equal to the sizes of the seventh diffusion region 407 to the tenth diffusion region 410 (For example, the width in the direction D1). The size (for example, the width in the direction D1) of the sixth gate electrode G6 is also set to be the same as the size of the fourth gate electrode G4 or the fifth gate electrode G5 (for example, ).

The fifth and sixth diffusion regions 405 and 406 and the third gate electrode G3 and the eleventh and twelfth diffusion regions 411 and 412 and the sixth gate electrode G6 are formed in accordance with an embodiment of the present invention. It is possible to stably supply the virtual voltage (Virtual_V _DD ) to the standard cell disposed in an area where the virtual voltage (Virtual_V _DD ) is not sufficiently supplied (for example, between 402 and 404 or at any point between 408 and 410) have. In addition, the efficiency of the chip size can be improved by additionally providing relatively small-sized components without additional P-tabs or N-tabs.

12 is a plan view showing a power gate switching system 500 according to an embodiment of the present invention. 13 is a cross-sectional view taken along line B-B 'in Fig. 12 is substantially the same as that of FIG. 2, and hence the sectional view taken along the line A-A 'of FIG. 12 is omitted.

The power gate switching system 500 shown in Figs. 12 and 13 has N wells formed on its surface along the first direction D1 and adjacent to the N wells in the second direction D2, Lt; RTI ID = 0.0 > P-well < / RTI >

The seventh diffusion region 507 to the twelfth diffusion region 512 and the first N-tab1 to the fourth N-tab4 are formed in the P well, The power gate switching system 500 is similar to that shown in FIGS. 10 and 11, except that electrodes G4 through sixth gate electrodes G6 are formed on the P wells. Therefore, detailed description thereof will be omitted.

Of course, the distance s1 between the first gate electrode G1 and the third gate electrode G3 is preferably 1/4 to 3/4 of the distance s2 between the first gate electrode G1 and the second gate electrode G2. And the distance s1 between the fourth gate electrode G4 and the sixth gate electrode G6 may be equal to or smaller than the distance s5 between the fourth gate electrode G4 and the fifth gate electrode G5. / 4 to 3/4. The size (for example, the width in the direction D1) of the diffusion regions 505, 506, 511 and 512 is equal to the size of the diffusion regions 501 to 504 or 507 to 510 Of the width of the first region. The size (for example, the width in the direction D1) of the gate electrodes G3 and G6 may be smaller than the size (for example, the width in the direction D1) of the gate electrodes G1, G2, G4 and G5 have.

14 is a plan view showing a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention. For the sake of simplicity of explanation, a device isolation film (see FIG. 2, STI) is not shown.

Referring to FIG. 14, a plurality of N wells extending in a first direction D1 are formed on a P-type substrate along a second direction D2. Specifically, the N wells were formed along the first row (Row1), the third row (Row3), and the fifth row (Row5). As shown in the drawing, virtual power lines (Virtual_V _DD ) that are disposed across N wells along a first direction D1 are arranged and are connected to a ground line V _SS ) were deployed. The distance between the virtual power supply line (Virtual_V _DD ) and the ground line (V _SS ) in the second direction (D2) is defined as 1H (1height).

Various standard cells (not shown) are arranged on the P-type substrate and the N-well in order to constitute the semiconductor logic circuit, and a power gate switch system for supplying the virtual power supply (Virtual_V _DD ) to the standard cells Will be. First, according to the layout design tool, P-tabs adjacent to power switching cells and power switching cells will be uniformly arranged.

More specifically, the first cell 601 may be formed in the N well of the first row Row1. The first cell 601 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions formed in the first cell may be regions doped with P-type impurities. Further, two P-tabs adjacent to the first cell 601 may be formed. Two P-tabs may be formed to directly contact the first cell 601 as shown in the drawing, or may be formed so as not to be in direct contact therewith. Although two P-tabs are shown in the drawing, one P-tab may be formed as described above. For example, the P-taps may be doped with an N-type impurity and the doping concentration of the P-taps may be different from the doping concentration of the N-well.

The second cell 602 may be formed in the N well of the first row Row1 by being spaced apart from the first cell 601 by s3. As with the first cell 601, the second cell 602 may include at least one gate electrode and at least two diffusion regions. The distance between the first cell 601 and the second cell 602 (i.e., s3) may be set in consideration of the doping concentration of the N-well. That is, the distance between the first cell 601 and the second cell 602 (i.e., s3) may be a distance that prevents the latch-up phenomenon from occurring. The second cell 602 and the first cell 601 are substantially the same as each other except for the position in which they are disposed, and a detailed description thereof will be omitted.

And a third cell 603 may be formed in the N well of the third row Row3. As shown in the figure, the third cell 603 may be located at an intermediate portion between the first cell 601 and the second cell 602. The third cell 603 and the first cell 601 are substantially identical to each other except for a position where the third cell 603 and the first cell 601 are disposed, and a detailed description thereof will be omitted.

The fourth cell 604 and the fifth cell 605 may be formed in the N well of the fifth row Row5. The fourth cell 604, the fifth cell 605, and the first cell 601 are substantially the same as each other except for a position where they are disposed, and thus a detailed description thereof will be omitted.

Even if the first cell 601 to the fifth cell 605 are arranged uniformly as shown in the figure, a virtual voltage (Virtual_V _DD ) is applied to a standard cell (not shown) disposed in a specific region between the cells, May not be sufficiently supplied. That is, the voltage drop in any particular area between each cell may be so large that the standard cell can not operate normally. Additional cells 611 to 613 may be disposed for a standard cell in which such a voltage drop is large. The additional cells 611 to 613 shown in the figure are illustrative and do not necessarily mean that the voltage drop in the region is actually large.

A first additional cell 611 may be formed in the N well of the first row Rowl. The first additional cell 611 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions formed in the first additional cell 611 may be regions doped with P-type impurities. However, unlike the first cell 601 to the fifth cell 605, the first additional cell 611 is not provided with a P-tap. The size of the first additional cell 611 may be smaller than at least one of the first cell 601 to the fifth cell 605. That is, the size of the gate electrode of the first additional cell 611 (that is, the width in the direction D1) may be the same as or smaller than that of the first cell 601 to the fifth cell 605. The size of the diffusion region of the first additional cell 611 (that is, the width in the direction D1) may be the same as or smaller than that of the first cell 601 to the fifth cell 605. The distance s1 between the first cell 601 and the first additional cell 611 is 1/4 to 3/4 of the distance s3 between the first cell 601 and the second cell 602. [ Lt; / RTI >

A second additional cell 612 may be formed in the N well of the third row Row3 and the fifth row Row5. The second additional cell 612 may include at least one gate electrode and at least four diffusion regions. That is, the diffusion regions formed in the third row (Row3) and the diffusion regions formed in the fifth row (Row5) may share the gate electrode. At least four diffusion regions formed in the second additional cell 612 may be regions doped with P-type impurities. Similarly, unlike the first cell 601 to the fifth cell 605, the second additional cell 612 is not provided with a P-tap. The size of the second additional cell 612 may be equal to or smaller than at least one of the first cell 601 to the fifth cell 605. That is, the size of the gate electrode of the second additional cell 612 (that is, the width in the direction D1) may be the same as or smaller than that of the first cell 601 to the fifth cell 605. The size of the diffusion region of the second additional cell 612 (that is, the width in the direction D1) may be equal to or smaller than that of the first cell 601 to the fifth cell 605. Although the second additional cell 612 is shown in the figure as having a length of 3H in the second direction D2, it is not limited thereto.

A third additional cell 613 may be formed in the N well of the third row Row3. The third additional cell 613 may include at least one gate electrode and at least two diffusion regions. At least two diffusion regions of the third additional cell 613 and at least two diffusion regions of the second cell 602 may share a gate electrode. Or at least two diffusion regions of the third additional cell 613 and at least two diffusion regions of the fifth cell 605 may share a gate electrode.

At least two diffusion regions formed in the third additional cell 613 may be regions doped with P-type impurities. However, unlike the first cell 601 to the fifth cell 605, the third additional cell 611 is not provided with a P-tap. The size of the third additional cell 613 may be equal to or smaller than at least one of the first cell 601 to the fifth cell 605. That is, the size of the gate electrode of the third additional cell 613 (that is, the width in the direction D1) may be the same as or smaller than that of the first cell 601 to the fifth cell 605. The size of the diffusion region of the third additional cell 613 (that is, the width in the direction D1) may be the same as or smaller than that of the first cell 601 to the fifth cell 605.

By arranging the plurality of cells 601 to 605 and the additional cells 611 to 613 according to the embodiment described in this figure, a sufficient virtual voltage (Virtual_V _DD ) is provided for the standard cells arranged in the area where the voltage drop occurs relatively large, Can be supplied. In addition, since the plurality of additional cells 611 to 613 have a relatively small size as compared with the plurality of cells 601 to 605, there is an advantage in terms of reduction in chip size and layout of standard cells.

15 is a plan view showing a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention. For the sake of simplicity of explanation, a device isolation film (see FIG. 2, STI) is not shown. The layout of the semiconductor device shown in Fig. 15 is similar to the layout of the semiconductor device shown in Fig. 14, except that a plurality of N-taps are provided. Therefore, redundant description will be omitted.

A plurality of N-taps may be formed in the P-type substrate. For example, the N-tap may be arranged to extend in the second direction D2 and may be adjacent to the P-tap. Although P-tabs and N-taps are shown as being spaced apart from each other in the drawings, P-tabs and N-tabs may be in contact with each other at the boundary between N wells and P-type substrates. For example, the plurality of N-taps may be doped with a P-type impurity, and the doping concentration of the N-taps may be different from the doping concentration of the P-type substrate. Although not described in the separate drawings, a P-well doped with a P-type impurity may be formed in the P-type substrate. In this case, the N-taps may be formed in the P well.

16 is a plan view showing a layout of a semiconductor device applied to a power gate switching system according to an embodiment of the present invention. For the sake of simplicity of explanation, a device isolation film (see FIG. 2, STI) is not shown.

The elements formed in the N wells of the layout of the semiconductor device shown in this figure are substantially the same as those described in Figs. 14 and 15, and thus a duplicate description will be omitted. The N-taps formed in the P-type substrate (or the P-well formed in the P-type substrate) are substantially the same as those described in FIG. 15, and thus overlapping description will be omitted.

Subsequently, referring to FIG. 16, sixth to eighth cells 821 to 825 may be formed on a P-type substrate. Each of the sixth to eighth cells 821 to 825 may include at least one gate electrode and at least two diffusion regions. As shown in the figure, each of the sixth to tenth cells 821 to 825 may be formed between two N-taps.

The first additional cell 811 is substantially the same as that described above with reference to FIG. 15, and thus a duplicated description will be omitted.

The second additional cell 812 may be formed to extend in the second direction D2 across the second row (Row2) to the fourth row (Row4). Illustratively, the second additional cell 812 is shown to have 2H. The second cell 812 includes at least two diffusion regions formed in the P-type substrate of the second row Row2, at least two diffusion regions formed in the N well of the third row Row3, Row 3), and at least one gate electrode. That is, these diffusion regions can share at least one gate electrode with each other. However, when two or more gate electrodes are provided, these diffusion regions may not share the gate electrode. For example, the diffusion regions formed in the N well may be doped with a P-type impurity, and the diffusion regions formed in the P-type substrate may be doped with an N-type impurity.

A third additional cell 813 may be formed to extend in the second direction D2 across the second row (Row2) to the fourth row (Row4). Illustratively, the second additional cell 812 is shown to have 2H. The second cell 812 includes at least two diffusion regions formed in the P-type substrate of the second row Row2, at least two diffusion regions formed in the N well of the third row Row3, Row 3), and at least one gate electrode.

For example, the diffusion regions formed in the second row (Row2) of the components of the third additional cell 813 may share the gate electrodes with the diffusion regions of the cell 822. [ Or the fourth row Row4 of the components of the third additional cell 813 may share a gate electrode with the diffusion regions of the cell 825. [ That is, at least some or all of the diffusion regions of the third additional cell 813 may share a gate electrode with the cell 822 and / or 825.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

101, 102, 103, 104, 105, 106: diffusion region

Claims (20)

A substrate doped with a first type, the substrate extending in a first direction and formed with a doped well of a second type;
A first gate electrode extending on the well in a second direction perpendicular to the first direction;
A first diffusion region and a second diffusion region formed in the wells on both sides of the first gate electrode, wherein the first diffusion region is supplied with a power supply voltage and the second diffusion region is formed with a gate Outputting a virtual voltage according to a voltage;
A second gate electrode extending in the second direction on the well;
A third diffusion region and a fourth diffusion region formed in the wells on both sides of the second gate electrode, wherein the third diffusion region is supplied with the power source voltage and the fourth diffusion region is applied to the second gate electrode Outputting the virtual voltage according to a gate voltage;
A third gate electrode disposed between the first gate electrode and the second gate electrode on the well and extending in the second direction;
A fifth diffusion region and a sixth diffusion region formed in the wells on both sides of the third gate electrode, wherein the fifth diffusion region is supplied with the power source voltage and the sixth diffusion region is applied to the third gate electrode Outputting the virtual voltage according to a gate voltage;
A first P-tab formed in the well adjacent to the first diffusion region and extending in the second direction, the first P-tab being supplied with a first bias voltage; And
And a second P-tab formed in the well adjacent to the fourth diffusion region and extending in the second direction, the second P-tap being supplied with the first bias voltage,
Wherein the first diffusion region to the sixth diffusion region are doped with the first type and the first P-tap and the second P-tap are doped with the second type. The method according to claim 1,
And a distance between the first P-tap and the second P-tap is set according to a doping concentration of the well. The method according to claim 1,
Further comprising a plurality of element isolation films adjacent to each of the first P-tap to the fourth P-tap. The method according to claim 1,
Wherein a distance between the first gate electrode and the third gate electrode in the first direction is 1/4 to 3/4 of a distance between the first gate electrode and the second gate electrode. The method according to claim 1,
A third P-tab formed in the well adjacent to the second diffusion region; And
And a fourth P-tap formed in the well adjacent to the third diffusion region. The method according to claim 1,
And the doping concentration of the first P-tap to the fourth P-tap is different from the doping concentration of the N-well. The method according to claim 1,
Wherein the level of the first bias voltage is equal to the level of the power supply voltage. The method according to claim 1,
A first N-tab formed on the substrate, the first N-tap being adjacent to the first P-tap in the second direction and extending in the second direction, the first N-tab being supplied with a second bias voltage; And
And a second N-tap formed on the substrate, the second N-tap being adjacent to the second P-tap in the second direction and extending in the second direction, the second N-tap being supplied with the second bias voltage. 9. The method of claim 8,
Wherein the first N-taps and the second N-taps are doped with the first type and the doping concentration of the substrate and the doping densities of the first N-taps and the second N- system. 9. The method of claim 8,
And the second bias voltage is a ground voltage. 9. The method of claim 8,
A fourth gate electrode adjacent to the first gate electrode in the second direction and extending in the second direction on the substrate;
And a seventh diffusion region and an eighth diffusion region formed in the wells on both sides of the fourth gate electrode, wherein the seventh diffusion region is supplied with the power source voltage and the eighth diffusion region is provided with the fourth gate electrode Outputting the virtual voltage according to a gate voltage;
A fifth gate electrode adjacent to the second gate electrode in the second direction and extending in the second direction on the substrate;
And a ninth diffusion region and a tenth diffusion region formed in the wells on both sides of the fifth gate electrode, wherein the ninth diffusion region is supplied with the power source voltage and the tenth diffusion region is provided with the fifth gate electrode Outputting the virtual voltage according to a gate voltage;
A sixth gate electrode adjacent to the third gate electrode in the second direction and extending in the second direction on the substrate;
And an eleventh diffusion region and a twelfth diffusion region formed in the wells on both sides of the sixth gate electrode, wherein the tenth diffusion region is supplied with the power source voltage and the twelfth diffusion region is applied to the sixth gate electrode And outputting the virtual voltage according to a gate voltage. A substrate doped with a first type, wherein a plurality of wells doped with a second type are formed in the substrate, the plurality of wells extending in a first direction and formed in a second direction perpendicular to the first direction that;
Wherein the first cell includes a first gate electrode, a first diffusion region formed in the first well on both sides of the first gate electrode, and a second diffusion region formed in the first well of the plurality of wells, To do;
And a second cell formed in the second well adjacent to the first well in the second direction, wherein the second cell comprises a second gate, a third diffusion formed in the second well on both sides of the second gate electrode, Region and a fourth diffusion region, said second cell being spaced apart from said first cell in said first direction;
Further cells formed in the first well between the first cell and the second cell, the additional cell comprising a first additional diffusion region formed in the first well on both sides of the additional gate electrode and the additional gate electrode, 2 containing an additional diffusion region;
At least one first P-tab formed in the first well adjacent to the first cell; And
And at least one second P-tap formed in the second well adjacent to the second cell. 13. The method of claim 12,
The first P-taps and the second P-taps are doped with the first type, and the first P-taps and the second P- 2 type doped power gate switching system. 14. The method of claim 13,
A power supply voltage is supplied to the first diffusion region, the third diffusion region, and the first additional diffusion region,
A gate voltage is applied to the first gate electrode, the second gate electrode, and the additional gate electrode,
And a virtual voltage is output to the second diffusion region, the fourth diffusion region, and the second additional diffusion region according to application of the gate voltage. 14. The method of claim 13,
And a bias voltage is applied to the first P-tap and the second P-tap. 16. The method of claim 15,
Wherein the level of the bias voltage is equal to the level of the power supply voltage. 14. The method of claim 13,
At least one first N-tab formed adjacent to the at least one first P-tab on a substrate between the first well and the second well; And
And at least one second N-tab formed adjacent to the at least one second P-tab on a substrate between the first well and the second well,
Wherein the first N-taps and the second N-taps are doped with the first type. 18. The method of claim 17,
And the ground voltage is applied to the first N-tap and the second N-tap. 18. The method of claim 17,
A third cell formed adjacent to the first cell and the at least one first N-tap on a substrate between the first well and the second well, the third cell comprising a third gate electrode, A fifth diffusion region and a sixth diffusion region formed on the substrate on both sides of the gate electrode; And
A fourth cell formed adjacent to the second cell and the at least one second N-tup on a substrate between the first well and the second well, the fourth cell comprising a fourth gate electrode, And a seventh diffusion region and an eighth diffusion region formed in the substrate on both sides of the gate electrode. 20. The method of claim 19,
And the fifth diffusion region to the eighth diffusion region are doped with the second type.

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