TW201712851A - Semiconductor device and power gate switching system - Google Patents

Abstract

A semiconductor device and a power gate switching system are provided. The semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

Description

Power brake switching system

The inventive concept relates to a power gate switching system for supplying a virtual power supply voltage to a standard cell.

In general, to operate a standard cell of a semiconductor device, a power supply voltage is supplied to a standard cell from the outside of the semiconductor device via a power gate switch. The voltage output from the power gate switch can be referred to as a virtual power source voltage. To achieve stable operation of the semiconductor device, the virtual supply voltage should be equally applied to each of the standard cells. However, the semiconductor device can have a large voltage drop at a region relatively far from the power gate switch. For example, a standard cell remote from the power gate switch may not receive a power supply voltage that is at the same level as a standard cell near the power gate switch. In this case, the farther standard cell can fail.

According to an exemplary embodiment of the inventive concept, there is provided a semiconductor device comprising: a dummy power line extending in a first direction; a n-well extending in the first direction, wherein the virtual power line and the n The wells are disposed in a column; the first power gate switch cell is disposed in the n well; the second power gate switch cell is disposed in the n well, wherein the first power gate switch cell and the first The second power gate switch cell is a first type of cell; and the third power gate switch cell is disposed in the n well between the first power gate switch cell and the second power gate switch cell And wherein the third power gate switch cell is a second type of cell different from the first type of cell.

According to an exemplary embodiment of the inventive concept, a power gate switching system is provided, including: a first virtual power line extending in a first direction; a first power gate cell connected to the first virtual power line; a second power gate cell connected to the first virtual power line, wherein the first power gate cell and the second power gate cell respectively comprise at least one tap; and a third power gate cell connected to The first virtual power line is disposed between the first power gate cell and the second power gate cell, wherein the third power gate cell does not include a tap, and wherein the first power source The gate cell to the third power gate cell and the first virtual power line are arranged in the first column.

According to an exemplary embodiment of the inventive concept, a power gate switching system includes: a first column including a first virtual power line, a first power gate cell, and a second power gate cell, wherein the first power source The gate cell includes a first gate electrode disposed between the first diffusion region and the second diffusion region, and at least one tap, wherein the second power gate cell includes a third diffusion region and a fourth diffusion region a second gate electrode and not including a tap; and a second column comprising a second virtual power line, a third power gate cell, and a fourth power gate cell, wherein the third power gate cell includes a a third gate electrode between the fifth diffusion region and the sixth diffusion region, and at least one tap, and the fourth power gate cell includes a fourth gate electrode disposed between the seventh diffusion region and the eighth diffusion region The tap is not included, and wherein the fourth power gate cell is coupled to the second power gate cell.

FIG. 1 is a plan view illustrating a power gate switching system 100 in accordance with an exemplary embodiment of the inventive concept. 2 is a cross-sectional view taken along line AA' of FIG. 1 according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 1 and 2, the power gate switching system 100 may include: a p-type substrate P-sub; N well formed in the p-type substrate P-sub; first to sixth diffusion regions 101, 102, 103, 104, 105 and 106 are formed in the N well; the first gate electrode G1 is formed on the N well and formed between the first diffusion region 101 and the second diffusion region 102; the second gate electrode G2 is formed on the N well and formed Between the third diffusion region 103 and the fourth diffusion region 104; a third gate electrode G3 is formed on the N well and formed between the fifth diffusion region 105 and the sixth diffusion region 106; the first p tap P-tab1, Adjacent to the first diffusion region 101 formed in the N well; a second p tap P-tab2 adjacent to the second diffusion region 102 formed in the N well; a third p tap P-tab3 adjacent to the third diffusion region 103 formed in the N well; A fourth p-tap P-tab4 is formed adjacent to the fourth diffusion region 104 in the N-well.

The N well can extend in the first direction D1. For example, the N well can be a region doped with an n-type impurity.

The first to sixth diffusion regions 101 to 106 may be formed to extend in the first direction D1 in the N well. The first diffusion region 101 and the second diffusion region 102 may be spaced apart from each other, and the first gate electrode G1 may be disposed on a region between the first diffusion region 101 and the second diffusion region 102. The third diffusion region 103 and the fourth diffusion region 104 may be spaced apart from each other, and the second gate electrode G2 may be disposed on a region between the third diffusion region 103 and the fourth diffusion region 104. The fifth diffusion region 105 and the sixth diffusion region 106 may be formed between the second diffusion region 102 and the third diffusion region 103. The fifth diffusion region 105 and the sixth diffusion region 106 may be spaced apart from each other, and the third gate electrode G3 may be disposed on a region between the fifth diffusion region 105 and the sixth diffusion region 106. Each of the first to sixth diffusion regions 101 to 106 may be doped with a p-type impurity.

For example, the size of each of the fifth diffusion region 105 and the sixth diffusion region 106 may be smaller than the size of each of the first diffusion region 101 to the fourth diffusion region 104. In addition, the size of the third gate electrode G3 (for example, the width in the first direction D1) may be smaller than the size of the first gate electrode G1 or the second gate electrode G2 (for example, the width in the first direction D1).

The power supply voltage V _DD may be supplied to the first diffusion region 101. In the case where the gate voltage Gate_CTRL is applied to the first gate electrode G1 to form the first channel between the first diffusion region 101 and the second diffusion region 102, the power supply voltage V _DD applied to the first diffusion region 101 may be via The first channel and the second diffusion region 102 are output in the form of a virtual power supply voltage Virtual_V _DD . The virtual supply voltage Virtual_V _DD can be supplied to a standard cell for implementing the logic circuit.

The power supply voltage V _DD may be supplied to the third diffusion region 103. In the case where the gate voltage Gate_CTRL is applied to the second gate electrode G2 to form the second channel between the third diffusion region 103 and the fourth diffusion region 104, the power supply voltage V _DD applied to the fourth diffusion region 104 may be via The second channel and the fourth diffusion region 104 are output in the form of a virtual power supply voltage Virtual_V _DD . A virtual power supply voltage Virtual_V _DD may be supplied to the standard cell for implementing the logic circuit.

The power supply voltage V _DD may be supplied to the fifth diffusion region 105. In the case where the gate voltage Gate_CTRL is applied to the third gate electrode G3 to form a third channel between the fifth diffusion region 105 and the sixth diffusion region 106, the power supply voltage V _DD applied to the fifth diffusion region 105 may be via The third channel and the sixth diffusion region 106 are output as a virtual power supply voltage Virtual_V _DD . A virtual power supply voltage Virtual_V _DD may be supplied to the standard cell for implementing the logic circuit.

An insulating layer may be further formed between the first gate electrode G1 and the N well, between the second gate electrode G2 and the N well, and between the third gate electrode G3 and the N well.

The first p-tap P-tab1 and the second p-tap P-tab2 may be formed adjacent to the first diffusion region 101 and the second diffusion region 102, respectively. The third p-tap P-tab3 and the fourth p-tap P-tab4 may be formed adjacent to the third diffusion region 103 and the fourth diffusion region 104, respectively. For example, each of the first p-tap P-tab1 to the fourth p-tap P-tab4 may be a region doped with an n-type impurity. The first p-tap to the fourth p-tap P-tab4 may have a different doping concentration than the doping concentration of the N-well. The first p-tap P-tab1 to the fourth p-tap P-tab4 may extend in the second direction D2. Further, although the first p-tap P-tab1 is shown not to be in direct contact with the first diffusion region 101, the first p-tap P-tab1 may be in direct contact with the first diffusion region 101. The second p-tap P-tab2 to the fourth p-tap P-tab4 may be formed in a manner similar to the first p-tap P-tab1.

The bias voltage Vbias can be applied to the first p-tap P-tab1 to the fourth p-tap P-tab4. The bias voltage Vbias prevents a latch-up phenomenon from occurring in the power gate switching system 100. Although the bias voltage Vbias is shown to be applied separately to the first p-tap P-tab1 to the fourth p-tap P-tab4, the power supply voltage V _DD may be applied to the first p-tap P-tab1 instead of the bias voltage V _DD The fourth p tap P-tab4.

The distance between the second p-tap P-tab2 and the third p-tap P-tab3 can be determined by considering the doping concentration of the N-well. For example, the second p-tap P-tab2 and the third p-tap P-tab3 may be adapted to prevent distances at which the latch-up phenomenon occurs in the power gate switching system 100 from being spaced apart from one another. For example, in a 10 nanometer logic process, the distance between the taps can be about 50 microns. If the distance between the second p-tap P-tab2 and the third p-tap P-tab3 is greater than a critical distance (eg, the distance at which the latch-up phenomenon can be prevented), the fifth diffusion region 105 or the sixth diffusion region can be accessed. 106 sets at least one additional p tap. Even when the distance between the second p-tap P-tab2 and the third p-tap P-tab3 is within a range suitable for preventing the latch-up phenomenon, between the second diffusion region 102 and the third diffusion region 103 One of the standard cells may not receive enough power supply voltage V _DD . Therefore, by providing the fifth diffusion region 105, the sixth diffusion region 106, and the third gate electrode G3, the stable power supply voltage V _DD can be supplied to the standard between the second diffusion region 102 and the third diffusion region 103. Cells do not need to set additional p-tap.

Referring again to FIGS. 1 and 2, the distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 is shown as the distance between the first gate electrode G1 and the second gate electrode G2 (for example, Half of s2). However, in an exemplary embodiment of the inventive concept, a distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 may be at a distance between the first gate electrode G1 and the second gate electrode G2 (for example, s2) is in the range of 1/4 times to 3/4 times. In an exemplary embodiment of the inventive concept, in order to enable the third channel to be formed at an overlap region between the third gate electrode G3 and the N well, the fifth diffusion region 105 and the sixth diffusion region 106 may be disposed The position is appropriately adjusted in consideration of the position of the third gate electrode G3.

As shown in FIGS. 1 and 2, four p taps may be formed in the power gate switching system 100. However, the inventive concept may not be limited thereto; for example, as shown in FIG. 3, the power gate switching system 100 may include two p taps. The same reference numerals in FIG. 3 as those in FIGS. 1 and 2 may denote the same or similar elements. As an example, as shown in FIG. 3, the p-tap P-tab1 may be disposed adjacent to the first diffusion region 101 and the p-tap P-tab4 may be disposed adjacent to the fourth diffusion region 104. As another example, the p-tap P-tab1 may be disposed adjacent to the first diffusion region 101 and the p-tap P-tab3 may be disposed adjacent to the third diffusion region 103. As a further example, the p-tap P-tab2 can be disposed adjacent to the second diffusion region 102 and the p-tap P-tab4 can be disposed adjacent to 104.

FIG. 4 is a plan view illustrating a power gate switching system 100 in accordance with an exemplary embodiment of the inventive concept. FIG. 5 is a cross-sectional view taken along line AA' of FIG. 4, according to an exemplary embodiment of the inventive concept. The same reference numerals in FIGS. 4 and 5 as those in FIGS. 1 and 2 may denote the same or similar elements.

The power gate switching system 100 can include a device isolation layer STI that can be formed using shallow trench isolation techniques. A device isolation layer STI may be provided to isolate a standard cell located between the second p-tap P-tap2 and the fifth diffusion region 105 or between the sixth diffusion region 106 and the third p-tap P-tab3. Each of the device isolation layers STI may be adjacent to a corresponding one of the p taps and extend in the second direction D2. The device isolation layer STI is shown not in direct contact with the p-tap, however in an exemplary embodiment of the inventive concept, the device isolation layer STI may be in direct contact with the p-tap.

In an exemplary embodiment of the inventive concept, the device isolation layer STI may be formed of a hafnium oxide layer or may include a hafnium oxide layer. For example, the device isolation layer STI can be enhanced by high-density plasma (HDP) oxide, TetraEthyl OrthoSilicate (TEOS), and plasma-enhanced tetraethylorthosilicate. , PE-TEOS), ozone-tetraethyl orthosilicate (O ₃ -TEOS), undoped Silicate Glass (USG), PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG) At least one or any combination thereof is formed.

FIG. 6 is a plan view illustrating a power gate switching system 200 in accordance with an exemplary embodiment of the inventive concept. FIG. 7 is a cross-sectional view taken along line BB' of FIG. 6 according to an exemplary embodiment of the inventive concept. A cross-sectional view taken along line A-A' shown in Fig. 6 will be omitted from Fig. 7 because it is substantially the same as that shown in Fig. 2.

Referring to FIGS. 6 and 7, the power gate switching system 200 may include a p-type substrate P-sub, and an N-well may be formed in the p-type substrate P-sub.

The power gate switching system 200 can include a first diffusion region 201, a second diffusion region 202, a third diffusion region 203, a fourth diffusion region 204, a fifth diffusion region 205, and a sixth diffusion region 206 formed in the N-well. The power gate switching system 200 may include: a first gate electrode G1 formed on the N well and formed between the first diffusion region 201 and the second diffusion region 202; and a second gate electrode G2 formed on the N well and formed in the third The diffusion region 203 and the fourth diffusion region 204; and the third gate electrode G3 are formed on the N well and formed between the fifth diffusion region 205 and the sixth diffusion region 206.

For example, the distance between the first gate electrode G1 and the third gate electrode G3 (eg, s1) may be half the distance between the first gate electrode G1 and the second gate electrode G2 (eg, s2). However, the distance (eg, s1) between the first gate electrode G1 and the third gate electrode G3 may be 1/4 times the distance (eg, s2) between the first gate electrode G1 and the second gate electrode G2 to 3/4 times the range. In an exemplary embodiment of the inventive concept, in order to enable the third channel to be formed at an overlap region between the third gate electrode G3 and the N well, the fifth diffusion region 205 and the sixth diffusion region 206 may be disposed The position is appropriately adjusted in consideration of the position of the third gate electrode G3.

For example, the first to sixth diffusion regions 201 to 206 may be doped with a p-type impurity. The power supply voltage V _DD (for example, as shown in FIG. 2) may be supplied to the first diffusion region 201, the third diffusion region 203, and the fifth diffusion region 205. The power applied to the first diffusion region 201, the third diffusion region 203, and the fifth diffusion region 205 is determined depending on the voltage Gate_CTRL applied to the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3. The voltage V _DD can be used as the virtual power supply voltage Virtual_V _DD to be output via the second diffusion region 202, the fourth diffusion region 204, and the sixth diffusion region 206.

For example, the size of each of the fifth diffusion region 205 and the sixth diffusion region 206 may be smaller than the size of each of the first diffusion region 201 to the fourth diffusion region 204. In addition, the size of the third gate electrode G3 (for example, the width in the first direction D1) may be smaller than the size of the first gate electrode G1 or the second gate electrode G2 (for example, the width in the first direction D1).

The power gate switching system 200 can include first p taps P-tab1 through fourth p taps P-tab4 disposed in the N-well. The first p-tap P-tab1 to the fourth p-tap P-tab4 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The first p-tap P-tab1 may be adjacent to the first diffusion region 201. The second p-tap P-tab2 may be adjacent to the second diffusion region 202. The third p-tap P-tab3 may be adjacent to the third diffusion region 203. The fourth p-tap P-tab4 may be adjacent to the fourth diffusion region 204. The p taps are shown not to be in direct contact with the respective diffusion regions, however in an exemplary embodiment of the inventive concept, the p taps may be in direct contact with the diffusion regions.

For example, the first p-tap P-tab1 to the fourth p-tap P-tab4 may be doped with an n-type impurity and may have a different doping concentration than the doping concentration of the N-well. A bias voltage Vbias (for example, as shown in FIG. 2) may be applied to the first p-tap P-tab1 to the fourth p-tap P-tab4 to prevent the latch-up phenomenon from occurring.

The power gate switching system 200 may further include first n-tap N-tab1 to fourth n-tap N-tab4, the first n-tap N-tab1 to the fourth n-tap N-tab4 being formed in the p-type substrate P-sub as The second direction D2 extends and is formed to be spaced apart from each other in the first direction D1. In the p-type substrate P-sub, the first n-tap N-tab1 may be parallel to the second direction D2 and coaxial with the first p-tap P-tab1. In the p-type substrate P-sub, the second n-tap N-tab2 may be parallel to the second direction D2 and coaxial with the second p-tap P-tab2. In the p-type substrate P-sub, the third n-tap N-tab3 may be parallel to the second direction D2 and coaxial with the third p-tap P-tab3. In the p-type substrate P-sub, the fourth n-tap N-tab4 may be parallel to the second direction D2 and coaxial with the fourth p-tap P-tab4.

For example, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be doped with a p-type impurity, and the first n-tap N-tab1 to the fourth n-tap N-tab4 may have a p-type substrate P The doping concentration of -sub is different. The bias voltage Vbias2 may be applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 to prevent the latch-up phenomenon from occurring. In an exemplary embodiment of the inventive concept, the bias voltage Vbias2 applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 may be a ground voltage.

As shown in FIG. 6, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be spaced apart from the first p-tap P-tab1 to the fourth p-tap P-tab4. However, each of the first n-tap N-tab1 to the fourth n-tap N-tab4 may be at a boundary between the p-type substrate P-sub and the N-well with the first p-tap P-tab1 to the fourth p A corresponding one of the taps P-tab4 is in contact.

The distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 may take into account the doping concentration of the N-well, p The doping concentration of the type substrate P-sub or a combination thereof is determined. For example, the distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 may be at a power gate Within the range of the latching phenomenon occurring in the switching system 200.

Similar to the one described with reference to FIG. 3, the p-tap can be composed only of the first p-tap P-tab1 and the third p-tap P-tab3 or only the first p-tap P-tab1 and the fourth p-tap P-tab4 . Furthermore, the n-tap may consist of only the first n-tap N-tab1 and the third n-tap N-tab3 or only the first n-tap N-tab1 and the fourth n-tap N-tab4. In addition, the power gate switching system 200 may further include a plurality of device isolation layers STI as shown in FIGS. 4 and 5.

Referring back to FIG. 6, a plurality of standard cells STD Cells may be disposed between the second p-tap P-tab2 and the third p-tap P-tab3 and between the second n-tap N-tab2 and the third n-tap N-tab3 . The virtual power supply voltage Virtual_V _DD and the ground voltage V _SS can be supplied to a plurality of standard cells STD Cells. In the case of virtual power voltage Virtual_V _DD via the output 202 and the fourth diffusion region of the second diffusion region 204, the virtual power voltage Virtual_V _DD can be sufficiently supplied to the plurality of standard cells in membered STD Cells adjacent to the second diffusion region 202 and the second Some standard cells STD Cells are placed in the four diffusion regions 204. However, the virtual power supply voltage Virtual_V _DD may not be sufficiently supplied to some of the standard cells STD Cells located between the second diffusion region 202 and the fourth diffusion region 204. For the standard cells that are not sufficiently supplied with the virtual power supply voltage Virtual_V _DD , the fifth diffusion region 205 and the sixth diffusion region 206 and the third gate electrode G3 may be further provided. In this case, the virtual power supply voltage Virtual_V _DD outputted through the sixth diffusion region 206 may be supplied to adjacent standard cells, and thus, the positions are closer to the second diffusion region 202 and the fourth diffusion region 204. The standard cell at the midpoint between them can be stably operated.

According to an exemplary embodiment of the inventive concept, by providing the fifth diffusion region 205 and the sixth diffusion region 206 and the third gate electrode G3, an additional supply of the virtual power supply voltage Virtual_V _DD can be achieved without setting any additional p-tap. Therefore, the virtual power supply voltage Virtual_V _DD can be efficiently and stably supplied to the standard cell STD Cells without increasing the chip size.

FIG. 8 is a plan view illustrating a power gate switching system 300 in accordance with an exemplary embodiment of the inventive concept. FIG. 9 is a cross-sectional view taken along line BB' of FIG. 8 according to an exemplary embodiment of the inventive concept. A cross-sectional view taken along line A-A' shown in Fig. 8 will be omitted from Fig. 9 because it is substantially the same as that shown in Fig. 2.

Referring to FIGS. 8 and 9, the N well may be formed to extend in the first direction D1 in the p-type substrate P-sub. A P well extending in the first direction may be formed adjacent to the N well in the second direction D2. As shown in FIG. 8, the N and P wells may be spaced apart from each other in the second direction D2, however in an exemplary embodiment of the inventive concept, the N and P wells may be in contact with each other in the second direction D2.

The first to sixth diffusion regions 301 to 306 and the first p-tap P-tab1 to the fourth p-tap P-tab4 may be formed in the N-well, and the first to third gate electrodes G1 to G3 may be formed on the N-well . For example, the first to sixth diffusion regions 301 to 306, the first p-tap P-tab1 to the fourth p-tap P-tab4, and the first to third gate electrodes G1 to G3 may be configured to have The features set forth with reference to Figures 6 through 7 are substantially identical and, therefore, will not be described again.

As shown in FIGS. 8 and 9, the first n-tap N-tab1 to the fourth n-tap N-tab4 extending in the second direction D2 and spaced apart from each other in the first direction D1 may be disposed in the P-well. In the P well, the first n tap N-tab1 may be parallel to the second direction D2 and coaxial with the first p tap P-tab1. In the P well, the second n-tap N-tab2 may be parallel to the second direction D2 and coaxial with the second p-tap P-tab2. In the P well, the third n-tap N-tab3 may be parallel to the second direction D2 and coaxial with the third p-tap P-tab3. In the P well, the fourth n-tap N-tab4 may be parallel to the second direction D2 and coaxial with the fourth p-tap P-tab4.

In an exemplary embodiment of the inventive concept, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be doped with a p-type impurity, and the first n-tap N-tab1 to the fourth n-tap N-tab4 The doping concentration can be different from the doping concentration of the P well. The bias voltage Vbias2 may be applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 to prevent the latch-up phenomenon from occurring. In an exemplary embodiment of the inventive concept, the bias voltage Vbias2 applied to the first n-tap N-tab1 to the fourth n-tap N-tab4 may be a ground voltage.

As shown in FIG. 8, the first n-tap N-tab1 to the fourth n-tap N-tab4 may be spaced apart from the first p-tap P-tab1 to the fourth p-tap P-tab4. However, the N and P wells may be in contact with each other, and each of the first n-tap N-tab1 to the fourth n-tap N-tab4 may be at the boundary between the N-well and the P-well with the first p-tap P The corresponding one of the -tab1 to the fourth p tap P-tab4 is in contact.

The distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 may take into account the doping concentration of the N-well, P The doping concentration of the well or a combination thereof is determined. For example, the distance between the second p-tap P-tab2 and the third p-tap P-tab3 and the distance between the second n-tap N-tab2 and the third n-tap N-tab3 may be at a power gate Within the range of the latching phenomenon occurring in the switching system 300.

Similar to the one described with reference to FIG. 3, the p-tap can be composed only of the first p-tap P-tab1 and the third p-tap P-tab3 or only the first p-tap P-tab1 and the fourth p-tap P-tab4 . Furthermore, the n-tap may consist of only the first n-tap N-tab1 and the third n-tap N-tab3 or only the first n-tap N-tab1 and the fourth n-tap N-tab4. In addition, the power gate switching system 300 may further include a plurality of device isolation layers STI as shown in FIGS. 4 and 5.

FIG. 10 is a plan view illustrating a power gate switching system 400 in accordance with an exemplary embodiment of the inventive concept. FIG. 11 is a cross-sectional view taken along line BB' of FIG. 10, according to an exemplary embodiment of the inventive concept. A cross-sectional view taken along line A-A' shown in Fig. 10 will be omitted from Fig. 11 because it is substantially the same as that shown in Fig. 2.

Referring to Figures 10 and 11, the power gate switching system 400 will be described in detail below. The power gate switching system 400 may include: an N well formed to extend in the first direction D1; a first diffusion region 401 to a sixth diffusion region 406 and first p taps P-tab1 to fourth p taps P-tab4, forming In the N well; and the first gate electrode G1 to the third gate electrode G3 are formed on the N well. The first to sixth diffusion regions 401 to 406 may be doped with p-type impurities, and the first p-tap P-tab1 to the fourth p-tap P-tab4 may be doped with an n-type impurity. The first p-tap to the fourth p-tap P-tab4 may have a different doping concentration than the doping concentration of the N-well.

The distance between the first gate electrode G1 and the second gate electrode G2 can be determined by considering the doping concentration of the N well. In other words, the first gate electrode G1 and the second gate electrode G2 may be capable of preventing the distances at which the latch-up phenomenon occurs in the power gate switching system 400 from being spaced apart from each other. For example, the distance s1 between the first gate electrode G1 and the third gate electrode G3 may be in the range of 1/4 to 3/4 times the distance s2 between the first gate electrode G1 and the second gate electrode G2. Inside.

Elements disposed in the N-well or disposed on the N-well may have substantially the same features as those illustrated with reference to Figures 1, 2, and 6, and thus, will not be described again.

The power gate switching system 400 may include a seventh diffusion region 407 to a twelfth diffusion region 412 formed in the p-type substrate P-sub to extend in the second direction D2 And formed to be spaced apart from each other in the first direction D1. The first diffusion region 401 and the seventh diffusion region 407 may be formed to be coaxial with each other, thereby forming a row. The seventh diffusion region 407 may be doped with an n-type impurity. Similarly, each of the eighth diffusion region 408 to the twelfth diffusion region 412 may be formed to be coaxial with a corresponding one of the second diffusion region 402 to the sixth diffusion region 406, thereby forming individual rows.

The fourth gate electrode G4 may be formed on the p-type substrate P-sub and formed between the seventh diffusion region 407 and the eighth diffusion region 408. The fifth gate electrode G5 may be formed on the p-type substrate P-sub and formed between the ninth diffusion region 409 and the tenth diffusion region 410. The sixth gate electrode G6 may be formed on the p-type substrate P-sub and formed between the eleventh diffusion region 411 and the twelfth diffusion region 412. An insulating layer may be further disposed between the fourth gate electrode G4, the fifth gate electrode G5, the sixth gate electrode G6, and the p-type substrate P-sub. For example, the seventh to twelfth diffusion regions 407 to 412 may be doped with an n-type impurity.

The first n-tap N-tab1 and the second n-tap N-tab2 may be formed in the p-type substrate P-sub adjacent to the seventh diffusion region 407 and the eighth diffusion region 408, respectively. Although the first n-tap N-tab1 and the second n-tap N-tab2 are shown not in direct contact with the seventh diffusion region 407 and the eighth diffusion region 408, the first n-tap N-tab1 and the second n-tap N -tab2 may be in direct contact with the seventh diffusion region 407 and the eighth diffusion region 408, respectively. The first n-tap N-tab1 to the fourth n-tap N-tab4 may be doped with a p-type impurity. The first n-tap N-tab1 to the fourth n-tap N-tab4 may have a different doping concentration than the doping concentration of the p-type substrate P-sub.

A ground voltage V _SS may be applied to the seventh diffusion region 407. Depending on the voltage Gate_CTRL applied to the fourth gate electrode G4, the ground voltage V _SS can be used as the virtual ground voltage Virtual_V _SS to be output via the eighth diffusion region 408. The virtual ground voltage Virtual_V _SS can be supplied to at least one standard cell adjacent to the location. The ground voltage _Vss can also be supplied to at least one standard cell adjacent to the location.

To prevent the latch-up phenomenon from occurring in the power gate switching system 400, a bias voltage Vbias2 can be applied to the first n-tap N-tab1 and the second n-tap N-tab2. Although the bias voltage Vbias2 is shown to be applied separately to the first n-tap N-tab1 and the second n-tap N-tab2, the ground voltage V _SS may be applied to the first n-tap N-tab1 and the second instead of the bias voltage Vbias2 Two n taps N-tab2.

The third n-tap N-tab3 and the fourth n-tap N-tab4 may be formed in the p-type substrate P-sub adjacent to the ninth diffusion region 409 and the tenth diffusion region 410, respectively. Although the third n-tap N-tab3 and the fourth n-tap N-tab4 are shown not in direct contact with the ninth diffusion region 409 and the tenth diffusion region 410, respectively, the third n-tap N-tab3 and the fourth n-tap N-tab 4 may be formed to be in direct contact with the ninth diffusion region 409 and the tenth diffusion region 410, respectively.

A ground voltage V _SS may be applied to the ninth diffusion region 409. Depending on the voltage Gate_CTRL applied to the fifth gate electrode G5, the ground voltage V _SS can be used as the virtual ground voltage Virtual_V _SS to be output via the tenth diffusion region 410. The virtual ground voltage Virtual_V _SS can be supplied to at least one standard cell adjacent to the location. The ground voltage _Vss can also be supplied to at least one standard cell adjacent to the location.

The bias voltage Vbias2 can be applied to the third n-tap N-tab3 and the fourth n-tap N-tab4. Although the bias voltage Vbias2 is shown as being applied separately to the third n-tap N-tab3 and the fourth n-tap N-tab4, the ground voltage _Vss can be applied to the third n-tap N-tab3 instead of the bias voltage Vbias2 and Four n taps N-tab4.

In the case of a virtual ground voltage via the output Virtual_V _SS eighth or tenth diffusion region 408 in the diffusion region 410, the virtual ground voltage Virtual_V _SS can be sufficiently supplied to the standard cell adjacent to the eighth or tenth diffusion region 408 of the element diffusion region 410 . However, the virtual ground voltage Virtual_V _SS may not be sufficiently supplied to other standard cells located between the eighth diffusion region 408 and the tenth diffusion region 410. For such a standard cell that is not sufficiently supplied with the virtual ground voltage Virtual_V _SS , the eleventh diffusion region 411 and the twelfth diffusion region 412 and the sixth gate electrode G6 may be further provided.

For example, the sizes of the eleventh diffusion region 411 and the twelfth diffusion region 412 (eg, the width in the first direction D1) may be smaller than the size of the seventh diffusion region 407 to the tenth diffusion region 410 (for example, at The width in the first direction D1). The size of the sixth gate electrode G6 (for example, the width in the first direction D1) may also be smaller than the size of the fourth gate electrode G4 or the fifth gate electrode G5 (for example, the width in the first direction D1).

According to an exemplary embodiment of the inventive concept, the fifth diffusion region 405 and the sixth diffusion region 406, the third gate electrode G3, the eleventh diffusion region 411 and the twelfth diffusion region 412, and the sixth gate electrode G6 are disposed. Therefore, the virtual power supply voltage Virtual_V _DD can be stably supplied to the insufficiently supplied virtual ground voltage Virtual_V located in the weak region (for example, between the diffusion region 402 and the diffusion region 404 or between the diffusion region 408 and the diffusion region 410) The standard cell of _SS . In addition, the size of the semiconductor wafer can be reduced by adding a relatively small component without an additional p-tap or n-tap.

FIG. 12 is a plan view illustrating a power gate switching system 500 in accordance with an exemplary embodiment of the inventive concept. FIG. 13 is a cross-sectional view taken along line BB' of FIG. 12, according to an exemplary embodiment of the inventive concept. A cross-sectional view taken along line A-A' shown in Fig. 12 will be omitted from Fig. 13 because it is substantially the same as that shown in Fig. 2.

Referring to Figures 12 and 13, the power gate switching system 500 will be described in detail below. The power gate switching system 500 shown in FIGS. 12 and 13 may include a p-type substrate P-sub, and a p-well and a P-well are formed in the p-type substrate P-sub. The N and P wells may be adjacent to each other in the second direction D2 and may extend in the first direction D1.

The power gate switching system 500 may include: a seventh diffusion region 507 to a twelfth diffusion region 512 formed in the P well, and first n-tap N-tab1 to fourth n-tap N-tab4, and a fourth formed on the P-well Gate electrode G4 to sixth gate electrode G6. In addition, the power gate switching system 500 can be similar to that shown in FIGS. 10 and 11. For example, the power gate switching system 500 can include first to sixth diffusion regions 501 to 506 formed in the N-well and first to fourth p-tap-P1 to P-tab4, and formed on the N-well. The first gate electrode G1 to the third gate electrode G3. Therefore, it will not be repeated.

In an exemplary embodiment of the inventive concept, the distance s1 between the first gate electrode G1 and the third gate electrode G3 may be 1/4 times the distance s2 between the first gate electrode G1 and the second gate electrode G2. Up to 3/4 times, and the distance s1 between the fourth gate electrode G4 and the sixth gate electrode G6 may be 1/4 times the distance s2 between the fourth gate electrode G4 and the fifth gate electrode G5 3/4 times the range. The size of each of the diffusion regions 505, 506, 511, and 512 (eg, the width in the first direction D1) may be smaller than each of the diffusion regions 501 to 504 or 507 to 510 (eg, at The width in the first direction D1). The size of each of the gate electrode G3 and the gate electrode G6 (for example, the width in the first direction D1) may also be smaller than the size of each of the gate electrodes G1, G2, G4, and G5 (for example, at the The width in one direction D1).

FIG. 14 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept. For the sake of brevity, the device isolation layer (eg, the STI shown in Figure 4) is omitted from Figure 14.

Referring to FIG. 14, a plurality of N wells extending in the first direction D1 and spaced apart from each other in the second direction D2 may be formed in the p-type substrate P-sub. For example, the N well may extend parallel to the first column Row1, the third column Row3, and the fifth column Row5. In Figure 14, the N well is shown by cross hatching. As shown in FIG. 14, the virtual power line Virtual_V _DD may be disposed to span the N well in the first direction D1, and the ground line V _SS may be disposed to span the p-type substrate P-sub in the first direction D1. The distance between the virtual power line Virtual_V _DD measured in the second direction D2 and the ground line V _SS is referred to as 1H.

Various standard cells constituting the semiconductor logic circuit and a power gate switching system for supplying the virtual power source Virtual_V _DD to the standard cell may be disposed on the p-type substrate P-sub and on the N-well. The power gate cell and its adjacent p-tap can be evenly placed by utilizing a layout design tool.

For example, the first cell 601 can overlap with the N well located on the first column Row1. The first cell 601 can include at least one gate electrode and at least one diffusion region. The at least two diffusion regions of the first cell 601 may be regions doped with p-type impurities. Two p taps can be placed adjacent to the first cell 601. As shown in FIG. 14, the two p taps may or may not be in direct contact with the first cell 601. Although two p taps are shown, as described above, the p taps may be formed individually. For example, the p-tap can be doped with an n-type impurity, and the doping concentration of the p-tap can be different than the doping concentration of the N-well.

The second cell 602 may be spaced apart from the first cell 601 by a distance s3 and may overlap with the N well located on the first column Row. Similar to the first cell 601, the second cell 602 can include at least one gate electrode and at least two diffusion regions. The distance between the first cell 601 and the second cell 602 (e.g., s3) can be determined by considering the doping concentration of the N well. For example, the first cell 601 and the second cell 602 may be capable of preventing the distance at which the latch-up phenomenon occurs from being spaced apart from each other. The second cell 602 and the first cell 601 can be configured to have substantially the same features except for their locations, and thus, will not be described again.

The third cell 603 can overlap with the N well located on the third column Row3. As shown in FIG. 14, the third cell 603 can be positioned between the first cell 601 and the second cell 602. The third cell 603 and the first cell 601 can be configured to have substantially the same features except for their locations, and thus, a detailed description thereof will not be repeated.

The fourth cell 604 and the fifth cell 605 may overlap with the N well located on the fifth column Row5. The fourth cell 604, the fifth cell 605, and the first cell 601 may be configured to have substantially the same features except for their positions, and thus, a detailed description thereof will not be repeated.

As shown in FIG. 14, even if the first cell 601 to the fifth cell 605 are uniformly disposed, at least one standard cell disposed between the cells may have a shortage or pressure of the virtual power source voltage Virtual_V _DD . drop. In the case of such a large pressure drop, at least one standard cell disposed between each cell may operate abnormally. By setting the first additional cell 611 to the third additional cell 613, at least one standard cell in which a large voltage drop occurs can be prevented from operating abnormally. For example, the pressure drop at the location of the additional cell 611 to the additional cell 613 may not be large.

The first additional cell 611 can overlap with the N well located on the first column Row1. The first additional cell 611 can include at least one gate electrode and at least two diffusion regions. At least two diffusion regions of the first additional cell 611 may be doped with a p-type impurity. However, unlike the first cell 601 to the fifth cell 605, the p tap may not be provided in the first additional cell 611. The size of the first additional cell 611 may be smaller than the size of at least one of the first cell 601 to the fifth cell 605. For example, the size of the gate electrode of the first additional cell 611 (eg, the width in the first direction D1) may be equal to or smaller than at least one of the first cell 601 to the fifth cell 605. size. In addition, the size of the diffusion region of the first additional cell 611 (eg, the width in the first direction D1) may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. In addition, the distance s1 between the first cell 601 and the first additional cell 611 may be in the range of 1/4 to 3/4 times the distance s3 between the first cell 601 and the second cell 602. .

The second additional cell 612 can overlap with the N well located in the third column Row3 and the fifth column Row5. The second additional cell 612 can include at least one gate electrode and at least four diffusion regions. In other words, the diffusion regions of the third column Row3 and the fifth column Row5 may be configured to share the gate electrode. The at least four diffusion regions of the second additional cell 612 may be doped with a p-type impurity. Unlike the first cell 601 to the fifth cell 605, the p tap may not be provided in the second additional cell 612. The size of the second additional cell 612 may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. In other words, the size of the gate electrode of the second additional cell 612 (eg, the width in the first direction D1) may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. The size of the diffusion region of the second additional cell 612 (eg, the width in the first direction D1) may be equal to or smaller than the size of at least one of the first cell 601 to the fifth cell 605. Although the second additional cell 612 is shown to have a length 3H in the second direction D2, the inventive concept is not limited thereto.

The third additional cell 613 may overlap with the N well located on the third column Row3. The third additional cell 613 can include at least one gate electrode and at least two diffusion regions. The third additional cell 613 and the second cell 602 can be configured to share the same gate electrode (eg, the at least one gate electrode). The third additional cell 613 and the fifth cell 605 can be configured to share the same gate electrode (eg, the at least one gate electrode).

The at least two diffusion regions of the third additional cell 613 may be doped with a p-type impurity. Unlike the first cell 601 to the fifth cell 605, the p tap may not be provided in the third additional cell 613. The third additional cell 613 may have a size equal to or smaller than at least one of the first cell 601 to the fifth cell 605. In other words, the size of the gate electrode of the third additional cell 613 (for example, the width in the first direction D1) may be equal to or smaller than the size of the first cell 601 to the fifth cell 605. The size of the diffusion region of the third additional cell 613 (for example, the width in the first direction D1) may be equal to or smaller than the size of the first cell 601 to the fifth cell 605.

As explained with reference to FIG. 14, by providing a plurality of cells 601 to 605 and a plurality of additional cells 611 to 613, the virtual power supply voltage Virtual_V _DD can be sufficiently supplied to be disposed at a region where a large voltage drop can exist. Standard cell. In addition, since each of the additional cell 611 to the additional cell 613 has a smaller size than each of the cell 601 to the cell 605, the size of the semiconductor wafer can be reduced and the placement can be strategically placed. Standard cell.

FIG. 15 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept. For the sake of brevity, the device isolation layer (eg, the STI shown in FIG. 4) is omitted from FIG. The layout of the semiconductor device illustrated in FIG. 15 may be configured to have substantially the same or similar features as the features illustrated in FIG. 14 except that a plurality of n taps are provided, and thus, may no longer be on the previous The elements set forth in Figure 14 are set forth. For example, FIG. 15 shows first to fifth cells 701 to 705 which are similar to the first to fifth cells 601 to 605 shown in FIG. 14, and additional cells 611 shown in FIG. Additional cells 711 to additional cells 713 are added to additional cells 613.

A plurality of n taps may be disposed to overlap the p-type substrate P-sub. For example, each of the n taps can be positioned to extend in a second direction D2, and at least one of the n taps can be adjacent to a corresponding one of the p taps. Although the adjacent pair of p taps and n taps are shown as being spaced apart from each other, they may be in direct contact with each other at the boundary between the N well and the p-type substrate P-sub. The plurality of n taps may be doped with p-type impurities, and the doping concentration of the n-tap may be different from the doping concentration of the p-type substrate P-sub. Further, the P well doped with the p-type impurity may overlap with the p-type substrate P-sub. In this case, the n tap can overlap with the P well.

FIG. 16 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept. For the sake of brevity, the device isolation layer (e.g., the STI shown in Figure 4) is omitted from Figure 16.

The semiconductor device shown in FIG. 16 may include elements that overlap with the N well and have substantially the same features as those shown in FIGS. 14 and 15, and thus, for the sake of brevity, they will not be described again. In addition, the semiconductor device shown in FIG. 16 may include an n-tap that overlaps with the p-type substrate P-sub or P well and has substantially the same features as those shown in FIG. 15, and thus, for the sake of brevity See, we will not repeat them. For example, FIG. 16 shows first to fifth cells 801 to 805 similar to the first to fifth cells 601 to 605 shown in FIG.

Referring to FIG. 16, the sixth cell 821 to the tenth cell 825 may be disposed on the p-type substrate P-sub. Each of the sixth cell 821 to the tenth cell 825 may include at least one gate electrode and at least two diffusion regions. As shown in FIG. 16, each of the sixth cell 821 to the tenth cell 825 can be disposed between two n taps.

The first additional cell 811 can be configured to have substantially the same features as the first additional cell 711 shown in FIG. 15, and thus, for the sake of brevity, it will not be described again.

The second additional cell 812 can extend from the second column Row2 to the fourth column Row4 in the second direction D2. For example, as shown in FIG. 16, the second additional cell 812 can have a length 2H. The second additional cell 812 may include at least two diffusion regions formed in the p-type substrate P-sub of the second column Row2, at least two diffusion regions formed in the N well of the third column Row3, formed in the third column At least two diffusion regions of the p-type substrate P-sub of Row3, and at least one gate electrode. In this case, the diffusion region may be configured to share the at least one gate electrode. However, in the case where two or more gate electrodes are provided, the diffusion regions may not share a single gate electrode. For example, the diffusion region formed in the N well may be doped with a p-type impurity, and the diffusion region formed in the p-type substrate P-sub may be doped with an n-type impurity.

The third additional cell 813 can extend from the second column Row2 to the fourth column Row4 in the second direction D2. For example, as shown in FIG. 16, the second additional cell 812 can have a length 2H. The third additional cell 813 may include at least two diffusion regions formed in the p-type substrate P-sub of the second column Row2, at least two diffusion regions formed in the N well of the third column Row3, formed in the third column At least two diffusion regions of the p-type substrate P-sub of Row3, and at least one gate electrode.

For example, the diffusion region of the third additional cell 813 in the second column Row2 can be configured to share the diffusion region of the seventh cell 822 and the gate electrode. Further, the diffusion region of the third additional cell 813 in the fourth column Row4 can be configured to share the diffusion region of the tenth cell 825 and the gate electrode. In other words, at least a portion or all of the diffusion regions of the third additional cell 813 can be configured to share the gate electrodes of at least one of the seventh cell 822 and the tenth cell 825.

FIG. 17A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept. The plan view shown in Fig. 17A is similar to the plan view shown in Fig. 10. Therefore, the differences between the two schemas will be mainly explained.

For example, as shown in FIG. 17A, the power gate switching system 1100 can include an upper column, a middle column, and a bottom column.

The upper column may include first power gate cells (P-tab1, 1101, G1, 1102, P) disposed between virtual VDD and VSS (or virtual VSS) and connected to virtual VDD and VSS (or virtual VSS) -tab2), the second power gate cell (1105, G3, 1106) and the third power gate cell (P-tab3, 1103, G2, 1104, P-tab4). In other words, the upper column shows a p-channel metal oxide semi-conductor (PMOS) power supply gate cell connected between virtual VDD and VSS (or virtual VSS). The upper column may further include a plurality of standard cells (Std) disposed between the virtual VDD and VSS (or virtual VSS) and connected to the virtual VDD and VSS (or virtual VSS). The plurality of standard cells (Std) may be disposed between the PMOS power gate cells in the upper column. Each of the plurality of standard cells (Std) may include a PMOS transistor on the N well and an n-channel metal oxide semi-conductor (NMOS) transistor on the P-sub. As shown in Figure 17A, the N-well of the PMOS transistor of each of the plurality of standard cells can be merged with the N-well of the PMOS power gate cell in the upper column. The shape of the merged N well in which the PMOS power supply cells are placed may be different from the shape of the N well in FIG. 10 due to being disposed in the plurality of standard cells between the PMOS power supply gate cells G1, G2, and G3. One of them includes an NMOS transistor on the P-sub.

The bottom column may include first power gate cells (N-tab1, 1107, G4, 1108, N) disposed between virtual VSS and VDD (or virtual VDD) and connected to virtual VSS and VDD (or virtual VDD) -tab2), the second power gate cell (1111, G6, 1112) and the third power gate cell (N-tab3, 1109, G5, 1110, N-tab4). In other words, the bottom column shows the NMOS power supply gate cells connected between virtual VSS and virtual VDD (or VDD). The bottom column may further include a plurality of standard cells (Std) disposed between VDD (or virtual VDD) and virtual VSS and connected to VDD (or virtual VDD) and virtual VSS. The plurality of standard cells (Std) may be disposed between the NMOS power gate cells in the bottom column. Each of the plurality of standard cells (Std) may include a PMOS transistor on the N well and an NMOS transistor on the P-sub. Therefore, the N well of the PMOS transistor of the standard cell disposed between the NMOS power gate cells in the bottom column can be placed on the P-sub in the bottom column. As shown in Figure 17A, the N-well of the PMOS transistor of each of the plurality of standard cells can be combined with the N-well of a plurality of standard cells in the middle column.

The intermediate column may be disposed between a pair of virtual VSS and VDD, between a pair of virtual VDD and VSS or between a pair of virtual VDD and virtual VSS and connected to a pair of virtual VSS and VDD, a pair of virtual VDD and VSS or a pair of virtual VDD and virtual VSS standard cells (Std).

The power gate switching system 1100 can further include a plurality of intermediate columns connected to virtual VSS or virtual VDD. One of the plurality of intermediate columns may be connected to a virtual VSS connected to an NMOS power supply gate cell or may be connected to VSS. The other of the plurality of intermediate columns may be connected to a virtual VDD connected to the PMOS power gate cell or may be connected to VDD. Here, one of the power gate cells G1 to G6 may be extended to at least one of the intermediate columns to provide the virtual VDD node or the virtual VSS node to the at least one of the intermediate columns Multiple standard cells.

FIG. 17B is a cross-sectional view taken along line AA′ shown in FIG. 17A, according to an exemplary embodiment of the inventive concept. The element shown in Fig. 17B corresponds to the element shown in Fig. 12. Therefore, the differences between the two schemas will be mainly explained. For example, Figure 17B shows an N-well on the P-sub that is discontinuous in the D1 direction. The NMOS transistor of the standard cell can be placed on the P-sub between the power supply gate cells G1, G2 and G3.

FIG. 17C is a cross-sectional view taken along line BB' of FIG. 17A, according to an exemplary embodiment of the inventive concept. The element shown in Fig. 17C corresponds to the element shown in Fig. 11. Therefore, the differences between the two schemas will be mainly explained. For example, Figure 17B shows NMOS power supply gate cells connected to VSS and virtual VSS. The N well of the PMOS transistor of the standard cell can be placed between the power gate cells G4, G5 and G6 on the P-sub.

FIG. 18A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept. The plan view shown in Fig. 18A is similar to the plan view shown in Fig. 12. Therefore, the differences between the two schemas will be mainly explained.

For example, as shown in FIG. 18A, the power gate switching system 1200 can include an upper column, a middle column, and a bottom column.

The upper column includes first power gate cells (P-tab1, 1201, G1, 1202, P-) disposed between virtual VDD and virtual VSS (or VSS) and connected to virtual VDD and virtual VSS (or VSS) Tab2), the second power gate cell (1205, G3, 1206) and the third power gate cell (P-tab3, 1203, G2, 1204, P-tab4). In other words, the upper column shows the PMOS power gate cells connected between virtual VDD and virtual VSS (or VSS). The upper column may further include a plurality of standard cells (Std) disposed between the virtual VDD and VSS (or virtual VSS) and connected to the virtual VDD and VSS (or virtual VSS). The plurality of standard cells (Std) may be disposed between the PMOS power gate cells in the upper column. Each of the plurality of standard cells (Std) may include a PMOS transistor on the N well and an NMOS transistor on the P well. As shown in Figure 18A, the N-well of the PMOS transistor of each of the plurality of standard cells in the upper column can be merged with the N-well of the PMOS power gate cell in the upper column. The shape of the merged N well in which the PMOS power supply cells are placed may be different from the shape of the N well in FIG. 12 due to one of a plurality of standard cells disposed between the PMOS power supply gate cells G1, G2, and G3. The NMOS transistor on the P well is included.

The bottom column includes first power gate cells (N-tab1, 1207, G4, 1208, N-) disposed between virtual VSS and VDD (or virtual VDD) and connected to virtual VSS and VDD (or virtual VDD) Tab2), the second power gate cell (1211, G6, 1212) and the third power gate cell (N-tab3, 1209, G5, 1210, N-tab4). In other words, the bottom column shows the NMOS power supply gate cells connected between virtual VSS and virtual VDD (or VDD). The bottom column further includes a plurality of standard cells (Std) disposed between VDD (or virtual VDD) and virtual VSS and connected to VDD (or virtual VDD) and virtual VSS. The plurality of standard cells (Std) may be disposed between the NMOS power gate cells in the bottom column. Each of the plurality of standard cells (Std) may include a PMOS transistor on the N well and an NMOS transistor on the P well. Therefore, the N well of the PMOS transistor of the standard cell disposed between the NMOS power gate cells G4, G5, and G6 in the bottom column can be placed on the P-sub away from the P well in the bottom column. As shown in Figure 18A, the N-well of the PMOS transistor of each of the plurality of standard cells in the bottom column can be merged with the N-well of the plurality of standard cells in the middle column.

The intermediate column may be disposed between a pair of virtual VSS and VDD, between a pair of virtual VDD and VSS or between a pair of virtual VDD and virtual VSS and connected to a pair of virtual VSS and VDD, a pair of virtual VDD and VSS or a pair of virtual VDD and virtual VSS standard cells (Std). The power gate switching system 1200 can further include a plurality of intermediate columns connected to virtual VSS or virtual VDD. One of the plurality of intermediate columns may be connected to a virtual VSS connected to an NMOS power supply gate cell or may be connected to VSS. The other of the plurality of intermediate columns may be connected to a virtual VDD connected to a PMOS power supply gate or may be connected to VDD. Here, one of the power gate cells G1 to G6 may be extended to at least one of the intermediate columns to provide the virtual VDD node or the virtual VSS node to the at least one of the intermediate columns Multiple standard cells.

FIG. 18B is a cross-sectional view taken along line AA′ shown in FIG. 18A, according to an exemplary embodiment of the inventive concept. The element shown in Fig. 18B corresponds to the element shown in Fig. 12. Therefore, the difference between the two drawings will be mainly explained with reference to FIGS. 2 and 12. For example, FIG. 18B shows, in a cross-sectional view, the NMOS transistor of the N well in the D1 direction and one of the standard cells of the PMOS power supply gate cells G1, G2, and G3 on the P-sub. Placed in the P well between the discontinuous N wells. An NMOS transistor of a standard cell can be formed on the P well.

FIG. 18C is a cross-sectional view taken along line BB' of FIG. 18A, according to an exemplary embodiment of the inventive concept. The element shown in Fig. 18C corresponds to the element shown in Fig. 13. Therefore, the difference between the two drawings will be mainly explained with reference to FIGS. 18A and 13. For example, FIG. 18C shows, in a cross-sectional view, the placement of PMOS transistors of one of the P wells and the standard cells that are discontinuous in the D1 direction of the NMOS power supply gate cells G4, G5, and G6 on the P-sub. N well between discontinuous P wells. A PMOS transistor of a standard cell can be formed on the N well.

19 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept.

Specifically, FIG. 19 illustrates a plurality of PMOS power supply gate cells connected to a plurality of metal power supply lines, virtual VDD and VSS (or virtual VSS). Each of the PMOS power supply gate cells can have at least one p tap on both sides and can have at least one n tap on both sides. Referring to FIG. 19, in FIG. 19, the PMOS tap (or tap) is identified as "PT", the NMOS tap (or tap) is identified as "NT", the diffusion break is identified as "DB" and The standard cell identifier is "Std.Cells". Figure 19 further illustrates VSS (or virtual VSS) extending longitudinally along the top and bottom of the columns of PMOS power supply gate cells. Additionally, one of the metal power lines virtual VDD and VSS (or virtual VSS) extends longitudinally through the middle of each column of PMOS power supply gate cells. The distance W_pg2pg can be the minimum distance required between the power cells.

It will be further appreciated that a P well may be present in the standard cell region (e.g., Region I in Figure 19). In addition, the N well may be present in the Region II adjacent to Region I. The N well in Region II can be penetrated by the metal power line virtual VDD. Further, the line disposed between the NMOS taps NT may be the power supply line NVSS to connect the respective NMOS taps NT to each other.

Referring to FIG. 19, the semiconductor device 1300 may include various types of power supply gate cells. For example, a first type of PMOS power thyristor cell can include a p-tap PT on both sides of a PMOS power gate transistor in a PMOS power gate cell. The first type of PMOS power supply gate cell can include an n-tap NT on both ends of the PMOS power supply gate cell. The PMOS power thyristor cell can include one or more PMOS transistors connected in parallel between virtual VDD and virtual VSS (or VSS). The second type of PMOS power thyristor cell may include one or more PMOS transistors connected in parallel between virtual VDD and virtual VSS (or VSS) without including a p-tap PT or on both ends of the PMOS power supply gate cell n tap NT. The number of PMOS transistors can be proportional to the current drive capability of the PMOS power supply gate cells.

The first type of PMOS power thyristor cells may be aligned in a vertical region including a plurality of dummy power supply lines Virtual_V _DD and the second type of PMOS power thyristor cells may be in a vertical region including a plurality of virtual power supply lines Virtual_V _DD Align. The position, type or number of PMOS power gate cells in the floor plan of the semiconductor device 1300 may vary depending on the power source provided by the PMOS power supply gate cells.

According to an exemplary embodiment of the inventive concept, a power gate switching system for efficiently supplying a virtual power source voltage to a region where a large voltage drop of a semiconductor device can occur may be provided.

According to an exemplary embodiment of the inventive concept, the power gate switching system can be implemented by improved area efficiency.

Although the present invention has been particularly shown and described with reference to the exemplary embodiments of the present invention, it should be understood by those of ordinary skill in the art Various changes in form and detail.

100, 200, 300, 400, 500, 1100, 1200‧‧‧ power gate switching system
101, 201, 301, 401, 501‧‧‧ first diffusion zone
102, 202, 302, 402, 502‧‧‧ second diffusion zone
103, 203, 303, 403, 503‧‧‧ third diffusion zone
104, 204, 304, 404, 504‧‧‧ fourth diffusion zone
105, 205, 305, 405, 505‧‧‧ fifth diffusion zone
106, 206, 306, 406, 506‧‧‧ sixth diffusion zone
407, 507‧‧‧ seventh diffusion zone
408, 508‧‧‧ eighth diffusion zone
409, 509‧‧‧ ninth diffusion zone
410, 510‧‧‧ Tenth Diffusion Zone
411, 511‧‧‧ eleventh diffusion zone
412, 512‧‧‧ twelfth diffusion zone
601, 701, 801‧‧‧ first cell
602, 702, 802‧‧‧ second cell
603, 703, 803‧‧‧ third cell
604, 704, 804‧‧‧ fourth cell
605, 705, 805‧‧‧ fifth cell
611, 711, 811‧‧‧ first additional cells
612, 712, 812‧‧‧ second additional cells
613, 713, 813‧‧‧ third additional cells
821‧‧‧ sixth cell
822‧‧‧ seventh cell
823‧‧‧ eighth cell
824‧‧‧ ninth cell
825‧‧‧ tenth cell
1101, 1102, 1103, 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212‧‧ Diffusion zone
1300‧‧‧ semiconductor device
D1‧‧‧ first direction
D2‧‧‧ second direction
D3‧‧‧ third direction
DB‧‧‧Diffusion Interruption
G1‧‧‧first gate electrode
G2‧‧‧second gate electrode
G3‧‧‧third gate electrode
G4‧‧‧fourth gate electrode
G5‧‧‧ fifth gate electrode
G6‧‧‧ sixth gate electrode
Gate_CTRL‧‧‧gate voltage, voltage
N-tab‧‧‧n tap
N-tab1‧‧‧first n tap
N-tab2‧‧‧second n tap
N-tab3‧‧‧ third n tap
N-tab4‧‧‧fourth tap
NT‧‧‧NMOS tap
NVSS‧‧‧Power cord
N-well‧‧‧N well
PMOS‧‧‧P channel metal oxide semiconductor
P-sub‧‧‧p type substrate
P-tab1‧‧‧first p tap
P-tab2‧‧‧second p tap
P-tab3‧‧‧ third p tap
P-tab4‧‧‧4th p tap
PT‧‧‧ PMOS tap
P-well‧‧‧P well
Region I‧‧‧Standard Cell Area
Region II‧‧‧
Row1‧‧‧first column
Row2‧‧‧Second column
Row3‧‧‧ third column
Row4‧‧‧ fourth column
Row5‧‧‧ fifth column
S1, s2, s3, W_pg2pg‧‧‧ distance
Std1, Std2, Std3, Std4, Std5, Std6, STD Cells, Std.cells‧‧‧ standard cells
STI‧‧‧ device isolation layer
Vbias, Vbias2‧‧‧ partial voltage
V _DD ‧‧‧Power supply voltage / power cord
V _SS ‧‧‧ Grounding voltage / grounding wire
Virtual_V _DD ‧‧‧Virtual Power Supply Voltage / Virtual Power Cord
Virtual_V _SS ‧‧‧Virtual Ground Voltage / Virtual Ground Wire

The above and other features of the inventive concept will be more clearly understood from the exemplary embodiments of the invention.

FIG. 1 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

2 is a cross-sectional view taken along line AA' of FIG. 1 according to an exemplary embodiment of the inventive concept.

FIG. 3 is a cross-sectional view taken along line AA' of FIG. 1 according to an exemplary embodiment of the inventive concept.

FIG. 4 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 5 is a cross-sectional view taken along line AA' of FIG. 4, according to an exemplary embodiment of the inventive concept.

FIG. 6 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 7 is a cross-sectional view taken along line BB' of FIG. 6 according to an exemplary embodiment of the inventive concept.

FIG. 8 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 9 is a cross-sectional view taken along line BB' of FIG. 8 according to an exemplary embodiment of the inventive concept.

FIG. 10 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 11 is a cross-sectional view taken along line BB' of FIG. 10, according to an exemplary embodiment of the inventive concept.

FIG. 12 is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 13 is a cross-sectional view taken along line BB' of FIG. 12, according to an exemplary embodiment of the inventive concept.

FIG. 14 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept.

FIG. 15 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept.

FIG. 16 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept.

FIG. 17A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 17B is a cross-sectional view taken along line AA′ shown in FIG. 17A, according to an exemplary embodiment of the inventive concept.

FIG. 17C is a cross-sectional view taken along line BB' of FIG. 17A, according to an exemplary embodiment of the inventive concept.

FIG. 18A is a plan view illustrating a power gate switching system according to an exemplary embodiment of the inventive concept.

FIG. 18B is a cross-sectional view taken along line AA′ shown in FIG. 18A, according to an exemplary embodiment of the inventive concept.

FIG. 18C is a cross-sectional view taken along line BB' of FIG. 18A, according to an exemplary embodiment of the inventive concept.

19 is a plan view illustrating a layout of a semiconductor device applied to a power gate switching system, according to an exemplary embodiment of the inventive concept.

100‧‧‧Power Gate Switching System

101‧‧‧First Diffusion Zone

102‧‧‧Second diffusion zone

103‧‧‧ Third Diffusion Zone

104‧‧‧ fourth diffusion zone

105‧‧‧ Fifth Diffusion Zone

106‧‧‧ sixth diffusion zone

D1‧‧‧ first direction

D2‧‧‧ second direction

D3‧‧‧ third direction

G1‧‧‧first gate electrode

G2‧‧‧second gate electrode

G3‧‧‧third gate electrode

N-well‧‧‧N well

P-sub‧‧‧p type substrate

P-tab1‧‧‧first p tap

P-tab2‧‧‧second p tap

P-tab3‧‧‧ third p tap

P-tab4‧‧‧4th p tap

S1, s2‧‧‧ distance

Virtual_V _DD ‧‧‧Virtual Power Supply Voltage / Virtual Power Cord

Claims (31)

A semiconductor device comprising: a virtual power line extending in a first direction; a n-well extending in the first direction, wherein the virtual power line and the n-well are disposed in a column; the first power gate switch a cell, disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first power gate switch cell and the second power gate switch cell are a first type cell And a third power gate switch cell disposed in the n-well between the first power gate switch cell and the second power gate switch cell, wherein the third power gate switch cell Is a second type of cell that is different from the first type of cell. The semiconductor device of claim 1, wherein the third power gate switch cell is disposed closer to the first power gate switch cell than the second power gate switch cell. The semiconductor device of claim 1, wherein the third power gate switch cell is disposed closer to the second power gate switch cell than the first power gate switch cell. The semiconductor device of claim 1, wherein each of the first type of cells comprises a gate electrode disposed between a pair of diffusion regions and disposed adjacent to one of the diffusion regions Tap. The semiconductor device of claim 4, wherein the tap is a p-tap, and in a column adjacent to the column of the n-well, an n is placed on the same axis as the p-tap Tap, and the n tap is connected to the ground line. The semiconductor device of claim 4, wherein the second type of cell comprises a gate electrode disposed between a pair of diffusion regions, and wherein the second type of cell does not include a tap. The semiconductor device of claim 1, wherein the size of the second type of cell is smaller than the size of each of the first type of cells. The semiconductor device of claim 1, wherein the n well is disposed in a p-type substrate. The semiconductor device according to claim 1, wherein the n well is doped with an n-type impurity. The semiconductor device of claim 1, wherein the first power supply gate cell includes a gate electrode disposed between the first diffusion region and the second diffusion region, and adjacent to the first diffusion region or The first tap disposed in the second diffusion region. The semiconductor device according to claim 10, wherein the first diffusion region and the second diffusion region are doped with a p-type impurity and the first tap is doped with an n-type impurity. The semiconductor device of claim 10, wherein the first tap is connected to the virtual power line, the first diffusion region is connected to a real power line, and the second diffusion region is connected to the virtual power cable. The semiconductor device of claim 12, wherein the third power supply gate cell comprises a gate electrode disposed between the third diffusion region and the fourth diffusion region, and wherein the second type of cell is not A tap is included, and wherein the third diffusion region is connected to the real power line and the fourth diffusion region is connected to the virtual power line. A power gate switching system includes: a first virtual power line extending in a first direction; a first power gate cell connected to the first virtual power line; a second power gate cell connected to the first a virtual power line, wherein the first power gate cell and the second power gate cell respectively comprise at least one tap; and a third power gate cell connected to the first virtual power line and disposed in the Between the first power gate cell and the second power gate cell, wherein the third power gate cell does not include a tap, and wherein the first power gate cell to the third power gate cell The element and the first virtual power line are arranged in the first column. The power gate switching system of claim 14, further comprising: a second virtual power line extending in the first direction; a fourth power gate cell connected to the second virtual power line; And a fifth power gate cell coupled to the second virtual power line, wherein each of the fourth power gate cell and the fifth power gate cell includes at least one tap, wherein the The four power gate cells and the fifth power gate cell and the second virtual power line are arranged in the second column. The power gate switching system of claim 14, wherein the first column comprises a plurality of logic cells disposed between the first power gate cell and the third power gate cell, And a plurality of logic cells disposed between the second power gate cell and the third power gate cell. The power gate switching system of claim 14, wherein the first column comprises: a n-well region disposed on the first side and the second side of the first virtual power line; the first ground line And disposed on the first side of the first virtual power line; and a second ground line disposed on the second side of the first virtual power line. The power gate switching system of claim 17, further comprising: a first p-well region extending in the first direction and disposed on the first side of the first virtual power line Between the first ground line and the n-well region; and a second p-well region extending in the first direction and disposed on the second side of the first virtual power line A second ground line is between the n well region. The power gate switching system of claim 17, wherein the first power gate cell includes a p-tap connected to the first virtual power line and a first n connected to the first ground line Tap. The power gate switching system of claim 19, wherein the first power gate cell comprises a second n tap connected to the second ground line. The power gate switching system of claim 20, wherein the first n tap, the p tap, and the second n tap are sequentially arranged. A power gate switching system includes: a first column including a first virtual power line, a first power gate cell, and a second power gate cell, wherein the first power gate cell includes a first diffusion region and a first gate electrode and at least one tap between the second diffusion regions, wherein the second power gate cell includes a second gate electrode disposed between the third diffusion region and the fourth diffusion region and the second power source The gate cell does not include a tap; and the second column includes a second virtual power line, a third power gate cell, and a fourth power gate cell, wherein the third power gate cell includes a fifth diffusion region a third gate electrode between the sixth diffusion region and at least one tap, and the fourth power gate cell includes a fourth gate electrode disposed between the seventh diffusion region and the eighth diffusion region and the fourth power source The gate cell does not include a tap, and wherein the fourth power gate cell is coupled to the second power gate cell. The power gate switching system of claim 22, wherein the first column and the second column extend in a first direction, and a gate control line and a gate of the second power gate cell The gate control line of the fourth power gate cell extends in a second direction that is substantially perpendicular to the first direction. The power gate switching system of claim 22, wherein the first power gate cell includes a device isolation layer adjacent to the at least one tap, and the second power gate cell includes adjacent to the first A device isolation layer for each of the triple diffusion region and the fourth diffusion region. The power gate switching system of claim 22, further comprising: a third column comprising a third virtual power line, a fifth power gate cell, and a sixth power gate cell, wherein the fifth power gate The cell includes a fifth gate electrode and at least one tap disposed between the ninth diffusion region and the tenth diffusion region, and the sixth power gate cell includes the eleventh diffusion region and the twelfth diffusion region And a sixth gate electrode and the sixth power gate cell does not include a tap, and wherein the sixth power gate cell is coupled to the fourth power gate cell. The power gate switching system of claim 25, wherein the first power gate cell and the fifth power gate cell are disposed in a first row, and the second power gate cell, The fourth power gate cell and the sixth power gate cell are disposed in the second row. The power gate switching system of claim 26, wherein the first column to the third column extend in a first direction, and the first row and the second row are substantially vertical Extending in a second direction of the first direction. The power gate switching system of claim 22, wherein a width of the channel of the first power gate cell in the column direction is greater than a channel of the second power gate cell in the column direction width. The power gate switching system of claim 22, wherein the size of the first power gate cell is greater than the size of the second power gate cell. The power gate switching system of claim 25, wherein the gate control signal line of the second power gate cell, the gate control signal line of the fourth power gate cell, and the sixth A gate control signal line of the power gate cell extends across the first virtual power line, the second virtual power line, and the third virtual power line. The power gate switching system of claim 22, wherein the first power gate cell extends across the first virtual power line.