CN111128959A - Groove guard ring structure and forming method thereof - Google Patents
Groove guard ring structure and forming method thereof Download PDFInfo
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- CN111128959A CN111128959A CN201811289747.8A CN201811289747A CN111128959A CN 111128959 A CN111128959 A CN 111128959A CN 201811289747 A CN201811289747 A CN 201811289747A CN 111128959 A CN111128959 A CN 111128959A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
A groove guard ring structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a plurality of chip areas, and a protection ring area is arranged between adjacent chip areas; forming a groove in the protective ring area, and forming a word line structure in the groove, wherein the upper surface of the word line structure is not higher than the upper surface of the substrate; the method comprises the steps of arranging a plurality of metal interconnection layers on a substrate in a laminated mode, arranging an inter-metal dielectric layer between every two adjacent metal interconnection layers, forming a plurality of first connecting pieces in the inter-metal dielectric layer to be connected with the adjacent metal interconnection layers, arranging an interlayer dielectric layer between the metal interconnection layer at the bottommost layer and the substrate, arranging a plurality of second connecting pieces in the interlayer dielectric layer, and connecting the metal interconnection layer at the bottommost layer with a word line structure through at least one of the second connecting pieces so as to form a groove protection ring structure. The groove guard ring structure formed by the method can reduce leakage paths of word line channels and can prevent floating node potential from floating.
Description
Technical Field
The invention relates to a semiconductor memory manufacturing process. And more particularly to memory device architecture and flow.
Background
The main chip protection ring is an important protection barrier for wafer packaging and scribing. The chip protection ring can prevent damage to the wafer caused by external moisture and stress, so that good product reliability is realized. Conventional guard rings are formed from a simple silicon substrate with metal interconnect layers and vias on it, similar to a "wall" structure. However, the chip protection ring in the prior art has the problems of electric leakage path, potential floating of nodes and the like, and a better solution is needed.
Disclosure of Invention
The invention provides a groove guard ring structure and a forming method thereof, which can reduce the electric leakage of the guard ring structure and avoid the potential floating of a node.
The invention provides a method for forming a groove guard ring structure, which comprises the following steps: a substrate is provided, the substrate is provided with a plurality of chip areas, and a protection ring area is arranged between adjacent chip areas. A trench is formed in the guard ring region, a word line structure is formed in the trench, and an upper surface of the word line structure is not higher than an upper surface of the substrate. The method comprises the steps of arranging a plurality of metal interconnection layers on a substrate in a laminated mode, arranging an inter-metal dielectric layer between every two adjacent metal interconnection layers, forming a first connecting piece in the inter-metal dielectric layer to be connected with the adjacent metal interconnection layers, arranging an interlayer dielectric layer between the metal interconnection layer at the bottommost layer and the substrate, arranging a second connecting piece in the interlayer dielectric layer, and enabling the metal interconnection layer at the bottommost layer to be connected with a word line structure, so that a groove guard ring structure is formed.
In some embodiments of the present invention, the word line structure within the trench in the guard ring region is electrically grounded.
In some embodiments of the present invention, the trench guard ring structure includes a plurality of trenches and a plurality of word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the number of the trenches are 2 or a multiple of 2.
In some embodiments of the present invention, the lowermost metal interconnect layer is connected to at least one of the plurality of word line structures through a second connection.
In some embodiments of the present invention, corresponding identical or similar components including a trench, a word line structure, an interlayer dielectric layer, a second connection, a metal interconnect layer, an inter-metal dielectric layer, and a first connection are formed in a chip region at the same time that respective components in a trench guard ring structure are formed in a guard ring region.
In some embodiments of the present invention, the metal interconnection layer, the first connection member, the second connection member, and the word line structure in the guard ring region are not connected to corresponding same or similar components in the chip region.
The present invention also provides a trench guard ring structure, comprising: the device comprises a substrate, a groove, a word line structure, a plurality of metal interconnection layers, an inter-metal dielectric layer and an interlayer dielectric layer. The substrate has a plurality of chip regions and guard ring regions between adjacent chip regions. The trench is located in the guard ring region. The word line structure is located in the trench. The metal interconnection layers are positioned on the substrate and arranged in a laminated mode. The inter-metal dielectric layer is positioned between the adjacent metal interconnection layers, wherein the inter-metal dielectric layer is provided with a first connecting piece, and the first connecting piece is connected with the upper and lower adjacent metal interconnection layers. The interlayer dielectric layer is positioned between the bottommost metal interconnection layer and the substrate, wherein the interlayer dielectric layer is provided with a second connecting piece, and the second connecting piece is connected with the bottommost metal interconnection layer and the word line structure.
In some embodiments of the present invention, the word line structure within the trench in the guard ring region is electrically grounded.
In some embodiments of the present invention, the trench guard ring structure includes a plurality of trenches and a plurality of word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the number of the trenches are multiples of 2 or 2.
In some embodiments of the present invention, the lowermost metal interconnect layer is connected to at least one of the plurality of word line structures through a second connection.
In some embodiments of the present invention, the chip region includes respective components that are the same as or similar to those in the trench guard ring region, and the components include a trench, a word line structure, an interlayer dielectric layer, a second connection, a metal interconnection layer, an inter-metal dielectric layer, and a first connection.
In some embodiments of the present invention, the metal interconnection layer, the first connection member, the second connection member, and the word line structure in the guard ring region are not connected to corresponding same or similar components in the chip region.
The invention has the beneficial effects that two word line structures are arranged in the substrate in the protective ring area, and the potential of the word line structures is grounded so as to reduce the electric leakage path of the protective ring structure. And at least one of the word line structures is connected to the metal interconnection layer through a connecting piece, so that the node potential can be prevented from floating.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art substrate including a trench guard ring structure;
FIG. 2 is a schematic cross-sectional view of a substrate including a trench guard ring structure according to the present invention.
Fig. 3 is a schematic top view of a substrate of the present invention.
Detailed Description
The following is a description of embodiments of the trench guard structure and the trench guard structure forming method disclosed in the present invention by specific examples, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure in the present specification. The invention is capable of other and different embodiments and its several details are capable of modification and various other changes, which can be made in various details within the specification and without departing from the spirit and scope of the invention. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
See fig. 1 and 2 and fig. 3. FIG. 1 is a schematic cross-sectional view of a prior art substrate including a trench guard ring structure; FIG. 2 is a schematic cross-sectional view of a substrate including a trench guard ring structure according to the present invention; fig. 3 is a schematic top view of a substrate of the present invention. The invention provides a method for forming a groove guard ring structure, which comprises the following steps: first, a substrate W having a plurality of chip regions C is provided. For example, referring to fig. 2 and fig. 3, a cross-sectional view of the substrate including the trench guard ring structure shown in fig. 2 is a cross-sectional view of a boundary portion of a chip region C. In this portion, a guard ring region P is provided. As shown in fig. 3, each chip region C has a guard ring region P at its periphery. In other words, the guard ring region P is provided between adjacent chip regions. The substrate of this portion is a silicon substrate, and a semiconductor material such as gallium nitride, silicon carbide, or silicon germanium may be used. Ion implantation is carried out on the substrate, and III group element ions (such as boron ions) are doped to form a P-type well region or V group element ions (such as arsenic ions) are doped to form an N-type well region; group v ions (e.g., arsenic ions) are doped in the P-type well region to form an N + region or group iii ions (e.g., boron ions) are doped in the N-type well region to form a P + region. Shallow Trench Isolation (STI) is arranged at the edge of the P-type well region and the edge of the N-type well region; a plurality of trenches are formed in the P-well region under the guard ring region, the trenches themselves forming a trench ring. Word Line structures (WL) are respectively formed in the grooves, the potential of each Word Line structure is grounded, and the upper surface of each Word Line structure is not higher than that of the substrate. The number of trenches is the same as the number of word line structures. That is, a word line structure word line potential ground is formed in each trench to terminate the electrical leakage path of the guard ring structure. The word line structure filling material may be a metal material such as tungsten, titanium, or titanium nitride. A plurality of metal interconnection layers are arranged above the protective ring area on the substrate, wherein four metal interconnection layers are taken as examples and are respectively M0, M1, M2 and M3. An interlayer dielectric layer is arranged between the metal interconnection layer M0 at the bottommost layer and the substrate, one or more trench channels are arranged in the interlayer dielectric layer, and the trench channels are filled to form a second connecting piece so that the metal interconnection layer M0 is connected with the word line structure WL. If there are a plurality of second connectors, at least one of the second connectors is connected to at least one word line structure, and the other second connectors may be connected to the N + region or the P + region on the substrate. An inter-metal dielectric layer is arranged between the metal interconnection layers, a groove channel is formed in the inter-metal dielectric layer, and first connecting pieces VIA0, VIA1 and VIA2 are formed in the groove channel and connected with the adjacent metal interconnection layers. For example, as shown in fig. 2, VIA0 is formed between M0 and M1, VIA1 is formed between M1 and M2, VIA2 … … is formed between M2 and M3, and so on. Similarly to the above, the number of trench channels in the inter-metal dielectric layer may be one or more. These first connecting members form a "wall" like structure in the longitudinal direction, which together with the word line structure constitutes a trench guard structure.
In this embodiment, the metal interconnection layer, the first connection member, and the second connection member may be made of a metal material such as copper, aluminum, or tungsten; the intermetal dielectric layer and the interlayer dielectric layer may be made of insulating dielectric material such as silicon dioxide and silicon nitride.
Specifically, in this embodiment, the metal interconnection layer is four layers. In other embodiments, there may be fewer or more metal interconnect layers, and correspondingly, there may be fewer or more intermetal dielectric layers. For example, the metal interconnection layer may be 2 layers, and the corresponding intermetal dielectric layer may be 1 layer. The skilled person can select it according to the actual need. In this embodiment, the number of trenches and the number of word line structures are both 2. In other embodiments, more trenches and more word line structures are possible. In some preferred embodiments, the number of trenches and the number of word line structures is a multiple of 2. In this embodiment, the trench channels between the upper metal interconnect layer and the lower metal interconnect layer adjacent to each metal interconnect layer are arranged in a staggered manner. As shown in fig. 2, for example, the first connection VIA2 between the metal interconnect layer M2 and the metal interconnect layer M3 on the upper side thereof and the first connection VIA1 between the metal interconnect layer M2 and the metal interconnect layer M1 on the lower side thereof are always offset in position in the longitudinal direction. However, in other embodiments, the first connectors may be non-staggered and aligned in longitudinal position. The specific case can be selected by those skilled in the art according to the actual situation, and the invention is not limited to this. In this embodiment, there are two first connecting members between the metal interconnection layers. That is, there are only two first connectors in each IMD layer. In other embodiments, there may be one or more than two first connecting elements in each intermetal dielectric layer, and those skilled in the art can select them according to actual needs. In this embodiment, the number of the second connectors is three, one of which is connected to the word line structure WL, and the rest of which is connected to the other portion of the substrate. In other embodiments, the number of the second connectors may be smaller or larger, but at least one connects the word line structure WL and the lowest metal interconnect layer M0. Also, there may be a plurality of second connections connecting the lowermost metal interconnection layer M0 and the word line structure WL. The skilled person can select the desired one according to the actual need. In addition, the trench and the word line structure are formed in the P-well, but in other embodiments of the present invention, they may also be formed in the N-well, and those skilled in the art can select them according to the actual requirement, which is not limited to the present invention.
In some embodiments, the above method forms respective components in the trench guard ring structure in the guard ring region, and forms corresponding same or similar components in the chip region, including: the device comprises a groove, a word line structure, an interlayer dielectric layer, a second connecting piece, a metal interconnection layer, an inter-metal dielectric layer and a first connecting piece. And the grooves, the word line structures, the second connecting pieces, the metal interconnection layers and the first connecting pieces in the chip areas are not connected with corresponding same or similar components in the guard ring areas.
In the present invention, the terms "same or similar" in the above-mentioned methods specifically refer to the same or similar process steps, shapes, structures, materials or functions. Specifically, for example, when a trench is formed in the guard ring region, the same or similar trench is also formed in the chip region, and when a word line structure is filled in the trench of the guard ring region, the same or similar word line structure is also filled in the trench of the chip region, the process steps, shapes, structures, and materials of the two are the same or similar, but functionally, the former serves as a part of the guard ring structure to prevent electrical leakage and avoid potential floating of a node, and the latter serves as a gate in a transistor device to perform a switching function. For another example, while the first connection element is formed by filling a metal material into a trench formed in the inter-metal dielectric layer in the protection ring region by using a Dual Damascene process (Dual Damascene), a hole is formed in the inter-metal dielectric layer in the chip region by using the same Dual Damascene process and a similar component is formed by filling the same metal material into the trench, and both the metal material and the metal material are structurally the same and are connected to the upper and lower adjacent metal interconnection layers, but in terms of shape, the former is formed by filling the trench with the metal material, and the latter is formed by filling the hole with the metal material.
According to the above method, the present invention further provides a trench guard ring structure, which comprises a substrate, a trench, a word line structure, a plurality of metal interconnection layers, an inter-metal dielectric layer, and an interlayer dielectric layer. The substrate W has a plurality of chip regions C thereon. For example, referring to fig. 2 and fig. 3, a cross-sectional view of the substrate including the trench guard ring structure shown in fig. 2 is a cross-sectional view of a boundary portion of a chip region C. In this portion, a guard ring region P is provided. As shown in fig. 3, each chip region C has a guard ring region P at its periphery. In other words, the guard circle region P is provided between the adjacent chip regions C. The substrate of this portion is a silicon substrate, and a semiconductor material such as gallium nitride, silicon carbide, or silicon germanium may be used. Ion implantation is carried out on the substrate, and III group element ions (such as boron ions) are doped to form a P-type well region or V group element ions (such as arsenic ions) are doped to form an N-type well region; group v ions (e.g., arsenic ions) are doped in the P-type well region to form an N + region or group iii ions (e.g., boron ions) are doped in the N-type well region to form a P + region. The edge of the P-type well region and the edge of the N-type well region are Shallow Trench Isolations (STI); a plurality of trenches are formed in the P-type well region of the guard ring region, the trenches themselves forming a trench ring. The trenches are respectively provided with a word line structure (WL) which is grounded, and the upper surface of the word line structure is not higher than the upper surface of the substrate. The number of trenches is the same as the number of word line structures. That is, a word line structure word line potential ground is formed in each trench to terminate the electrical leakage path of the guard ring structure. The word line structure filling material may be a metal material such as tungsten, titanium, or titanium nitride. A plurality of metal interconnection layers are arranged above the protective ring area on the substrate, and four metal interconnection layers are taken as an example and are respectively M0, M1, M2 and M3. An interlayer dielectric layer is arranged between the metal interconnection layer M0 at the bottommost layer and the substrate, one or more trench channels are formed in the interlayer dielectric layer, and second connecting pieces are filled in the trench channels to connect the metal interconnection layer M0 with a word line structure (WL). If there are a plurality of second connectors, at least one of the second connectors is connected to at least one word line structure, and the other second connectors may be connected to the N + region or the P + region on the substrate. An inter-metal dielectric layer is arranged between the metal interconnection layers, a groove channel is arranged in the inter-metal dielectric layer, and first connecting pieces VIA0, VIA1 and VIA2 are filled in the groove channel and are connected with the adjacent metal interconnection layers. For example, as shown in fig. 2, VIA0 is formed between M0 and M1, VIA1 is formed between M1 and M2, VIA2 … … is formed between M2 and M3, and so on. Similarly to the above, the number of trench channels in the inter-metal dielectric layer may be one or more. These first connecting members form a "wall" like structure in the longitudinal direction, which together with the word line structure constitutes a trench guard structure.
In this embodiment, the metal interconnection layer, the first connection member, and the second connection member may be made of a metal material such as copper, aluminum, or tungsten; the intermetal dielectric layer and the interlayer dielectric layer may be made of insulating dielectric material such as silicon dioxide and silicon nitride.
Specifically, in this embodiment, the metal interconnection layer is four layers. In other embodiments, there may be fewer or more metal interconnect layers, and correspondingly, there may be fewer or more intermetal dielectric layers. For example, the metal interconnection layer may be 2 layers, and the corresponding intermetal dielectric layer may be 1 layer. The skilled person can select it according to the actual need. In this embodiment, the number of trenches and the number of word line structures are both 2. In other embodiments, more trenches and more word line structures are possible. In some preferred embodiments, the number of trenches and the number of word line structures is a multiple of 2. In this embodiment, the connection trench channels between the upper metal interconnection layer and the lower metal interconnection layer adjacent to each metal interconnection layer are arranged in a staggered manner. As shown in fig. 2, for example, the first connection VIA2 between the metal interconnect layer M2 and the metal interconnect layer M3 on the upper side thereof and the first connection VIA1 between the metal interconnect layer M2 and the metal interconnect layer M1 on the lower side thereof are always offset in position in the longitudinal direction. However, in other embodiments, the first connectors may be non-staggered and aligned in longitudinal position. The specific case can be selected by those skilled in the art according to the actual situation, and the invention is not limited to this. In addition, in this embodiment, two first connection members are provided between the metal interconnection layers. That is, there are only two first connectors in each IMD layer. In other embodiments, there may be one or more than two first connecting elements in each intermetal dielectric layer, and those skilled in the art can select them according to actual needs. In this embodiment, the number of the second connectors is three, one of which is connected to the word line structure (WL) and the rest of which is connected to the other portion of the substrate. In other embodiments, the number of the second connectors may be smaller or larger, but there is at least one metal interconnection layer M0 connecting the word line structure (WL) and the bottom layer. Also, there may be a plurality of second connections connecting the lowermost metal interconnection layer M0 and the word line structure (WL). The skilled person can select the desired one according to the actual need. In addition, the trench and the word line structure are formed in the P-well, but in other embodiments of the present invention, they may also be formed in the N-well, and those skilled in the art can select them according to the actual requirement, which is not limited to the present invention.
In some embodiments, the substrate also forms the same component corresponding to the groove guard ring region in the chip region, and the component includes: the device comprises a groove, a word line structure, an interlayer dielectric layer, a second connecting piece, a metal interconnection layer, an inter-metal dielectric layer and a first connecting piece. And the grooves, the word line structures, the interlayer dielectric layers, the second connecting pieces, the metal interconnection layers, the inter-metal dielectric layers and the first connecting pieces in the chip areas are not connected with corresponding same or similar components in the guard ring areas.
In the present invention, the terms "same or similar" as used above specifically refer to the same or similar process steps, shapes, structures, materials or functions. Specifically, for example, if the trench is formed in the guard ring region, the same or similar trench is also formed in the chip region, the word line structure is filled in the trench in the guard ring region, and the same or similar word line structure is also filled in the trench in the chip region, and the process steps, shapes, structures, and materials of the two are the same or similar, but functionally, the former serves as a part of the guard ring structure to prevent electrical leakage and prevent potential floating of a node, and the latter serves as a gate in a transistor device to perform a switching function. For example, while the trench is formed in the inter-metal dielectric layer in the protection ring region by using a dual damascene process and the metal material is filled in the trench to form the first connection element, the same dual damascene process is used in the inter-metal dielectric layer in the chip region to form the hole and the same metal material is filled in the hole to form a component similar to the first connection element, and both the metal interconnect layers are structurally the same and are connected with the upper and lower adjacent metal interconnect layers, but in terms of shape, the former is formed by filling the trench and the latter is formed by filling the hole.
As described above, the present invention has an advantageous effect in that, by providing two word lines on the substrate under the protection ring region, the word line potential is grounded to reduce the leakage path of the word line channel. One of the two word lines is connected to the metal interconnection layer through a connecting piece, so that node potential floating can be avoided. The word line channel has less leakage and the node potential floats less than if the word line were not typically provided in the prior art.
The above embodiments of the trench guard and the method for forming the trench guard provided by the present invention are described in detail, and it is believed that those skilled in the art can understand the technical solution and the operation principle of the present invention. However, the above is only a preferred embodiment of the present invention and does not limit the present invention. The technical solution provided by the present invention can be modified appropriately according to the actual needs by those skilled in the art, and modifications and equivalent changes can be made without departing from the scope of the present invention as claimed. The scope of the invention is to be determined by the following claims.
Claims (12)
1. A method for forming a trench guard ring structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of chip areas, and a protection ring area is arranged between the adjacent chip areas;
forming a groove in the guard ring area, and forming a word line structure in the groove, wherein the upper surface of the word line structure is not higher than the upper surface of the substrate;
the method comprises the steps of stacking a plurality of metal interconnection layers on a substrate, arranging an inter-metal dielectric layer between the adjacent metal interconnection layers, forming a first connecting piece in the inter-metal dielectric layer to be connected with the adjacent metal interconnection layers, arranging an interlayer dielectric layer between the metal interconnection layer at the bottommost layer and the substrate, and arranging a second connecting piece in the interlayer dielectric layer to connect the metal interconnection layer at the bottommost layer and the word line structure, so that a groove guard ring structure is formed.
2. The method of forming a trench guard ring structure as claimed in claim 1, wherein said wordline structure within said trench in said guard ring region is electrically grounded.
3. The method for forming a trench guard ring structure as claimed in claim 1, wherein the trench guard ring structure comprises a plurality of trenches and a plurality of word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the trenches is 2 or a multiple of 2.
4. The method of forming a trench guard ring structure as claimed in claim 3, wherein the metal interconnect layer of the lowermost layer is connected to at least one of the plurality of word line structures through the second connection.
5. The method of claim 1, wherein the forming of each component of the trench guard ring structure in the guard ring region is performed simultaneously with forming the corresponding same or similar component in a chip region, the component including the trench, the word line structure, the interlayer dielectric layer, the second connection, the metal interconnection layer, the inter-metal dielectric layer, and the first connection.
6. The method of forming a trench guard ring structure as claimed in claim 5, wherein said metal interconnect layer, said first connection, said second connection and said word line structure in said guard ring region are not connected to corresponding same or similar components in said chip region.
7. A trench guard ring structure, comprising:
the chip protection structure comprises a substrate, a plurality of chip regions and a protection ring region, wherein the chip regions are adjacent to each other;
a trench located in the guard ring region;
a word line structure located in the trench;
the metal interconnection layers are positioned on the substrate and are arranged in a laminated manner;
the intermetallic dielectric layer is positioned between the adjacent metal interconnection layers, and a first connecting piece is arranged in the intermetallic dielectric layer and is connected with the upper and lower adjacent metal interconnection layers;
and the interlayer dielectric layer is positioned between the metal interconnection layer at the bottommost layer and the substrate, wherein the interlayer dielectric layer is provided with a second connecting piece, and the second connecting piece is connected with the metal interconnection layer at the bottommost layer and the word line structure.
8. The trench guard ring structure of claim 7 wherein said wordline structure within said trench in said guard ring region is electrically grounded.
9. The trench guard ring structure of claim 7, wherein the trench guard ring structure comprises a plurality of the trenches and a plurality of the word line structures, the number of the trenches is the same as the number of the word line structures, and the number of the word lines and the trenches is a multiple of 2 or 2.
10. The trench guard ring structure of claim 9 wherein a lowermost of said metal interconnect layers and at least one of said plurality of wordline structures are connected by said second connection.
11. The trench guard ring structure of claim 7, said chip region containing respective components that are the same as or similar to corresponding ones in said trench guard ring region, said components including said trench, said wordline structure, said interlayer dielectric layer, said second connection, said metal interconnect layer, said intermetal dielectric layer, and said first connection.
12. The trench guard ring structure of claim 7, wherein said metal interconnect layer, said first connection, said second connection, and said wordline structure in said guard ring region are not connected to corresponding same or similar components in said chip region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811289747.8A CN111128959A (en) | 2018-10-31 | 2018-10-31 | Groove guard ring structure and forming method thereof |
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| CN201811289747.8A CN111128959A (en) | 2018-10-31 | 2018-10-31 | Groove guard ring structure and forming method thereof |
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|---|---|---|---|
| CN201811289747.8A Pending CN111128959A (en) | 2018-10-31 | 2018-10-31 | Groove guard ring structure and forming method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN111128959A (en) |
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2018
- 2018-10-31 CN CN201811289747.8A patent/CN111128959A/en active Pending
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