TWI754340B - Chip - Google Patents

Abstract

A chip includes a substrate, functional blocks and at least one first insulating layer. The substrate has circuit areas and a first non-circuit area, wherein the first non-circuit area is disposed between the circuit areas. The functional blocks are respectively disposed on the circuit areas of the substrate. A functional block includes a thin film transistor, and the thin film transistor has a source/drain, a gate and a semiconductor pattern. The at least one first insulating layer is disposed between at least two of the source /drain, the gate and the semiconductor pattern of the thin film transistor. The at least one first insulating layer has first through holes and solid portions. The first through holes and the solid portions of the at least one first insulating layer are alternately arranged to define a reference track. In particular, at least one portion of the reference track is located on the first non-circuit area of the substrate.

Description

wafer

The present invention relates to an electronic component, and in particular to a wafer.

Near Field Communication (NFC) technology allows two electronic devices equipped with antenna functions to communicate wirelessly within a distance of a few centimeters. This contactless data exchange mechanism has the advantages of high response speed, high security, and convenience. Therefore, in recent years, many products on the market have integrated near-field wireless communication functions, such as e-ticket cards (for example: EasyCards). etc.), electronic payment devices (e.g. smart phones, smart watches, etc.), etc. The user only needs to bring the object with the near-field wireless communication tag (NFC tag) close to the card reader (NFC reader), and then the authentication and data exchange can be completed in a short time, providing users with a more convenient lifestyle.

A near field wireless communication tag (NFC tag) includes an antenna and a wireless communication chip electrically connected to the antenna. In order to easily install the NFC tag on electronic products of various shapes, the NFC tag and its wireless communication chip need to be flexible. That is to say, the wireless communication chip needs to use a flexible substrate to carry the wireless communication circuit. However, when the flexible substrate is excessively bent, the wireless communication circuit is easily broken, thereby causing the wireless communication chip to fail.

The invention provides a wafer which is resistant to bending.

A chip of the present invention includes a substrate, a plurality of functional blocks and at least one first insulating layer. The substrate has a plurality of circuit areas and a first non-circuit area, wherein the first non-circuit area is arranged between the plurality of circuit areas. A plurality of functional blocks are respectively disposed on a plurality of circuit areas of the substrate. A functional block includes a thin film transistor, and the thin film transistor has a source-drain electrode, a gate electrode and a semiconductor pattern. At least one first insulating layer is disposed between at least two of the source-drain electrode, the gate electrode and the semiconductor pattern of the thin film transistor. At least one first insulating layer has a plurality of first through holes and a plurality of solid portions. A plurality of first through holes and a plurality of solid portions of at least one first insulating layer are alternately arranged to define a reference track. In particular, at least a portion of the reference trace is located on the first non-circuit area of the substrate.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specific amount of measurement-related error (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic top view of a chip 10 according to an embodiment of the present invention.

FIG. 2 is an enlarged schematic view of a part R1 of the wafer 10 according to an embodiment of the present invention. FIG. 2 corresponds to the part R1 of FIG. 1 .

FIG. 3 shows a cross-section of a portion R1 of the wafer 10 according to an embodiment of the present invention. Fig. 3 corresponds to section line A-A' of Fig. 2 .

FIG. 4 is an enlarged schematic view of another part R2 of the wafer 10 according to an embodiment of the present invention. FIG. 4 corresponds to the part R2 of FIG. 1 .

FIG. 5 shows a cross-section of another part R1 of the wafer 10 according to an embodiment of the present invention. Fig. 5 corresponds to the section line B-B' in Fig. 4 .

1, 2 and 4 omit the illustration of the second insulating layer 180 and the recess 162a.

Referring to FIG. 1 , the chip 10 includes a substrate 110 and a plurality of function blocks FB. Referring to FIGS. 1 , 2 and 3 , the substrate 110 has a plurality of circuit areas 112 , and a plurality of functional blocks FB are respectively disposed on the plurality of circuit areas 112 (marked in FIG. 3 ) of the substrate 110 . The substrate 110 also has a first non-circuit area 114 a (shown in FIG. 3 ) disposed between the plurality of circuit areas 112 . Referring to FIGS. 1 , 4 and 5 , in this embodiment, the substrate 110 may further have a second non-circuit area 114 b (marked in FIGS. 3 and 5 ) located in the plurality of circuit areas 112 and the plurality of circuit areas 112 outside the first non-wire area 114a between.

In this embodiment, the substrate 110 is flexible; that is, in this embodiment, the wafer 10 may be a flexible wafer, but the invention is not limited thereto.

For example, in this embodiment, the material of the substrate 110 may include organic polymers, such as: polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate Ethylene terephthalate (PET), polycarbonate (PC), polyether sulfone (PES), polyarylate, other suitable materials, or at least two of the foregoing materials combination, but the present invention is not limited thereto.

Please refer to FIG. 1 , each functional block FB has a specific function. For example, in this embodiment, a plurality of functional blocks FB can form a wireless communication circuit. Specifically, in this embodiment, the plurality of functional blocks FB may include a load modulator M, a rectifier Rec, a standard format (ISO format) circuit ISO, and a frequency division (CLK Division) Circuit CLK, Data select circuit DS, Buffer BF, Encoder enc, Cycle Redundancy Check CRC, Counter CNT, Decoder )dec and memory ROM. However, the present invention is not limited thereto, and in other embodiments, according to different functions of the chip 10 , the plurality of functional blocks FB may also include other types of functional circuits.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 , in addition, in this embodiment, the chip 10 may further include a plurality of pads P (drawn in FIG. 1 ) disposed on the second non-circuit area 114 b of the substrate 110 (marked at 2), and is electrically connected to a plurality of functional blocks FB. For example, in the present embodiment, the plurality of pads P can be used as differential signal input pairs of the wireless communication circuit, and are suitable for engaging with the antenna 20 (shown in FIG. 3 ).

Please refer to FIG. 1 , FIG. 2 and FIG. 3 , at least one functional block FB includes at least one thin film transistor T. As shown in FIG. The thin film transistor T has a source-drain electrode 172 , a source-drain electrode 174 , a gate electrode 150 and a semiconductor pattern 130 , wherein the source-drain electrode 172 and the source-drain electrode 174 are respectively electrically connected to two different regions of the semiconductor pattern 130 .

It should be noted that, in this embodiment, the standard format circuit ISO and the encoding circuit enc include a plurality of thin film transistors T as an example for description. However, the present invention is not limited thereto, and in other embodiments, the functional block FB including the thin film transistor T may also be other types of functional circuits.

2 , 3 , 4 and 5 , the chip 10 further includes at least one first insulating layer 140 , 160 disposed on at least two of the source-drain electrodes 172 , the gate electrodes 150 and the semiconductor patterns 130 of the thin film transistor T between. At least one of the first insulating layers 140 and 160 has a plurality of first through holes 164 and a plurality of solid portions 162 , wherein the plurality of first through holes 164 and the plurality of solid portions 162 are alternately arranged and define a reference track K. A vertical projection of the connecting lines of the plurality of first through holes 164 and the plurality of solid portions 162 on the substrate 110 coincides with a vertical projection of the reference track K on the substrate 110 .

In particular, at least a portion of the reference track K is located on the first non-circuit area 114a of the substrate 110 . That is to say, at least a part of the vertical projections of the first through holes 164 of the at least one first insulating layer 140 and 160 on the substrate 110 are located in the vertical projections of the adjacent multi-functional blocks FB on the substrate 110 . between projections.

Referring to FIGS. 1 to 5 , in this embodiment, the reference track K is not only located on the first non-circuit area 114a between the multi-functional blocks FB, but also can selectively extend to the first non-circuit area 114a outside the multi-functional blocks FB. on the second non-circuit area 114b. In this embodiment, a plurality of multi-functional blocks FB can be electrically connected to each other by using the first wires L1 disposed on the first non-circuit area 114a, and at least one functional block FB can be disposed in the second non-circuit area 114b by using The second wire L2 on the upper part is electrically connected to at least one pad P, and the reference track K does not cross the first wire L1 and the second wire L2.

It is worth mentioning that the reference track K defined by the plurality of first through holes 164 can be regarded as a pseudo-tear line of the wafer 10 . When the wafer 10 is bent, the stress is easily transmitted along the pseudo-tear line (ie, the reference track K), and is released on the pseudo-tear line (ie, the reference track K), resulting in generation along the pseudo-tear line (ie, the reference track K) 's cracks. When the stress is sufficiently released on the quasi-tear line (ie, the reference track K) between the multiple functional blocks FB, the multiple functional blocks FB will not be easily damaged. Therefore, even if the wafer 10 is excessively bent and cracked, the wafer 10 can still operate normally.

Referring to FIG. 2 and FIG. 3 , at least one first insulating layer 140 and 160 is disposed between at least two of the source-drain electrode 172 , the gate electrode 150 and the semiconductor pattern 130 of the thin film transistor T. As shown in FIG. For example, in this embodiment, the at least one first insulating layer 140 and 160 may include a first insulating layer 140 and a first insulating layer 160 , wherein the first insulating layer 160 is disposed on the source and drain electrodes 172 of the thin film transistor T Between the gate electrode 150 and the gate electrode 150 , the first insulating layer 140 is disposed between the gate electrode 150 of the thin film transistor T and the semiconductor pattern 130 .

In this embodiment, the first insulating layer 160 may have a plurality of first through holes 164 defining the reference track K, and the first insulating layer 140 may not have through holes overlapping the first through holes 164 . That is to say, in this embodiment, the reference track K may be selectively defined by the plurality of first through holes 164 of the first insulating layer 160 . However, the present invention is not limited thereto. In another embodiment, the reference track K may also be defined by a plurality of through holes (not shown) in the first insulating layer 140 , and the first insulating layer 160 may not include the first insulating layer 160 . The plurality of through holes of the layer 140 are overlapped; in another embodiment, the reference track K can also be composed of a plurality of through holes (not shown) of the first insulating layer 140 and the first insulating layer 160 The plurality of first through holes 164 are collectively defined, wherein the plurality of through holes (not shown) of the first insulating layer 140 are respectively overlapped with the plurality of first through holes 164 of the first insulating layer 160 .

The materials of the first insulating layers 140 and 160 may be inorganic materials (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), organic materials, or combinations thereof. For example, in this embodiment, the first insulating layer 140 may be a stacked layer of silicon oxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ), and the material of the first insulating layer 160 may be silicon oxide (SiO 2 ). _x ) and a stacked layer of silicon nitride (SiN _x ), but the invention is not limited thereto.

In this embodiment, the source-drain electrodes 172 and/or the source-drain electrodes 174 of the thin film transistor T are made of metal materials, such as a stacked layer of titanium (Ti)/aluminum (Al)/titanium (Ti). The invention is not limited to this, and according to other embodiments, the source-drain electrodes 172 and/or the source-drain electrodes 174 of the thin film transistor T may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, metals oxynitride of materials, or stacked layers of metallic materials and other conductive materials.

In this embodiment, the gate electrode 150 of the thin film transistor T is made of, for example, a metal material, such as molybdenum (Mo). However, the present invention is not limited thereto. According to other embodiments, the gate electrode 150 of the thin film transistor T may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, Or a stacked layer of metal materials and other conductive materials.

In this embodiment, the semiconductor pattern 130 of the thin film transistor T is, for example, polysilicon (poly-Si). However, the present invention is not limited thereto, and in other embodiments, the semiconductor pattern 130 may also be amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (eg, indium zinc oxide, indium gallium zinc oxides, or other suitable materials, or a combination of the above), or other suitable materials, or contain dopants in the above materials, or a combination of the above.

In addition, in this embodiment, the gate 150 of the thin film transistor T can be selectively located above the semiconductor pattern 130; that is, the thin film transistor T of this embodiment can be selectively a top-gate type thin film transistor (top gate TFT); but the present invention is not limited thereto, in other embodiments, the thin film transistor T may also be a bottom gate type thin film transistor (bottom gate TFT) or other types of thin film transistors.

Referring to FIGS. 2 , 3 , 4 and 5 , in this embodiment, the wafer 10 may optionally include a buffer layer 120 disposed between the thin film transistor T and the substrate 110 . Referring to FIGS. 4 and 5 , the buffer layer 120 has a plurality of first through holes 124 and a plurality of solid portions 122 , and the plurality of first through holes 124 of the buffer layer 120 are respectively overlapped with at least one of the first insulating layers 140 and 160 . The plurality of first through holes 164 and the plurality of solid portions 122 of the buffer layer 120 are respectively overlapped with the plurality of solid portions 162 of the at least one first insulating layer 140 and 160 . A vertical projection of the connection lines of the plurality of first through holes 124 and the plurality of solid portions 122 of the buffer layer 120 on the substrate 110 coincides with a vertical projection of the reference track K on the substrate 110 . That is to say, in this embodiment, the reference track K can be selectively defined by the plurality of first through holes 164 of the first insulating layer 160 and the plurality of first through holes 124 of the buffer layer 120 , but the present invention Not limited to this.

For example, in this embodiment, the material of the buffer layer 120 may include a plurality of polycrystalline silicon nitrides (poly-SiN _x ) and a plurality of polycrystalline silicon oxides (poly-SiO _x ) stacked alternately. However, the present invention is not limited thereto, and in other embodiments, the buffer layer 120 may also include other materials.

Referring to FIGS. 2 , 3 , 4 and 5 , the wafer 10 further includes a second insulating layer 180 . The second insulating layer 180 is disposed on the thin film transistor T, and the thin film transistor T is disposed between the second insulating layer 180 and the substrate 110 . The material of the second insulating layer 180 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof. For example, in this embodiment, the material of the second insulating layer 180 may be silicon nitride (SiN _x ), but the invention is not limited thereto.

It is worth noting that the second insulating layer 180 is disposed on at least one of the first insulating layers 140 and 160 , and the second insulating layer 180 has a plurality of first through holes overlapping at least one of the first insulating layers 140 and 160 respectively. The plurality of first recesses 182 of 164 . A vertical projection of the connecting lines of the plurality of first recesses 182 of the second insulating layer 180 on the substrate 110 coincides with a vertical projection of the reference track K on the substrate 110 . That is, the to-be-tear line (ie, the reference track K) of the wafer 10 can be jointly defined by the plurality of first through holes 164 of the first insulating layer 160 and the plurality of first recesses 182 of the second insulating layer 180 .

FIG. 6 shows the stress distribution on a first recess 182 of the second insulating layer 180 according to an embodiment of the present invention.

Please refer to FIG. 2 , FIG. 3 and FIG. 6 . The data in FIG. 6 proves that when the wafer 10 is bent, the stress is concentrated at the corners 182 c of the plurality of first recesses 182 of the second insulating layer 180 , and cracks are easily The first recess 182 is formed at the corner 182c. That is to say, when the wafer 10 is bent, it is more likely that cracks will be generated along the plurality of first recesses 182 (or the reference track K) of the second insulating layer 180 . When the stress causes cracks on the corners 182c of the first recesses 182 of the second insulating layer 180 (or, in other words, on the reference track K) and is fully released, the functional block FB is not easily damaged. Therefore, even if the wafer 10 is excessively bent and cracked, the wafer 10 can still operate normally.

Referring to FIG. 1 , FIG. 2 and FIG. 3 , in this embodiment, the conductive adhesive ACP can be disposed between the antenna 20 and the second insulating layer 180 of the chip 10 , wherein the plurality of pads P of the chip 10 are passed through the conductive adhesive ACP In electrical connection with the antenna 20 , at least part of the conductive adhesive ACP is located in the plurality of first recesses 182 of the second insulating layer 180 of the chip 10 .

It is worth mentioning that the plurality of first recesses 182 in the second insulating layer 180 are not only used to define the path for stress relief (ie, the reference track K), the arrangement of the plurality of first recesses 182 can also increase the number of chips 10 and conductive adhesives. The contact area of the ACP; thereby, the bonding force between the chip 10 and the antenna 20 can be increased, so that the antenna 20 and the chip 10 are not easily separated. In addition, the stress on the chip 10 can also be transmitted upward to the antenna 20 through the conductive adhesive ACP; thereby, the stress is dispersed to the antenna 20 with better bending tolerance, which makes the functional block FB of the chip 10 more difficult cracked.

Referring to FIGS. 4 and 5 , in this embodiment, the plurality of solid portions 162 of at least one of the first insulating layers 140 and 160 can selectively have a plurality of recesses 162 a respectively, and the plurality of solid portions 122 of the buffer layer 120 can be The second insulating layer 180 can selectively have a plurality of second recesses 184 respectively, wherein the plurality of second recesses 184 of the second insulating layer 180 respectively overlap at least one first insulating layer 140 The plurality of recesses 162 a of the plurality of solid portions 162 of the buffer layer 160 and the plurality of recesses 122 a of the plurality of solid portions 122 of the buffer layer 120 .

In this embodiment, since the second recess 184 of the second insulating layer 180 overlaps the recess 162 a of the solid portion 162 of at least one of the first insulating layers 140 and 160 and the recess 122 a of the solid portion 122 of the buffer layer 120 , the first The first recesses 182 of the two insulating layers 180 overlap at least one of the first through holes 164 of the first insulating layers 140 and 160 and the first through holes 124 of the buffer layer 120 . Therefore, the second recesses 184 of the second insulating layer 180 The depth D2 of the second insulating layer 180 is smaller than the depth D1 of the first recess 182 of the second insulating layer 180 .

For example, in this embodiment, the recesses 162a of the solid portion 162 of the at least one first insulating layer 140 and 160 and the recesses 122a of the solid portion 122 of the buffer layer 120 may use a half tone or a grayscale tone ( gray tone) mask, but the present invention is not limited to this.

Referring to FIGS. 5 and 6 , similar to the first recesses 182 of the second insulating layer 180 in FIG. 6 , when the wafer 10 is bent, the stress will be concentrated on the corners of the plurality of second recesses 184 of the second insulating layer 180 184c , and cracks are easily generated from the corners 184c of the second recesses 184 . That is, when the wafer 10 is bent, cracks may be generated along the plurality of first recesses 182 of the second insulating layer 180 and may also be generated along the plurality of second recesses 184 of the second insulating layer 180 . In this way, in addition to the plurality of first recesses 182 of the second insulating layer 180 , the stress relief locations also include a plurality of second recesses 184 of the second insulating layer 180 . The arrangement of the plurality of second recesses 184 helps to increase the stress relief, thereby protecting the functional block FB (marked in FIG. 1 ) of the wafer 10 .

In addition, in this embodiment, in addition to the plurality of first recesses 182 of the second insulating layer 180 , part of the conductive adhesive ACP may also be located in the plurality of second recesses 184 of the second insulating layer 180 of the wafer 10 . That is to say, the arrangement of the plurality of second recesses 184 can not only increase the stress relief, but also increase the contact area between the conductive adhesive ACP and the chip 10 , thereby further increasing the bonding force between the chip 10 and the antenna 20 .

Please refer to FIG. 1 , FIG. 4 and FIG. 5 . In this embodiment, at least one first insulating layer 140 and 160 further has at least one second through hole 146 and 166 , and at least one first insulating layer 140 and 160 has at least one first through hole 146 and 166 . The two through-holes 146 and 166 are located at the end of the reference track K; the second insulating layer 180 also has a through-hole 186 , and the through-hole 186 of the second insulating layer 180 overlaps with at least one second insulating layer 140 and 160 . Through holes 146 , 166 ; the buffer layer 120 has a second through hole 126 , and the second through hole 126 of the buffer layer 120 overlaps at least one second through hole 146 , 166 of the at least one first insulating layer 140 , 160 .

In this embodiment, the area of the second through holes 146 and 166 of the at least one first insulating layer 140 and 160 is larger than the area of the first through holes 164 of the at least one first insulating layer 140 and 160 . The area of the through hole 186 of the at least one second insulating layer 180 is larger than the area of the first through hole 164 of the at least one first insulating layer 140 and 160 .

The at least one second through hole 146 and 166 of the at least one first insulating layer 140 and 160 , the through hole 186 of the second insulating layer 180 and the second through hole 126 of the buffer layer 120 may form a stress transfer stop cell O. The stress transfer stop pool O is set at the end of the reference trajectory K (or, in other words, the pseudo-tear line). All non-conductive layers of the wafer 10 (eg, the buffer layer 120 , the first insulating layers 140 , 160 and the second insulating layer 180 ) are hollowed out at the location where the stress transfer stop cell O is located. Therefore, along the reference track K ( In other words, the stress transmitted by the quasi-tear line) will be stopped in the stress transmission stop pool O, so that the functional block FB and/or other important structures of the wafer 10 are not easily damaged.

In this embodiment, the reference trace K may extend to the second non-circuit area 114b of the substrate 110 , and the at least one second through hole 146 and 166 of the at least one first insulating layer 140 and 160 and the second insulating layer 180 The through holes 186 and the second through holes 126 of the buffer layer 120 are located on the second non-circuit area 114b. That is to say, in this embodiment, the stress transfer stop pool O is disposed on the second non-circuit area 114b outside the plurality of functional blocks FB. For example, in this embodiment, the stress transfer stop pool O may be disposed beside the pads P of the wafer 10 , but the present invention is not limited thereto. In other embodiments, the stress transfer stop pool O can also be arranged at other places where the line density is lower.

In this embodiment, since the stress transfer stop pool O is disposed beside the pads P of the wafer 10, the conductive adhesive ACP formed on the pads P will overflow into the stress transfer stop pool O, and at least part of the conductive adhesive ACP will overflow into the stress transfer stop pool O. The at least one second through hole 146 and 166 of the at least one first insulating layer 140 and 160 , the through hole 186 of the second insulating layer 180 and the second through hole 126 of the buffer layer 120 may be located. However, the present invention is not limited to this. In another embodiment, if the amount of the conductive adhesive ACP formed on the pads P is small and/or the stress transfer stop cell O is far away from the pads P, the conductive adhesive ACP may not be will be filled and/or set in the stress transfer cessation cell O.

To sum up, a chip according to an embodiment of the present invention includes a substrate, a plurality of functional blocks disposed on a plurality of circuit regions of the substrate, and at least one first insulating layer. At least one functional block includes at least one thin film transistor. At least the thin film transistor has a source-drain electrode, a gate electrode and a semiconductor pattern, and at least one first insulating layer is disposed between at least two of the source-drain electrode, the gate electrode and the semiconductor pattern of the thin film transistor. At least one first insulating layer has a plurality of first through holes and a plurality of solid portions. A plurality of first through holes and a plurality of solid portions of at least one first insulating layer are alternately arranged to define a reference track. In particular, at least a portion of the reference trace is located on the first non-wire area between the plurality of functional blocks.

The reference track defined by the plurality of first through holes of the at least one first insulating layer can be regarded as a pseudo-tear line of the wafer. When the wafer is bent, the stress is easily transmitted along the pseudo-tear line, and is released on the pseudo-tear line, resulting in cracks along the pseudo-tear line. When the stress is fully released on the quasi-tear line between the multiple functional blocks, it is not easy to cause damage to the multiple functional blocks. In this way, even if the wafer is excessively bent and cracks are generated along the torn line, the wafer can still operate normally.

10: Wafer 20: Antenna 110: Substrate 112: Line area 114a: First non-wire area 114b: Second non-wire area 120: Buffer layer 122, 162: Entity 122a, 162a: depression 124, 164: The first through hole 126, 146, 166: second through hole 130: Semiconductor pattern 140, 160: the first insulating layer 150: gate 172, 174: source and drain 180: Second insulating layer 182: The first depression 182c, 184c: Corner 184: Second Sag 186: Through hole A-A', B-B': section line ACP: Conductive Adhesive BF: Buffer circuit CLK: Frequency divider circuit CRC: Cyclic Redundancy Check Circuit CNT: counting circuit D1, D2: depth DS: Data Selection Circuit dec: decoding circuit enc: encoding circuit FB: functional block ISO: standard format circuit K: Reference track L1: the first wire L2: Second wire M: Load modulation circuit O: Stress transfer stop cell P: Pad R1, R2: local Rec: Rectifier circuit ROM: memory T: thin film transistor

FIG. 1 is a schematic top view of a chip 10 according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of a part R1 of the wafer 10 according to an embodiment of the present invention. FIG. 3 shows a cross-section of a portion R1 of the wafer 10 according to an embodiment of the present invention. FIG. 4 is an enlarged schematic view of another part R2 of the wafer 10 according to an embodiment of the present invention. FIG. 5 shows a cross-section of another part R1 of the wafer 10 according to an embodiment of the present invention. FIG. 6 shows the stress distribution on a first recess 182 of the second insulating layer 180 according to an embodiment of the present invention.

10: Wafer

110: Substrate

114a: First non-wire area

114b: Second non-wire area

164: The first through hole

BF: Buffer circuit

CLK: Frequency divider circuit

CRC: Cyclic Redundancy Check Circuit

CNT: counting circuit

DS: Data Selection Circuit

dec: decoding circuit

enc: encoding circuit

FB: functional block

ISO: standard format circuit

K: Reference track

L1: the first wire

L2: Second wire

M: Load modulation circuit

O: Stress transfer stop cell

P: Pad

R1, R2: local

Rec: Rectifier circuit

ROM: memory

Claims (13)

A wafer comprising: a substrate having a plurality of circuit areas and a first non-circuit area, wherein the first non-circuit area is disposed between the circuit areas; a plurality of functional blocks respectively disposed on the circuit regions of the substrate, wherein one of the functional blocks includes a thin film transistor, and the thin film transistor has a source-drain electrode, a gate electrode and a semiconductor pattern; At least one first insulating layer is disposed between at least two of the source-drain electrode, the gate electrode and the semiconductor pattern of the thin film transistor, wherein the at least one first insulating layer has a plurality of first through holes and a plurality of a solid portion, the first through holes and the solid portions are alternately arranged and define a reference track, at least a part of the reference track is located on the first non-circuit area of the substrate; and a second insulating layer disposed on the thin film transistor and having a plurality of first recesses, wherein the first recesses of the second insulating layer respectively overlap the first through holes of the at least one first insulating layer hole. The wafer according to claim 1, further comprising: a buffer layer disposed between the thin film transistor and the substrate, wherein the buffer layer has a plurality of first through holes and a plurality of solid parts, and the first through holes of the buffer layer respectively overlap the at least one first through hole The first through holes of an insulating layer, and the solid portions of the buffer layer are respectively overlapped with the solid portions of the at least one first insulating layer. The chip of claim 1, wherein a conductive adhesive is disposed between an antenna and the second insulating layer of the chip, and at least part of the conductive adhesive is located in the first recesses of the second insulating layer of the chip middle. The wafer of claim 1, wherein the solid portions of the at least one first insulating layer respectively have a plurality of recesses, the second insulating layer has a plurality of second recesses, and the first insulating layers of the second insulating layer have a plurality of recesses respectively. The two recesses respectively overlap the recesses of the solid portions of the at least one first insulating layer. The wafer according to claim 4, further comprising: a buffer layer disposed between the thin film transistor and the substrate, wherein the buffer layer has a plurality of first through holes and a plurality of solid portions, and the first through holes of the buffer layer overlap the at least one first through hole The first through holes of the insulating layer, the solid portions of the buffer layer are respectively overlapped with the solid portions of the at least one first insulating layer, the solid portions of the buffer layer respectively have a plurality of recesses, and the The recesses of the solid portions of the at least one first insulating layer overlap the recesses of the solid portions of the buffer layer, respectively. The chip of claim 4, wherein a conductive adhesive is disposed between an antenna and the second insulating layer of the chip, and at least part of the conductive adhesive is located in the second recesses of the second insulating layer of the chip middle. The wafer of claim 4, wherein the depth of the second recess in one of the second insulating layers is smaller than the depth of the first recess in one of the second insulating layers. The wafer of claim 1, wherein the at least one first insulating layer further has at least one second through hole, and the at least one second through hole of the at least one first insulating layer is located at the end of the reference track; the first The two insulating layers also have through holes, and the through holes of the second insulating layer overlap the at least one second through hole of the at least one first insulating layer. The wafer according to claim 8, further comprising: a buffer layer disposed between the thin film transistor and the substrate, wherein the buffer layer has a second through hole, and the second through hole of the buffer layer overlaps the second through hole of the at least one first insulating layer Through hole. The chip of claim 8, wherein a conductive adhesive is disposed between an antenna and the second insulating layer of the chip, and at least part of the conductive adhesive is located in the through hole and the at least one first insulating layer of the second insulating layer. in the at least one second through hole of an insulating layer. The wafer of claim 8, wherein an area of the at least one second through hole of the at least one first insulating layer is larger than an area of the first through hole of the at least one first insulating layer. The wafer of claim 8, wherein the area of the through hole in the at least one second insulating layer is larger than the area of the first through hole in the at least one first insulating layer. The chip of claim 8, wherein the substrate further has a second non-circuit area, the second non-circuit area is located outside the circuit areas and the first non-circuit area, and the reference trace also extends to the substrate On the second non-circuit area, the at least one second through hole of the at least one first insulating layer and the through hole of the second insulating layer are located on the second non-circuit area of the substrate.

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