TWI754340B - Chip - Google Patents
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- TWI754340B TWI754340B TW109126326A TW109126326A TWI754340B TW I754340 B TWI754340 B TW I754340B TW 109126326 A TW109126326 A TW 109126326A TW 109126326 A TW109126326 A TW 109126326A TW I754340 B TWI754340 B TW I754340B
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Abstract
Description
本發明是有關於一種電子元件,且特別是有關於一種晶片。The present invention relates to an electronic component, and in particular to a wafer.
近場無線通訊技術(Near Field Communication;NFC)可讓配置天線功能的兩個電子裝置在相隔幾公分的距離內進行無線通訊。此種非接觸式資料交換機制具有高反應速度、高安全性、便利性等優勢,因此,近年來市面上已有許多產品整合有近場無線通訊功能,像是電子票卡(例如:悠遊卡等)、電子支付裝置(例如:智慧型手機、智慧型手錶等)等。使用者只需將具有近場無線通訊標籤(NFC tag)的物體與讀卡機(NFC reader)靠近,便能在短時間內完成身分驗證與數據交換,提供使用者更加便捷地生活方式。Near Field Communication (NFC) technology allows two electronic devices equipped with antenna functions to communicate wirelessly within a distance of a few centimeters. This contactless data exchange mechanism has the advantages of high response speed, high security, and convenience. Therefore, in recent years, many products on the market have integrated near-field wireless communication functions, such as e-ticket cards (for example: EasyCards). etc.), electronic payment devices (e.g. smart phones, smart watches, etc.), etc. The user only needs to bring the object with the near-field wireless communication tag (NFC tag) close to the card reader (NFC reader), and then the authentication and data exchange can be completed in a short time, providing users with a more convenient lifestyle.
近場無線通訊標籤(NFC tag)包括天線及與天線電性連接的無線通訊晶片。為使近場無線通訊標籤(NFC tag)易裝設於各種外型的電子產品上,近場無線通訊標籤(NFC tag)及其無線通訊晶片需可撓。也就是說,無線通訊晶片需使用可撓基板承載無線通訊電路。然而,當可撓基板被過度彎折時,無線通訊電路易裂損,進而導致無線通訊晶片失效。A near field wireless communication tag (NFC tag) includes an antenna and a wireless communication chip electrically connected to the antenna. In order to easily install the NFC tag on electronic products of various shapes, the NFC tag and its wireless communication chip need to be flexible. That is to say, the wireless communication chip needs to use a flexible substrate to carry the wireless communication circuit. However, when the flexible substrate is excessively bent, the wireless communication circuit is easily broken, thereby causing the wireless communication chip to fail.
本發明提供一種晶片,耐彎折。The invention provides a wafer which is resistant to bending.
本發明的一種晶片包括基板、多個功能區塊及至少一第一絕緣層。基板具有多個線路區及第一非線路區,其中第一非線路區設置於多個線路區之間。多個功能區塊分別設置於基板的多個線路區上。一功能區塊包括一薄膜電晶體,且薄膜電晶體具有源汲極、閘極及半導體圖案。至少一第一絕緣層設置於薄膜電晶體的源汲極、閘極及半導體圖案的至少二者之間。至少一第一絕緣層具有多個第一貫孔及多個實體部。至少一第一絕緣層的多個第一貫孔及多個實體部交替排列,以定義一參考軌跡。特別是,參考軌跡的至少一部分位於基板的第一非線路區上。A chip of the present invention includes a substrate, a plurality of functional blocks and at least one first insulating layer. The substrate has a plurality of circuit areas and a first non-circuit area, wherein the first non-circuit area is arranged between the plurality of circuit areas. A plurality of functional blocks are respectively disposed on a plurality of circuit areas of the substrate. A functional block includes a thin film transistor, and the thin film transistor has a source-drain electrode, a gate electrode and a semiconductor pattern. At least one first insulating layer is disposed between at least two of the source-drain electrode, the gate electrode and the semiconductor pattern of the thin film transistor. At least one first insulating layer has a plurality of first through holes and a plurality of solid portions. A plurality of first through holes and a plurality of solid portions of at least one first insulating layer are alternately arranged to define a reference track. In particular, at least a portion of the reference trace is located on the first non-circuit area of the substrate.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”可以是二元件間存在其它元件。It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specific amount of measurement-related error (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.
圖1為本發明一實施例之晶片10的上視示意圖。FIG. 1 is a schematic top view of a
圖2為本發明一實施例之晶片10之局部R1的放大示意圖。圖2對應圖1的局部R1。FIG. 2 is an enlarged schematic view of a part R1 of the
圖3示出本發明一實施例之晶片10之局部R1的剖面。圖3對應圖2的剖線A-A’。FIG. 3 shows a cross-section of a portion R1 of the
圖4為本發明一實施例之晶片10之另一局部R2的放大示意圖。圖4對應圖1的局部R2。FIG. 4 is an enlarged schematic view of another part R2 of the
圖5示出本發明一實施例之晶片10之另一局部R1的剖面。圖5對應圖4的剖線B-B’。FIG. 5 shows a cross-section of another part R1 of the
圖1、圖2及圖4省略第二絕緣層180及凹陷162a的繪示。1, 2 and 4 omit the illustration of the second
請參照圖1,晶片10包括基板110及多個功能區塊(Function Block)FB。請參照圖1、圖2及圖3,基板110具有多個線路區112,而多個功能區塊FB分別設置於基板110的多個線路區112(標示於圖3)上。基板110還具有第一非線路區114a(標示於圖3),設置於多個線路區112之間。請參照圖1、圖4及圖5,在本實施例中,基板110還可具有第二非線路區114b(標示於圖3及圖5),位於多個線路區112和多個線路區112之間的第一非線路區114a之外。Referring to FIG. 1 , the
在本實施例中,基板110具有可撓性;也就是說,在本實施例中,晶片10可以是可撓式晶片,但本發明不以此為限。In this embodiment, the
舉例而言,在本實施例中,基板110的材料可包括有機聚合物,例如:聚醯亞胺(polyimide;PI)、聚萘二甲酸乙醇酯(polyethylene naphthalate;PEN)、聚對苯二甲酸乙二酯(polyethylene terephthalate;PET)、聚碳酸酯(polycarbonates;PC)、聚醚碸(polyether sulfone;PES)、聚芳基酸酯(polyarylate)、其它合適的材料、或前述至少二種材料的組合,但本發明不以此為限。For example, in this embodiment, the material of the
請參照圖1,每一功能區塊FB具有一特定功能。舉例而言,在本實施例中,多個功能區塊FB可組成一無線通訊電路。具體而言,在本實施例中,多個功能區塊FB可包括負載調制電路(Load modulator)M、整流電路(Rectifier)Rec、標準格式化(ISO format)電路ISO、分頻(CLK Division)電路CLK、資料選擇(Data select)電路DS、緩衝電路(Buffer)BF、編碼電路(Encoder)enc、循環冗餘校驗(Cycle Redundancy Check)電路CRC、計數電路(Counter)CNT、解碼電路(Decoder)dec和記憶體ROM。然而,本發明不限於此,在其它實施例中,根據晶片10的功能不同,多個功能區塊FB也可包括其它種類的功能電路。Please refer to FIG. 1 , each functional block FB has a specific function. For example, in this embodiment, a plurality of functional blocks FB can form a wireless communication circuit. Specifically, in this embodiment, the plurality of functional blocks FB may include a load modulator M, a rectifier Rec, a standard format (ISO format) circuit ISO, and a frequency division (CLK Division) Circuit CLK, Data select circuit DS, Buffer BF, Encoder enc, Cycle Redundancy Check CRC, Counter CNT, Decoder )dec and memory ROM. However, the present invention is not limited thereto, and in other embodiments, according to different functions of the
請參照圖1、圖2及圖3,此外,在本實施例中,晶片10還可包括多個接墊P(繪於圖1),設置於基板110的第二非線路區114b(標示於圖2)上,且與多個功能區塊FB電性連接。舉例而言,在本實施例中,多個接墊P可做為無線通訊電路的差動訊號輸入對來使用,且適於與天線20(繪於圖3)接合。Please refer to FIG. 1 , FIG. 2 and FIG. 3 , in addition, in this embodiment, the
請參照圖1、圖2及圖3,至少一功能區塊FB包括至少一薄膜電晶體T。薄膜電晶體T具有一源汲極172、一源汲極174、一閘極150及一半導體圖案130,其中源汲極172及源汲極174分別與半導體圖案130的不同兩區電性連接。Please refer to FIG. 1 , FIG. 2 and FIG. 3 , at least one functional block FB includes at least one thin film transistor T. As shown in FIG. The thin film transistor T has a source-
需說明的是,在本實施例中,是以標準格式化電路ISO及編碼電路enc包括多個薄膜電晶體T為例說明。然而,本發明不限於此,在其它實施例中,包括薄膜電晶體T的功能區塊FB也可以是其它種類的功能電路。It should be noted that, in this embodiment, the standard format circuit ISO and the encoding circuit enc include a plurality of thin film transistors T as an example for description. However, the present invention is not limited thereto, and in other embodiments, the functional block FB including the thin film transistor T may also be other types of functional circuits.
請參照圖2、圖3、圖4及圖5,晶片10還包括至少一第一絕緣層140、160,設置於薄膜電晶體T的源汲極172、閘極150及半導體圖案130的至少二者之間。至少一第一絕緣層140、160具有多個第一貫孔164及多個實體部162,其中多個第一貫孔164及多個實體部162交替排列且定義一參考軌跡K。多個第一貫孔164及多個實體部162之連線於基板110上的一垂直投影與參考軌跡K於基板110上的一垂直投影重合。2 , 3 , 4 and 5 , the
特別是,參考軌跡K的至少一部分位於基板110的第一非線路區114a上。也就是說,至少一第一絕緣層140、160之多個第一貫孔164於基板110上的多個垂直投影的至少一部分位於相鄰之多功能區塊FB於基板110上的多個垂直投影之間。In particular, at least a portion of the reference track K is located on the first
請參照圖1至圖5,在本實施例中,參考軌跡K除了位於多功能區塊FB之間的第一非線路區114a上,還可選擇性地延伸至多功能區塊FB之外的第二非線路區114b上。在本實施例中,多個多功能區塊FB可利用設置於第一非線路區114a上的第一導線L1彼此電性連接,至少一功能區塊FB可利用設置於第二非線路區114b上的第二導線L2電性連接到至少一接墊P,而參考軌跡K不會跨越第一導線L1及第二導線L2。Referring to FIGS. 1 to 5 , in this embodiment, the reference track K is not only located on the first
值得一提的是,由多個第一貫孔164定義的參考軌跡K可視為晶片10的擬撕線。當晶片10被彎折時,應力容易沿著擬撕線(即參考軌跡K)傳遞,而在擬撕線(即參考軌跡K)上釋放,造成沿著擬撕線(即參考軌跡K)產生的裂痕。當應力在位在多個功能區塊FB之間的擬撕線(即參考軌跡K)上充分釋放後,便不易造成多個功能區塊FB的裂損。藉此,即便晶片10被過度彎折而產生裂痕,晶片10仍可正常運作。It is worth mentioning that the reference track K defined by the plurality of first through
請參照圖2及圖3,至少一第一絕緣層140、160設置於薄膜電晶體T的源汲極172、閘極150及半導體圖案130的至少二者之間。舉例而言,在本實施例中,至少一第一絕緣層140、160可包括第一絕緣層140及第一絕緣層160,其中第一絕緣層160設置於薄膜電晶體T之源汲極172與閘極150之間,且第一絕緣層140設置於薄膜電晶體T的閘極150與半導體圖案130之間。Referring to FIG. 2 and FIG. 3 , at least one first insulating
在本實施例中,第一絕緣層160可具有定義參考軌跡K的多個第一貫孔164,而第一絕緣層140可不具有重疊於第一貫孔164的貫孔。也就是說,在本實施例中,參考軌跡K可選擇性地由第一絕緣層160的多個第一貫孔164來定義。然而,本發明不限於此,在另一實施例中,參考軌跡K也可由第一絕緣層140的多個貫孔(未繪示)來定義,而第一絕緣層160可不包括與第一絕緣層140之所述多個貫孔重疊的多個貫孔;在又一實施例中,參考軌跡K也可由第一絕緣層140的多個貫孔(未繪示)及第一絕緣層160的多個第一貫孔164共同來定義,其中第一絕緣層140的多個貫孔(未繪示)分別重疊於第一絕緣層160的多個第一貫孔164。In this embodiment, the first insulating
第一絕緣層140、160的材料可以是無機材料(例如:氧化矽、氮化矽、氮氧化矽、或上述至少二種材料的堆疊層)、有機材料或上述之組合。舉例而言,在本實施例中,第一絕緣層140可以是氧化矽(SiO2
)及氮化矽(Si3
N4
)的堆疊層,第一絕緣層160的材料可以是氧化矽(SiOx
)及氮化矽(SiNx
)的堆疊層,但本發明不以此為限。The materials of the first insulating
在本實施例中,薄膜電晶體T的源汲極172及/或源汲極174例如是使用金屬材料,例如:鈦(Ti)/鋁(Al)/鈦(Ti)的堆疊層;但本發明不限於此,根據其他實施例,薄膜電晶體T的源汲極172及/或源汲極174也可以使用其他導電材料,例如:合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。In this embodiment, the source-
在本實施例中,薄膜電晶體T的閘極150例如是使用金屬材料,例如:鉬(Mo)。但本發明不限於此,根據其他實施例,薄膜電晶體T的閘極150也可以使用其他導電材料,例如:合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。In this embodiment, the
在本實施例中,薄膜電晶體T的半導體圖案130例如是多晶矽(poly-Si)。然而,本發明不限於此,在其它實施例中,半導體圖案130也可以是非晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如:銦鋅氧化物、銦鎵鋅氧化物、或是其它合適的材料、或上述之組合)、或其它合適的材料、或含有摻雜物(dopant)於上述材料中、或上述之組合。In this embodiment, the
此外,在本實施例中,薄膜電晶體T的閘極150可選擇性地位於半導體圖案130上方;也就是說,本實施例的薄膜電晶體T可選擇性地是頂部閘極型薄膜電晶體(top gate TFT);但本發明不限於此,在其它實施例中,薄膜電晶體T也可以是底部閘極型薄膜電晶體(bottom gate TFT)或其它型式的薄膜電晶體。In addition, in this embodiment, the
請參照圖2、圖3、圖4及圖5,在本實施例中,晶片10還可選擇性地包括緩衝層120,設置於薄膜電晶體T與基板110之間。請參照圖4及圖5,緩衝層120具有多個第一貫孔124及多個實體部122,緩衝層120的多個第一貫孔124分別重疊於至少一第一絕緣層140、160的多個第一貫孔164,且緩衝層120的多個實體部122分別重疊於至少一第一絕緣層140、160的多個實體部162。緩衝層120之多個第一貫孔124及多個實體部122之連線於基板110上的一垂直投影與參考軌跡K於基板110上的一垂直投影重合。也就是說,在本實施例中,參考軌跡K可選擇性地由第一絕緣層160的多個第一貫孔164及緩衝層120的多個第一貫孔124來共同定義,但本發明不以此為限。Referring to FIGS. 2 , 3 , 4 and 5 , in this embodiment, the
舉例而言,在本實施例中,緩衝層120的材料可包括交替堆疊的多個多晶氮化矽(poly-SiNx
)及多個多晶氧化矽(poly-SiOx
)。然而,本發明不以此為限,在其它實施例中,緩衝層120也可包括其它材料。For example, in this embodiment, the material of the
請參照圖2、圖3、圖4及圖5,晶片10還包括第二絕緣層180。第二絕緣層180設置於薄膜電晶體T上,且薄膜電晶體T設置於第二絕緣層180與基板110之間。第二絕緣層180的材料可以是無機材料(例如:氧化矽、氮化矽、氮氧化矽、或上述至少二種材料的堆疊層)、有機材料或上述之組合。舉例而言,在本實施例中,第二絕緣層180的材料可以是氮化矽(SiNx
),但本發明不以此為限。Referring to FIGS. 2 , 3 , 4 and 5 , the
值得注意的是,第二絕緣層180是設置於至少一第一絕緣層140、160上,而第二絕緣層180具有分別重疊於至少一第一絕緣層140、160之多個第一貫孔164的多個第一凹陷182。第二絕緣層180之多個第一凹陷182的連線在基板110上的一垂直投影與參考軌跡K在基板110上的一垂直投影重合。也就是說,晶片10的擬撕線(即參考軌跡K)可由第一絕緣層160的多個第一貫孔164及第二絕緣層180的多個第一凹陷182來共同定義。It is worth noting that the second insulating
圖6示出於本發明一實施例之第二絕緣層180之一第一凹陷182上的應力分佈狀況。FIG. 6 shows the stress distribution on a
請參照圖2、圖3及圖6,圖6的數據可證:晶片10被彎折時,應力會集中在第二絕緣層180之多個第一凹陷182的轉角處182c,而裂痕容易自第一凹陷182的轉角處182c上產生。也就是說,當晶片10被彎折時,較可能的發生狀況是,裂痕會沿著第二絕緣層180之多個第一凹陷182(或者說,參考軌跡K)產生。當應力在第二絕緣層180之多個第一凹陷182的多個轉角處182c上(或者說,參考軌跡K上)造成裂痕而充分釋放後,便不易對功能區塊FB造成損傷。藉此,即便晶片10被過度彎折而產生裂痕,晶片10仍可正常運作。Please refer to FIG. 2 , FIG. 3 and FIG. 6 . The data in FIG. 6 proves that when the
請參照圖1,圖2及圖3,在本實施例中,導電膠ACP可設置天線20與晶片10的第二絕緣層180之間,其中晶片10的多個接墊P是透過導電膠ACP與天線20電性連接,至少部分的導電膠ACP位於晶片10之第二絕緣層180的多個第一凹陷182中。Referring to FIG. 1 , FIG. 2 and FIG. 3 , in this embodiment, the conductive adhesive ACP can be disposed between the
值得一提的是,第二絕緣層180的多個第一凹陷182除了用以定義應力釋放的路徑(即參考軌跡K)外,多個第一凹陷182的設置還可增加晶片10與導電膠ACP的接觸面積;藉此,可增加晶片10與天線20的接合力,使天線20與晶片10更不易分離。此外,晶片10所承受的應力還可經由導電膠ACP向上傳遞至天線20;藉此,應力會分散至彎折耐受性較佳的天線20上,而使晶片10的功能區塊FB更不易裂損。It is worth mentioning that the plurality of
請參照圖4及圖5,在本實施例中,至少一第一絕緣層140、160的多個實體部162可選擇性地分別具有多個凹陷162a,緩衝層120的多個實體部122可選擇性地分別具有多個凹陷122a,第二絕緣層180可選擇性地具有多個第二凹陷184,其中第二絕緣層180的多個第二凹陷184分別重疊於至少一第一絕緣層140、160之多個實體部162的多個凹陷162a及緩衝層120之多個實體部122的多個凹陷122a。Referring to FIGS. 4 and 5 , in this embodiment, the plurality of
在本實施例中,由於第二絕緣層180的第二凹陷184是重疊於至少一第一絕緣層140、160之實體部162的凹陷162a及緩衝層120之實體部122的凹陷122a,而第二絕緣層180的第一凹陷182是重疊於至少一第一絕緣層140、160的第一貫孔164及緩衝層120的第一貫孔124,因此,第二絕緣層180之第二凹陷184的深度D2小於第二絕緣層180之第一凹陷182的深度D1。In this embodiment, since the
舉例而言,在本實施例中,至少一第一絕緣層140、160之實體部162的凹陷162a及緩衝層120之實體部122的凹陷122a可利用半調(half tone)或灰階調(gray tone)光罩來實現,但本發明不以此為限。For example, in this embodiment, the
請參照圖5及圖6,與圖6之第二絕緣層180的第一凹陷182類似地,晶片10被彎折時,應力會集中在第二絕緣層180之多個第二凹陷184的轉角處184c,而裂痕容易自多個第二凹陷184的多個轉角處184c上產生。也就是說,當晶片10被彎折時,裂痕除了可能沿著第二絕緣層180之多個第一凹陷182產生外,還可能沿著第二絕緣層180之多個第二凹陷184產生。藉此,應力的釋放處除了包括第二絕緣層180的多個第一凹陷182外,還多了第二絕緣層180之多個第二凹陷184。多個第二凹陷184的設置有助於增加應力釋放處,進而保護晶片10的功能區塊FB(標示於圖1)。Referring to FIGS. 5 and 6 , similar to the
此外,在本實施例中,部分的導電膠ACP除了位於第二絕緣層180的多個第一凹陷182以外,還可位於晶片10之第二絕緣層180的多個第二凹陷184中。也就是說,多個第二凹陷184的設置除了能增加應力的釋放處外,還能增加導電膠ACP與晶片10的接觸面積,而更進一步地增加晶片10與天線20的接合力。In addition, in this embodiment, in addition to the plurality of
請參照圖1、圖4及圖5在本實施例中,至少一第一絕緣層140、160還具有至少一第二貫孔146、166,至少一第一絕緣層140、160的至少一第二貫孔146、166位於參考軌跡K之末;第二絕緣層180還具有一貫孔186,且第二絕緣層180的貫孔186重疊於至少一第一絕緣層140、160的至少一第二貫孔146、166;緩衝層120具有一第二貫孔126,且緩衝層120的第二貫孔126重疊於至少一第一絕緣層140、160的至少一第二貫孔146、166。Please refer to FIG. 1 , FIG. 4 and FIG. 5 . In this embodiment, at least one first insulating
在本實施例中,至少一第一絕緣層140、160之第二貫孔146、166的面積大於至少一第一絕緣層140、160之第一貫孔164的面積。至少一第二絕緣層180之貫孔186的面積大於至少一第一絕緣層140、160之第一貫孔164的面積。In this embodiment, the area of the second through
至少一第一絕緣層140、160的至少一第二貫孔146、166、第二絕緣層180的貫孔186及緩衝層120的第二貫孔126可形成一應力傳遞中止池O。應力傳遞中止池O設置於參考軌跡K(或者說,擬撕線)之末。於應力傳遞中止池O所在處,晶片10之所有的非導電層(例如:緩衝層120、第一絕緣層140、160及第二絕緣層180)被挖空,因此,沿著參考軌跡K(或者說,擬撕線)傳遞的應力會被中止在應力傳遞中止池O,而不易破壞晶片10的功能區塊FB及/或其它重要結構。The at least one second through
在本實施例中,參考軌跡K可延伸至基板110的第二非線路區114b上,且至少一第一絕緣層140、160的至少一第二貫孔146、166、第二絕緣層180的貫孔186及緩衝層120的第二貫孔126位於第二非線路區114b上。也就是說,在本實施例中,應力傳遞中止池O是設置於多個功能區塊FB以外的第二非線路區114b上。舉例而言,在本實施例中,應力傳遞中止池O可設置於晶片10的接墊P旁,但本發明不以此為限。在其它實施例中,應力傳遞中止池O也可設置於其它線路密度較低處。In this embodiment, the reference trace K may extend to the second
在本實施例中,由於應力傳遞中止池O設置於晶片10的接墊P旁,因此形成在接墊P上的導電膠ACP會溢入應力傳遞中止池O中,而至少部分的導電膠ACP可位於至少一第一絕緣層140、160的至少一第二貫孔146、166、第二絕緣層180的貫孔186及緩衝層120的第二貫孔126中。但本發明不限於此,在另一實施例中,若形成在接墊P上的導電膠ACP的量較少及/或應力傳遞中止池O離接墊P較遠,導電膠ACP也可能不會充滿/或設置於應力傳遞中止池O中。In this embodiment, since the stress transfer stop pool O is disposed beside the pads P of the
綜上所述,本發明一實施例的晶片包括基板、設置於基板之多個線路區上的多個功能區塊及至少一第一絕緣層。至少一功能區塊包括至少一薄膜電晶體。至少薄膜電晶體具有源汲極、閘極及半導體圖案,而至少一第一絕緣層設置於薄膜電晶體的源汲極、閘極及半導體圖案的至少二者之間。至少一第一絕緣層具有多個第一貫孔及多個實體部。至少一第一絕緣層的多個第一貫孔及多個實體部交替排列,以定義一參考軌跡。特別是,參考軌跡的至少一部分位於多個功能區塊之間的第一非線路區上。To sum up, a chip according to an embodiment of the present invention includes a substrate, a plurality of functional blocks disposed on a plurality of circuit regions of the substrate, and at least one first insulating layer. At least one functional block includes at least one thin film transistor. At least the thin film transistor has a source-drain electrode, a gate electrode and a semiconductor pattern, and at least one first insulating layer is disposed between at least two of the source-drain electrode, the gate electrode and the semiconductor pattern of the thin film transistor. At least one first insulating layer has a plurality of first through holes and a plurality of solid portions. A plurality of first through holes and a plurality of solid portions of at least one first insulating layer are alternately arranged to define a reference track. In particular, at least a portion of the reference trace is located on the first non-wire area between the plurality of functional blocks.
至少一第一絕緣層之多個第一貫孔所定義的參考軌跡可視為晶片的擬撕線。當晶片被彎折時,應力容易沿著擬撕線傳遞,而在擬撕線上釋放,造成沿著擬撕線產生的裂痕。當應力在位在多個功能區塊之間的擬撕線上充分釋放後,便不易造成多個功能區塊的損傷。藉此,即便晶片被過度彎折而沿擬撕線產生裂痕,晶片仍能正常運作。The reference track defined by the plurality of first through holes of the at least one first insulating layer can be regarded as a pseudo-tear line of the wafer. When the wafer is bent, the stress is easily transmitted along the pseudo-tear line, and is released on the pseudo-tear line, resulting in cracks along the pseudo-tear line. When the stress is fully released on the quasi-tear line between the multiple functional blocks, it is not easy to cause damage to the multiple functional blocks. In this way, even if the wafer is excessively bent and cracks are generated along the torn line, the wafer can still operate normally.
10:晶片
20:天線
110:基板
112:線路區
114a:第一非線路區
114b:第二非線路區
120:緩衝層
122、162:實體部
122a、162a:凹陷
124、164:第一貫孔
126、146、166:第二貫孔
130:半導體圖案
140、160:第一絕緣層
150:閘極
172、174:源汲極
180:第二絕緣層
182:第一凹陷
182c、184c:轉角處
184:第二凹陷
186:貫孔
A-A’、B-B’:剖線
ACP:導電膠
BF:緩衝電路
CLK:分頻電路
CRC:循環冗餘校驗電路
CNT:計數電路
D1、D2:深度
DS:資料選擇電路
dec:解碼電路
enc:編碼電路
FB:功能區塊
ISO:標準格式化電路
K:參考軌跡
L1:第一導線
L2:第二導線
M:負載調制電路
O:應力傳遞中止池
P:接墊
R1、R2:局部
Rec:整流電路
ROM:記憶體
T:薄膜電晶體10: Wafer
20: Antenna
110: Substrate
112:
圖1為本發明一實施例之晶片10的上視示意圖。
圖2為本發明一實施例之晶片10之局部R1的放大示意圖。
圖3示出本發明一實施例之晶片10之局部R1的剖面。
圖4為本發明一實施例之晶片10之另一局部R2的放大示意圖。
圖5示出本發明一實施例之晶片10之另一局部R1的剖面。
圖6示出於本發明一實施例之第二絕緣層180之一第一凹陷182上的應力分佈狀況。FIG. 1 is a schematic top view of a
10:晶片10: Wafer
110:基板110: Substrate
114a:第一非線路區114a: First non-wire area
114b:第二非線路區114b: Second non-wire area
164:第一貫孔164: The first through hole
BF:緩衝電路BF: Buffer circuit
CLK:分頻電路CLK: Frequency divider circuit
CRC:循環冗餘校驗電路CRC: Cyclic Redundancy Check Circuit
CNT:計數電路CNT: counting circuit
DS:資料選擇電路DS: Data Selection Circuit
dec:解碼電路dec: decoding circuit
enc:編碼電路enc: encoding circuit
FB:功能區塊FB: functional block
ISO:標準格式化電路ISO: standard format circuit
K:參考軌跡K: Reference track
L1:第一導線L1: the first wire
L2:第二導線L2: Second wire
M:負載調制電路M: Load modulation circuit
O:應力傳遞中止池O: Stress transfer stop cell
P:接墊P: Pad
R1、R2:局部R1, R2: local
Rec:整流電路Rec: Rectifier circuit
ROM:記憶體ROM: memory
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- 2020-06-22 TW TW109121043A patent/TWI740548B/en active
- 2020-07-10 TW TW109123371A patent/TWI756736B/en active
- 2020-07-23 TW TW109124991A patent/TWI728879B/en active
- 2020-08-04 TW TW109126326A patent/TWI754340B/en active
- 2020-09-26 TW TW109133465A patent/TWI776243B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI524991B (en) * | 2013-02-04 | 2016-03-11 | Toyo Boseki | A laminated body, a method for producing a laminated body, and a method for manufacturing the flexible electronic device |
US20160148858A1 (en) * | 2014-11-26 | 2016-05-26 | Kookmin University Industry Academy Cooperation Foundation | Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby |
CN204810675U (en) * | 2015-07-13 | 2015-11-25 | 深圳市弘电显示技术有限公司 | Liquid crystal display is with preventing FPC structure of splitting |
TW201940018A (en) * | 2018-03-16 | 2019-10-01 | 友達光電股份有限公司 | Flexible electronic device and manufacturing method thereof |
CN109712932A (en) * | 2018-11-13 | 2019-05-03 | 友达光电股份有限公司 | Bendable array substrate and its manufacturing method |
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TW202123088A (en) | 2021-06-16 |
TW202123474A (en) | 2021-06-16 |
TW202137065A (en) | 2021-10-01 |
TW202123405A (en) | 2021-06-16 |
TWI776243B (en) | 2022-09-01 |
TW202123536A (en) | 2021-06-16 |
TWI740548B (en) | 2021-09-21 |
TWI747288B (en) | 2021-11-21 |
TWI756736B (en) | 2022-03-01 |
TWI728879B (en) | 2021-05-21 |
TW202123090A (en) | 2021-06-16 |
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