TWI776243B - Integrated circuit, wireless communication card and wiring structure of identification mark - Google Patents

Abstract

An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.

Description

Integrated circuit, wireless communication card and wiring structure of identification mark

The present invention relates to a circuit layout, and more particularly to an integrated circuit, a wireless communication card and a wiring structure for identification marks.

The advantage of wireless communication cards, such as near field wireless communication (NFC) cards and radio frequency identification (RFID) cards, is that they do not need to be pulled out of the wallet. Therefore, it has become a common trading interface. Since the wireless communication card communicates through radio frequency signals, the power supply of the wireless communication card is easily affected by high-frequency noise. In order to filter high-frequency noise, the higher the capacitance value of the voltage stabilization capacitor disposed between the power supply terminal and the ground terminal, the better the effect. Therefore, how to increase the capacitance value of the voltage regulator capacitor in the limited card layout area has become an important issue.

The invention provides an integrated circuit, a wireless communication card and a wiring structure of identification marks, which can increase the capacitance value between the power wiring and the ground wiring.

The integrated circuit of the present invention includes power wiring, ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring overlapping each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.

The wireless communication card of the present invention includes the above-mentioned integrated circuit and an antenna electrically connected to the integrated circuit.

The identification mark wiring structure of the present invention includes a first wiring, a second wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring overlapping each other, wherein the first conductive wiring is electrically connected to the first wiring, and the second conductive wiring is electrically connected to the second wiring.

Based on the above, in the integrated circuit, the wireless communication card and the identification mark wiring structure of the embodiment of the present invention, the identification mark pattern in the integrated circuit is made into a structure of double conductive layers, so as to form the capacitance between the power supply wiring and the ground wiring , thereby increasing the capacitance value between the power wiring and the ground wiring.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprising" and/or "comprising" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but do not exclude one or more The presence or addition of other features, entireties of regions, steps, operations, elements, components, and/or combinations thereof.

FIG. 1A is a schematic diagram of a system of a wireless communication card according to an embodiment of the present invention. Referring to FIG. 1A , in this embodiment, the wireless communication card 10 at least includes an integrated circuit 100 , a modulator 110 , and antenna pads A1 and A2 , wherein the wireless communication card 10 is applied to, for example, near field wireless communication (NFC) and At least one of Radio Frequency Identification (RFID). The integrated circuit 100 at least includes a power wiring Lpow (corresponding to a first wiring), a ground wiring Lgnd (corresponding to a second wiring), a row decoder 101 , a memory 102 , and a column decoder, which are arranged on a substrate SBX (eg, a flexible substrate). 103, a counter 104, a frequency divider (divider) 105, a clamp 106, rectifiers 107 and 108, and a plurality of identification mark patterns PIS1-PIS3.

In this embodiment, the row decoder 101, the memory 102, the column decoder 103, the counter 104, the frequency divider 105, the clamp 106, the rectifiers 107 and 108 are arranged in the main circuit region RMC, and the rectifier 107 and 108 are used to rectify the input received from the antenna (AT shown in FIG. 1A ) to provide the system high voltage and the system low voltage. The substrate SBX is, for example, a flexible substrate, such as a plastic substrate or other polymer substrates. The material of the flexible substrate is, for example, polyimide (PI) or other flexible materials, so that the flexible electronic device with the flexible substrate can be flexed or bent correspondingly when subjected to external force, It can also be thinner and lighter, which is more convenient when applied to integrated circuits and wireless communication cards.

The power wiring Lpow and the ground wiring Lgnd are electrically connected to the rectifiers 107 and 108 . The power wiring Lpow and the ground wiring Lgnd mostly overlap, and the power wiring Lpow and the ground wiring Lgnd are arranged along the edge of the integrated circuit 100 and surround a main circuit region RMC. The identification mark patterns PIS1 to PIS3 are arranged between the main circuit region RMC, the power supply wiring Lpow, and the ground wiring Lgnd. Different from the single metal layer of the traditional identification mark pattern, the identification mark patterns PIS1-PIS3 of the embodiment of the present invention are double conductive layers (that is, have a first conductive wiring and a second conductive wiring), so as to form a double conductive layer capacitor (eg first conductive layer/insulating layer/second conductive layer structure).

The two conductive layers (that is, having the first conductive wiring and the second conductive wiring) overlapping each other of the identification mark patterns PIS1 to PIS3 are electrically connected to the power wiring Lpow and the ground wiring Lgnd, respectively, to form a connection between the power wiring Lpow and the ground wiring Lgnd. The capacitance between the power supply wiring Lpow and the ground wiring Lgnd is thereby increased. The material of the two conductive layers of the identification mark patterns PIS1 to PIS3 is, for example, metal, and the reflectivity of the metal of the identification mark patterns PIS1 to PIS3 is greater than 50%.

In the embodiment of the present invention, the integrated circuit 100 is electrically connected to the antenna pads A1 and A2 through the modulator 110 . The modulator 110 simply converts the analog signal into a digital signal.

FIG. 1B is a schematic diagram of a system of a wireless communication card according to an embodiment of the present invention. 1C is a schematic diagram of a system of a wireless communication card according to an embodiment of the present invention. Referring to FIGS. 1A to 1C , in this embodiment, the rectifiers 107 and 108 rectify the inputs IN+ and IN- received from the antenna (AT shown in FIG. 1C ) to provide the system high voltage VDD and the system low voltage VSS , wherein the system high voltage VDD is transmitted to the components in the system (eg CP1 ~ CP4 ) through the power supply wiring Lpow, and the system low voltage VSS is transmitted to the components in the system (eg CP1 ~ CP4 ) through the ground wiring Lgnd. The integrated circuit 100 can be electrically connected to the antenna AT through, for example, the antenna pads A1 and A2.

In addition, the stabilization capacitor CX is constituted (or formed) by the identification mark patterns PIS1 to PIS3 between the power supply wiring Lpow and the ground wiring Lgnd, and the elements CP1 to CP4 in the system are, for example, the row decoder 101 shown in FIG. 1A . , memory 102 , column decoder 103 , counter 104 , frequency divider 105 and clamp 106 .

FIG. 2 is a detailed schematic diagram of the identification mark pattern PIS1 according to an embodiment of the present invention. Please refer to FIG. 1A and FIG. 2 , in this embodiment, the identification mark pattern PIS1 has a plurality of English character patterns 121-132 for identifying the definitions of the test keys below, such as “VDD” for defining the power terminal, and “VDD” for defining the low-voltage terminal. "VSS", "CLK" that defines the clock terminal, and "OUT" that defines the output terminal, but the embodiment of the present invention is not limited to this.

The two conductive layers of each of the English character patterns 121-132 are electrically connected to the power wiring Lpow and the ground wiring Lgnd individually through one of the pairs of wirings C121-C132 to form a space between the power wiring Lpow and the ground wiring Lgnd capacitor. In addition, in the embodiment of the present invention, the stroke thickness of the English character patterns 121-132 can be adjusted so that the wiring areas of the English character patterns 121-132, that is, the equivalent capacitance of the English character patterns 121-132, are the same. The structure in which the two conductive layers of each of the English character patterns 121-132 are individually electrically connected to the power wiring Lpow and the ground wiring Lgnd through one of the pairs of wirings C121-C132 can be regarded as an identification mark wiring structure. In addition, the outlines of the two conductive layers of each of the English character patterns 121-132 form corresponding identification marks.

FIG. 3 is a detailed schematic diagram of the identification mark pattern PIS2 according to an embodiment of the present invention. 1A and FIG. 3 , in this embodiment, the identification symbol pattern PIS2 has a plurality of English character patterns 140 , 144 , 147 , a plurality of underline character patterns 143 , 146 , and a plurality of digital character patterns 141 , 142 , 145 , 148 , 149 , and 150 are used to define the identification code (or model) of the integrated circuit 100 , for example, “N42_J9_E051”, but the embodiment of the present invention is not limited to this.

The two conductive layers of each of the English text patterns 140 , 144 , 147 , the underline text patterns 143 , 146 , and the digital text patterns 141 , 142 , 145 , 148 , 149 , and 150 pass through the plurality of pairs of traces C140 - 150 . One is electrically connected to the power wiring Lpow and the ground wiring Lgnd to form a capacitance between the power wiring Lpow and the ground wiring Lgnd. In addition, in the embodiment of the present invention, the stroke thickness of the English character patterns 140 , 144 and 147 can be adjusted so that the wiring areas of the English character patterns 140 , 144 and 147 are the same, that is, the equivalent of the English character patterns 140 , 144 and 147 The capacitance will be the same; the stroke thickness of the digital text patterns 141, 142, 145, 148, 149, and 150 can be adjusted to make the wiring areas of the digital text patterns 141, 142, 145, 148, 149, and 150 the same, that is, the digital text patterns 141 , 142, 145, 148, 149, 150 will have the same equivalent capacitance. In an embodiment of the present invention, the wiring areas of the English letter patterns 140 , 144 and 147 may be the same as or different from the wiring areas of the digital letter patterns 141 , 142 , 145 , 148 , 149 and 150 , that is, the English letter patterns 140 , The wiring areas of 144 and 147 may be greater than, equal to or smaller than the wiring areas of the digital character patterns 141 , 142 , 145 , 148 , 149 and 150 , but the embodiment of the present invention is not limited thereto.

Among them, the two conductive layers of each of the English text patterns 140, 144, 147, the underline text patterns 143, 146, and the digital text patterns 141, 142, 145, 148, 149, and 150 pass through the pairs of traces C140-C150 One of the structures in which the power supply wiring Lpow and the ground wiring Lgnd are electrically connected individually can be regarded as an identification mark wiring structure. In addition, the outlines of the two conductive layers of each of the English character patterns 140 , 144 , 147 , the underline character patterns 143 , 146 , and the digital character patterns 141 , 142 , 145 , 148 , 149 , and 150 form corresponding identification marks. .

FIG. 4A is a detailed schematic diagram of the identification mark pattern PIS3 according to an embodiment of the present invention. 1A and FIG. 4A , in this embodiment, the identification mark pattern PIS3 has a plurality of English character patterns 160-162 for identifying the manufacturer of the chip, such as “AUO”, but this is not the case in the embodiment of the present invention limit. Among them, the English character patterns 160-162 of the identification mark pattern PIS3 (that is, the identification marks) are formed by the hollow portions of the two conductive layers that pass through. Wherein, the identification symbol pattern PIS3 is not limited to English letters, and may be other patterns, such as trademark patterns.

The two conductive layers forming the English character patterns 160-162 can be electrically connected to the power wiring Lpow and the ground wiring Lgnd through a plurality of traces C160-C169 to form a capacitance between the power wiring Lpow and the ground wiring Lgnd. However, in the embodiment of the present invention, the two conductive layers forming the English character patterns 160-162 can be directly electrically connected to the power wiring Lpow and the ground wiring Lgnd, without configuring the wirings C160-C169. Among them, the two conductive layers forming the English character patterns 160-162 are directly/indirectly electrically connected to the power wiring Lpow and the ground wiring Lgnd, which can be regarded as a wiring structure of identification marks.

In addition, the integrated circuit 100 further includes extension wirings Lpowx and Lgndx electrically connected to the power wiring Lpow and the ground wiring Lgnd, and the two conductive layers forming the English character patterns 160-162 can be further electrically connected through the wirings C170-C171 To the extension wirings Lpowx and Lgndx. Wherein, the ratio of the hollow area to the non-hollow area (that is, the penetration rate) of the identification mark pattern PIS1 may be T%, where 90%>T%>10%.

FIG. 4B is a detailed schematic diagram of the identification mark pattern PIS3 according to an embodiment of the present invention. 4A and 4B, in this embodiment, the English character patterns 160a-162a of the identification mark pattern PIS3 are formed by the outline of the conductive layer, and are electrically connected to the power supply wiring Lpow and the ground via the wirings C160a-C167a Route Lgnd, where the same or similar elements use the same or similar reference numbers.

5 is a first schematic cross-sectional view of the line segment A-B of the identification mark pattern PIS3 according to an embodiment of the present invention. 5, in this embodiment, in the line segment A-B of the identification mark pattern PIS3, the edge of the first conductive wiring Lc1 and the edge of the second conductive wiring Lc2 of the identification mark pattern PIS1 are not aligned in the overlapping direction dv. Further, in the overlapping direction dv, in the identification mark pattern PIS1, the edge of the first conductive wiring Lc1 exceeds the edge of the second conductive wiring Lc2, wherein the edge of the first conductive wiring Lc1 and the edge of the second conductive wiring Lc2 The difference can be 1 to 3 microns (um).

6 is a second schematic cross-sectional view of the line segment A-B of the identification mark pattern PIS3 according to an embodiment of the present invention. 6, in this embodiment, in the line segment A-B of the identification mark pattern PIS3, the edge of the first conductive wiring Lc1 and the edge of the second conductive wiring Lc2 of the identification mark pattern PIS1 are not aligned in the overlapping direction dv. Further, in the overlapping direction dv, in the identification mark pattern PIS1, the edge of the second conductive wiring Lc2 exceeds the edge of the first conductive wiring Lc1, wherein the edge of the first conductive wiring Lc1 and the edge of the second conductive wiring Lc2 are The difference can be 1 to 3 microns (um).

FIG. 7 is a system schematic diagram of an identification mark wiring structure according to another embodiment of the present invention. Referring to FIG. 7 , in this embodiment, the identification mark wiring structure 200 includes a transistor T21 , a first conductive wiring Lc3 and a second conductive wiring Lc4 , wherein the first conductive wiring Lc3 is electrically connected to the drain wiring of the transistor T21 Ldr (corresponding to the first conductive wiring), and the second conductive wiring Lc4 is electrically connected to the gate wiring Lga (corresponding to the second conductive wiring) of the transistor T21 . In addition, the first conductive wiring Lc3 and the second conductive wiring Lc4 overlap each other, and the hollow portions of the first conductive wiring Lc3 and the second conductive wiring Lc4 form corresponding identification marks (eg, "0001"). Thereby, the distances between the first conductive wiring Lc3 and the second conductive wiring Lc4 and other wirings can be reduced, so that the overall circuit area of the integrated circuit can be reduced, and the circuit area for forming the identification mark can be reduced. In the embodiment of the present invention, the identification mark wiring structure 200 can be applied to any semiconductor product, for example, applied to an on-panel gate driver (Gate Driver on Array, GOA).

FIG. 8 is a schematic diagram illustrating the configuration of a memory and a transistor of a rectifier according to an embodiment of the present invention. Referring to FIG. 1A and FIG. 8 , in this embodiment, the memory 102 has a plurality of transistors T1 , and a plurality of first channel directions d1 from the source T1s to the drain T1d in the plurality of transistors T1 of the memory 102 identical to each other. In addition, the rectifier 107 has a plurality of transistors T2, and the plurality of second channel directions d2 from the source electrode T2s to the drain electrode T2d among the plurality of transistors T2 of the rectifier 107 are the same as each other. Furthermore, the first channel direction d1 from the source to the drain in the transistors T1 of the memory 102 is the same as the second channel direction d2 from the source to the drain in the transistors T1 of the rectifier 107, but the present invention The embodiment is not limited to this. In the embodiment of the present invention, the transistors in the row decoder 101 , the memory 102 , the column decoder 103 , the counter 104 , the frequency divider 105 , the clamp 106 , the rectifiers 107 and 108 of the integrated circuit 100 The channel directions from the source to the drain may be the same as each other, so that the electrical properties of the components in the integrated circuit 100 are uniform.

To sum up, in the integrated circuit, the wireless communication card, and the wiring structure of the identification mark according to the embodiment of the present invention, the identification mark pattern in the integrated circuit is made into a structure of double conductive layers, so as to form a structure between the power supply wiring and the ground wiring. capacitance, thereby increasing the capacitance value between the power wiring and the ground wiring.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Wireless communication card 100: Integrated Circuits 101: Line Decoder 102: Memory 103: Column Decoder 104: Counter 105: divider (divide) frequency 106: Clamp 107, 108: Rectifier 110: Modulator 121-132, 140, 144, 147, 160-162, 160a-162a: English text pattern 141, 142, 145, 148, 149, 150: digital text pattern 143, 146: Bottom line text pattern 200: Identification mark wiring structure A1, A2: Antenna pads A-B: line segment AT: Antenna C121-C132, C140-150, C160-C169, C160a-C167a, C170-C171: wiring d1: first channel direction d2: the direction of the second channel dv: Overlap direction Lc1, Lc3: first conductive wiring Lc2, Lc4: Second conductive wiring Ldr: drain wiring Lga: gate wiring Lgnd: Ground wiring Lpow: Power wiring Lpowx, Lgndx: Extended wiring PIS1~PIS3: Identification mark pattern RMC: Main circuit area SBX: Substrate T21, T1, T2: Transistor IN+, IN-: input VDD: system high voltage VSS: System Low Voltage CP1~CP4: Components CX: stabilized capacitor T1s, T2s: source T1d, T2d: drain

FIG. 1A is a schematic diagram of a system of a wireless communication card according to an embodiment of the present invention. FIG. 1B is a schematic diagram of a system of a wireless communication card according to an embodiment of the present invention. 1C is a schematic diagram of a system of a wireless communication card according to an embodiment of the present invention. FIG. 2 is a detailed schematic diagram of the identification mark pattern PIS1 according to an embodiment of the present invention. FIG. 3 is a detailed schematic diagram of the identification mark pattern PIS2 according to an embodiment of the present invention. FIG. 4A is a detailed schematic diagram of the identification mark pattern PIS3 according to an embodiment of the present invention. FIG. 4B is a detailed schematic diagram of the identification mark pattern PIS3 according to an embodiment of the present invention. 5 is a first schematic cross-sectional view of the line segment A-B of the identification mark pattern PIS3 according to an embodiment of the present invention. 6 is a second schematic cross-sectional view of the line segment A-B of the identification mark pattern PIS3 according to an embodiment of the present invention. FIG. 7 is a system schematic diagram of an identification mark wiring structure according to another embodiment of the present invention. FIG. 8 is a schematic diagram illustrating the configuration of a memory and a transistor of a rectifier according to an embodiment of the present invention.

10: Wireless communication card

100: Integrated Circuits

101: Line Decoder

102: Memory

103: Column Decoder

104: Counter

105: divider (divide) frequency

106: Clamp

107, 108: Rectifier

110: Modulator

A1, A2: Antenna pads

Lgnd: Ground wiring

Lpow: Power wiring

PIS1~PIS3: Identification mark pattern

RMC: Main circuit area

SBX: Substrate

Claims (21)

An integrated circuit includes: a power supply wiring; a ground wiring; at least one identification mark pattern, each of which has a first conductive wiring and a second conductive wiring overlapping each other, wherein a first conductive wiring is electrically connected to the power supply wiring , and the second conductive wiring is electrically connected to the ground wiring, wherein the penetration rate of the at least one identification mark pattern is 90%>T%>10%. The integrated circuit of claim 1, wherein the at least one identification mark pattern includes a plurality of character patterns, wherein the wiring areas of the character patterns are the same as each other. The integrated circuit of claim 1, wherein the at least one identification mark pattern is disposed on a flexible substrate. The integrated circuit of claim 1, wherein the outlines of the first conductive wiring and the second conductive wiring of each of the identification mark patterns form corresponding identification marks. The integrated circuit of claim 1, wherein the respective hollowed-out portions of the first conductive wiring and the second conductive wiring of each of the identification mark patterns form corresponding identification marks. The integrated circuit of claim 1, wherein edges of the first conductive wiring and edges of the second conductive wiring of each of the identification mark patterns are not aligned in an overlapping direction. The integrated circuit of claim 1, wherein the material of the first conductive wiring and the second conductive wiring is metal. The integrated circuit of claim 1, wherein the power wiring and the ground wiring overlap. The integrated circuit of claim 8, wherein the power wiring and the ground wiring are arranged along an edge of the near field communication integrated circuit and surround a main circuit area. The integrated circuit of claim 9, wherein the at least one identification mark pattern is disposed between the main circuit region and the power wiring and the ground wiring. The integrated circuit of claim 9, wherein the main circuit area is configured with a memory, and the directions of the first channels from the source to the drain in the transistors of the memory are the same as each other. The integrated circuit of claim 11, wherein the power wiring and the ground wiring are electrically connected to at least one rectifier, and the first channels from the source to the drain in the transistors of the memory are in the same direction A plurality of second channel directions from source to drain in the plurality of transistors of the at least one rectifier. A wireless communication card, comprising: an integrated circuit as in any one of claims 1 to 12; and an antenna electrically connected to the integrated circuit. An identification mark wiring structure, comprising: a first wiring; a second wiring; At least one identification mark pattern has a first conductive wiring and a second conductive wiring overlapping each other, wherein a first conductive wiring is electrically connected to the first wiring, and the second conductive wiring is electrically connected to the second wiring , wherein the penetration rate of the at least one identification mark pattern is 90%>T%>10%. The identification mark wiring structure of claim 14, wherein the first wiring is a power wiring, and the second wiring is a ground wiring. The identification mark wiring structure according to claim 15, wherein the outer contours of the respective first conductive wiring and the second conductive wiring of each of the at least one identification mark pattern form a corresponding identification mark. The identification mark wiring structure as claimed in claim 15, wherein the respective hollow portions of the first conductive wiring and the second conductive wiring of the at least one identification mark pattern form corresponding identification marks. The identification mark wiring structure of claim 14, wherein the first wiring is a drain wiring, and the second wiring is a source wiring. The identification mark wiring structure as claimed in claim 18, wherein the respective hollow portions of the first conductive wiring and the second conductive wiring of the at least one identification mark pattern form corresponding identification marks. An integrated circuit includes: a power supply wiring; a ground wiring; at least one identification mark pattern, each of which has a first conductive wiring and a second conductive wiring overlapping each other, wherein a first conductive wiring is electrically connected to the power supply wiring , And the second conductive wiring is electrically connected to the ground wiring, wherein the edge of the first conductive wiring and the edge of the second conductive wiring of each of the identification mark patterns are not aligned in an overlapping direction. An integrated circuit includes: a power supply wiring; a ground wiring; at least one identification mark pattern, each of which has a first conductive wiring and a second conductive wiring overlapping each other, wherein a first conductive wiring is electrically connected to the power supply wiring , and the second conductive wiring is electrically connected to the ground wiring, wherein the power wiring and the ground wiring are electrically connected to at least one rectifier, the first ones of the transistors from the source to the drain of the memory The channel direction is the same as a plurality of second channel directions from source to drain in the plurality of transistors of the at least one rectifier.

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