TWI741329B - 半導體封裝件及其製備方法 - Google Patents

半導體封裝件及其製備方法 Download PDF

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TWI741329B
TWI741329B TW108126994A TW108126994A TWI741329B TW I741329 B TWI741329 B TW I741329B TW 108126994 A TW108126994 A TW 108126994A TW 108126994 A TW108126994 A TW 108126994A TW I741329 B TWI741329 B TW I741329B
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Taiwan
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semiconductor layer
layer
fixing
width
opening
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TW108126994A
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TW202040785A (zh
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蘇國輝
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南亞科技股份有限公司
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露提供一種半導體封裝件及其製備方法。該半導體封裝件包括一下半導體層、一上半導體層、一固定結構以及一模塑層。該下半導體層具有一貼合區以及一固定區，該固定區鄰近該貼合區設置。該上半導體層配置在該貼合區上。該固定結構鄰近該上半導體層配置。該固定結構具有至少一固定孔，該固定孔具有一開口，該開口相對應該固定區設置，且該開口具有一第一寬度。該模塑層覆蓋該上半導體層的各側壁。該模塑層具有至少一固定突出物，該固定突出物延伸進入該固定孔中，該固定突出物具有一第一擴張部，該第一擴張部位在該開口下方，且該第一擴張部具有一第二寬度，該第二寬度大於該第一寬度。

Description

半導體封裝件及其製備方法
本申請案主張2019/04/19申請之美國正式申請案第16/389,167號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝件及其製備方法。特別是有關於一種具有複數個半導體層以及一模塑層之半導體封裝件及其製備方法。
對於許多現代應用，半導體裝置是必不可少的。隨著電子科技的進步，在提供具有較佳功能性以及較大量的積體電路的同時，半導體裝置的尺寸持續地變得越來越小。由於半導體裝置規格的微小化，因此提供具有複數個半導體層的一傳統半導體封裝。
所述傳統的半導體封裝具有一下半導體層(lower semiconductor layer)以及一上半導體層(upper semiconductor layer)，該上半導體層配置在該下半導體層的一貼合區(attached region)上。圍繞該上半導體層設置的一模塑層(molding layer)係配置在下半導體層的一固定區(fixturing region)上。
然而，在現今，所述固定區係變得越來越小，且所述模塑層可從該下半導體層分離。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝件。該半導體封裝件包括一下半導體層、一上半導體層、一固定結構以及一模塑層。該下半導體層具有一貼合區以及一固定區，該固定區鄰近該貼合區設置。該上半導體層配置在該貼合區上。該一固定結構鄰近該上半導體層配置，其中該固定結構具有至少一固定孔，該固定孔具有一開口，該開口相對應該固定區設置，且該開口具有一第一寬度。該模塑層覆蓋該上半導體層的各側壁，其中該模塑層具有至少一固定突出物，該固定突出物延伸進入該固定孔中，該固定突出物具有一第一擴張部，該第一擴張部位在該開口下方，且該第一擴張部具有一第二寬度，該第二寬度大於該第一寬度。
依據本揭露之一些實施例，該上半導體層為一晶片堆疊(chip stack)，該晶片堆疊具有複數個半導體晶片。
依據本揭露之一些實施例，該固定結構還具有一氧化層，該氧化層位在該下半導體層的該固定區上，該模塑層配置在該氧化層上。
依據本揭露之一些實施例，該至少一固定孔位在該氧化層中。
依據本揭露之一些實施例，該至少一固定孔位在該下半導體層中。
依據本揭露之一些實施例，該固定突出物從該下半導體層的一頂表面延伸進入到該固定孔中。
依據本揭露之一些實施例，該半導體封裝件還具有一黏貼層，該黏貼層配置在該下半導體層與該上半導體層之間。
依據本揭露之一些實施例，該半導體封裝件還具有多個直通矽穿孔(through silicon vias，TSVs)，該等直通矽穿孔將位在下半導體層下的多個接觸墊電性連接到該上半導體層。
依據本揭露之一些實施例，該固定結構圍繞該上半導體層設置。
依據本揭露之一些實施例，該固定結構為一多孔結構(porosity structure)，且該固定結構具有複數個固定孔，該等固定孔圍繞該上半導體層配置。
依據本揭露之一些實施例，該等固定孔為盲孔。
本揭露之另一實施例提供一種半導體封裝件的製備方法。該製備方法包括將一上半導體層貼合在一下半導體層的一貼合區上；在該下半導體層鄰近該貼合區的一固定區上，形成一氧化層；在該氧化層中形成至少一固定孔，其中該固定孔具有一開口以及一第二擴張部，該第二擴張部位在該開口下方，該開口具有一第一寬度，且該第二擴張部具有一第二寬度，該第二寬度大於該開口的該第一寬度；以及形成一模塑層以覆蓋該上半導體層的各側壁，並填滿該至少一固定孔。
依據本揭露之一些實施例，透過濕蝕刻該氧化層以形成該至少一固定孔。
依據本揭露之一些實施例，該製備方法還包括：在該氧化層中形成該至少一固定孔之前，在該氧化層上提供一蝕刻遮罩，其中該蝕刻遮罩具有至少一蝕刻穿孔，該至少一蝕刻穿孔分別地相對應該固定孔的該至少一開口設置；以及在該至少一固定孔形成之後，移除該蝕刻遮罩。
依據本揭露之一些實施例，該製備方法還包括：固化(curing)該模塑層。
依據本揭露之一些實施例，該製備方法還包括：在該上半導體層與該下半導體層之間形成一黏貼層(adhesive layer)。
本揭露之另一實施例提供一種半導體封裝件的製備方法。該製備方法包括將一上半導體層貼合在一下半導體層的一貼合區上；在該下半導體層的一固定區中形成至少一固定孔，其中該固定孔具有一開口以及一第二擴張部，該第二擴張部位在該開口下方，該開口具有一第一寬度，該第二擴張部具有一第二寬度，該第二寬度大於該開口的該第一寬度；以及形成一模塑層以覆蓋該上半導體層的各側壁，並填滿該至少一固定孔。
依據本揭露之一些實施例，透過濕蝕刻該下半導體層以形成該至少一固定孔。
依據本揭露之一些實施例，該製備方法還包括：在該下半導體層的該固定區中形成該至少一固定孔之前，在該下半導體層的該固定區上提供一蝕刻遮罩，其中該蝕刻遮罩具有至少一蝕刻穿孔，該至少一蝕刻穿孔分別地相對應該固定孔的該至少一開口設置；以及在該至少一固定孔形成之後，移除該蝕刻遮罩。
依據本揭露之一些實施例，該製備方法還包括：固化該模塑層。
依據本揭露之一些實施例，該製備方法還包括：在該上半導體層與該下半導體層之間形成一黏貼層。
由於本揭露的半導體封裝之設計，半導體封裝具有一固定結構(fixturing structure)以及多個固定突出物(fixturing protrusions)，以強化在該模塑層(molding layer)與該下半導體層之間的黏貼強度(adhesive strength)。
除此之外，該模塑層之該固定突出物的寬度係大於該固定孔之該開口的寬度，以使該模塑層可更穩固地黏貼並固定在該下半導體層之該固定孔。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
應當理解，儘管這裡可以使用術語第一，第二，第三等來描述各種元件、部件、區域、層或區段(sections)，但是這些元件、部件、區域、層或區段不受這些術語的限制。相反，這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此，在不脫離本發明進部性構思的教導的情況下，下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。
圖1為依據本揭露一些實施例的一種半導體封裝件的製備方法100之流程示意圖。圖2為依據本揭露一些實施例以圖1的製備方法100製造的一種半導體封裝件之結構示意圖。圖3至圖5為依據本揭露一些實施例以圖1的製備方法100製造一種半導體封裝件於不同製備階段之部分放大示意圖。圖6為依據本揭露一些實施例的一種半導體封裝件200之結構示意圖。圖7為依據本揭露一些實施例的一種半導體封裝件之平面示意圖。在一些實施例中，圖1之半導體封裝件200的製備方法100具有許多操作(s101、s103、s105、s107、s109以及s111)，且下列的敘述以及圖示並非視為所述操作順序的限制。
在操作s101中，如圖2所示，一上半導體層(upper semiconductor layer)210係貼合在一下半導體層(lower semiconductor layer)220的一貼合區(attached region)222上。在一些實施例中，一黏貼層(adhesive layer)240形成在上半導體層210與下半導體層220之間，以將上半導體層210黏貼到下半導體層220。在一些實施例中，上半導體層210為一晶片堆疊(chip stack)，所述晶片堆疊具有複數個半導體晶片，例如記憶體晶片(如DRAM)。在一些實施例中，下半導體層220可為一控制器晶片(controller chip)。
在操作s103中，如圖2所示，一氧化層(oxide layer)225形成在下半導體層220的一固定區(fixturing region)223上。固定區223鄰近貼合區222設置。在一些實施例中，氧化層225含有氧化矽材料。
在操作s105中，如圖3所示，在氧化層225上提供一蝕刻遮罩(etching mask)250。在一些實施例中，蝕刻遮罩250具有至少一蝕刻穿孔(etching via)251。在一些實施例中，蝕刻遮罩250具有複數個蝕刻穿孔251。
在操作s107中，如圖4所示，在氧化層225中形成至少一固定孔(fixturing hole)227。在一些實施例中，形成複數個固定孔227。
在一些實施例中，透過一非等向性(isotropic)蝕刻製程以形成該等固定孔227。在一些實施例中，透過該等蝕刻穿孔251對氧化層225進行濕蝕刻。以此方式，下切效應(undercut effect)發生在蝕刻遮罩250下方。每一固定孔227具有一開口(opening)228以及一第二擴張部(second expanding portion)231，第二擴張部231位在開口228下方。在一些實施例中，該等開口228分別地對應該等蝕刻穿孔251設置。開口228具有一第一寬度230，且該第二擴張部231具有一第二寬度233。第二擴張部231的第二寬度233大於開口228的第一寬度230。
在操作s109中，如圖5所示，移除蝕刻遮罩。在一些實施例中，可透過其他蝕刻製程或一化學機械平坦化(chemical mechanical planarization，CMP)製程移除蝕刻遮罩。
在操作s111中，如圖5所示，形成一模塑層(molding layer)260。在此方法中，形成模塑層260的多個固定突出物(fixturing protrusions)261，並延伸進入該等固定孔227中。每一固定突出物261具有一第一擴張部(first expanding portion)263，第一擴張部263對應第二擴張部231設置，且第一擴張部263具有一第二寬度233。意即，第一擴張部263與第二擴張部231具有相同寬度。
如圖6所示，模塑層260覆蓋上半導體層210的各側壁(side walls)211。在一些實施例中，透過一熱固化(thermal curing)製程固化(cured)模塑層260。在一些實施例中，模塑層260包含環氧化合物(epoxy compound)材料。
由於上述的該等操作，係提供如圖6所示的半導體封裝200。下半導體層220具有貼合區222以及固定區223，且固定區223鄰近貼合區222設置。上半導體層210配置在貼合區222上。上半導體層210為一晶片堆疊，所述晶片堆疊具有複數個半導體晶片。黏貼層240配置在下半導體層220與上半導體層210之間。複數個直通矽穿孔(through silicon vias，TSVs)237形成在下半導體層220，以將位在下半導體層220下方的接觸墊(contact pads)270電性連接到上半導體層210。一固定結構(fixturing structure)224鄰近上半導體層210配置。固定結構224具有至少一固定孔227。模塑層260覆蓋上半導體層210的各側壁211。
如圖7所示，固定結構224圍繞上半導體層210配置。固定結構224為一多孔結構(porosity structure)，且固定結構224具有複數個固定孔227，該等固定孔227圍繞上半導體層210配置。
如圖5所示，每一固定孔227具有開口228，開口228對應固定區223(圖6)設置。開口228具有第一寬度230。固定結構240還具有一氧化層225，氧化層225位在下半導體層220之固定區223上。模塑層260配置在氧化層225上。至少一固定孔227位在氧化層225中。該等固定孔227為盲孔(blind holes)。模塑層260具有至少一固定突出物261，固定突出物261延伸進入固定孔270中。該等固定突出物261具有第一擴張部263，第一擴張部263位在開口228下方，且每一第一擴張部263具有第二寬度233，第二寬度233大於第一寬度230。
圖8為依據本揭露一些實施例的一種半導體封裝件的製備方法700之流程示意圖。圖9為依據本揭露一些實施例以圖8的製備方法製造的一種半導體封裝件之結構示意圖。圖10至圖12為依據本揭露一些實施例以圖8的製備方法製造一種半導體封裝件於不同製備階段之部分放大示意圖。圖13為依據本揭露一些實施例的一種半導體封裝件800之結構示意圖。圖14為依據本揭露一些實施例的一種半導體封裝件之結構示意圖。在一些實施例中，圖8之一種半導體封裝件800的製備方法700具有許多操作(s701、s703、s705、s707以及s109)，且下列的敘述以及圖示並非視為所述操作順序的限制。
在操作s701中，如圖9所示，一上半導體層210貼合在一下半導體層220的一貼合區222上。在一些實施例中，一黏貼層240形成在上半導體層210與下半導體層220之間，以將上半導體層210黏貼到下半導體層220。
在一些實施例中，上半導體層210為一晶片堆疊，所述晶片堆疊具有複數個半導體晶片，例如記憶體晶片(如DRAM)。在一些實施例中，下半導體層220可為一控制器晶片。
在操作s703中，如圖10所示，在下半導體層220的一固定區223上提供一蝕刻遮罩250。在一些實施例中，固定區223鄰近貼合區222設置。蝕刻遮罩250具有至少一蝕刻穿孔251。在一些實施例中，蝕刻遮罩250具有複數個蝕刻穿孔251。
在提供蝕刻遮罩250之後，在操作s705中，如圖11所示，在下半導體層220的固定區223中形成至少一固定孔227。在一些實施例中，形成複數個固定孔227。
在一些實施例中，透過一非等向性蝕刻製程形成該等固定孔227。在一些實施例中，透過該等蝕刻穿孔251對下半導體層220進行濕蝕刻。在此方式中，一下切效應發生在蝕刻遮罩250下方。每一固定孔227具有一開口228以及一第二擴張部231，第二擴張部231位在開口228下方。
在一些實施例中，該等開口228分別地對應該等蝕刻穿孔251設置。每一開口228具有一第一寬度230，且第二擴張部231具有一第二寬度233。第二擴張部231的第二寬度233大於開口228的第一寬度230。
在操作s707中，如圖12所示，在該等固定孔227形成之後，移除蝕刻遮罩。在一些實施例中，可透過其他蝕刻製程或一化學機械平坦化製程移除蝕刻遮罩。
在操作s709中，如圖12所示，形成一模塑層260。模塑層260填滿該等固定孔227。在此方式中，形成模塑層260的該等固定突出物261，並延伸進入該等固定孔227中。每一固定突出物261具有一第一擴張部263，第一擴張部263對應第二擴張部231設置，且固定突出物261的第一擴張部263具有第二寬度233。在一些實施例中，固定突出物261的第一擴張部263與固定孔227的第二擴張部231具有相同寬度。
如圖13所示，模塑層260覆蓋上半導體層210的各側壁211。在一些實施例中，透過一熱固化製程以固化模塑層260。在一些實施例中，模塑層260含有環氧化合物材料。
由於上述的該等操作，提供如圖13所示的半導體封裝800。下半導體層220具有貼合區222以及固定區223，固定區223鄰近貼合區222設置。上半導體層210配置在下半導體層220的貼合區222上。上半導體層210為一晶片堆疊，所述晶片堆疊具有複數個半導體晶片。黏貼層240配置在下半導體層220與上半導體層210之間。複數個直通矽穿孔(TSVs)237形成在下半導體層220中，以將位在下半導體層220下方的多個接觸墊270電性連接到上半導體層210。一固定結構824鄰近上半導體層210設置。固定結構824具有至少一固定孔227。模塑層260覆蓋上半導體層210的各側壁211。
如圖14所示，固定結構824圍繞上半導體層210設置。固定結構824為一多孔結構，且固定結構824具有複數個固定孔227，該等固定孔227圍繞上半導體層210設置。
如圖12所示，每一固定孔227具有開口228，開口228對應固定區設置。開口228具有第一寬度230。所述至少一固定孔227位在下半導體層220中。該等固定孔227為盲孔。模塑層260具有至少一固頂突出物261，固定突出物261延伸進入固定孔227中。固定突出物261從下半導體層220的一頂表面221延伸進入固定孔227。該等固定突出物261具有第一擴張部263，該等第一擴張部263位在該等開口228下方，且每一第一擴張部263具有第二寬度233，第二寬度233大於第一寬度230。
綜上所述，由於本揭露的半導體封裝之架構，半導體封裝具有一固定結構與複數個固定突出物，以強化在模塑層與下半導體層之間的黏貼強度(adhesive strength)。
再者，模塑層之固定突出物的寬度大於固定孔之開口的寬度，以使模塑層可更穩固地黏貼並固定在下半導體層的固定孔。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
本揭露之一實施例提供一種半導體封裝件。該半導體封裝件包括一下半導體層、一上半導體層、一固定結構以及一模塑層。該下半導體層具有一貼合區以及一固定區，該固定區鄰近該貼合區設置。該上半導體層配置在該貼合區上。該一固定結構鄰近該上半導體層配置，其中該固定結構具有至少一固定孔，該固定孔具有一開口，該開口相對應該固定區設置，且該開口具有一第一寬度。該模塑層覆蓋該上半導體層的各側壁，其中該模塑層具有至少一固定突出物，該固定突出物延伸進入該固定孔中，該固定突出物具有一第一擴張部，該第一擴張部位在該開口下方，且該第一擴張部具有一第二寬度，該第二寬度大於該第一寬度。
本揭露之另一實施例提供一種半導體封裝件的製備方法。該製備方法包括將一上半導體層貼合在一下半導體層的一貼合區上；在該下半導體層鄰近該貼合區的一固定區上，形成一氧化層；在該氧化層中形成至少一固定孔，其中該固定孔具有一開口以及一第二擴張部，該第二擴張部位在該開口下方，該開口具有一第一寬度，且該第二擴張部具有一第二寬度，該第二寬度大於該開口的該第一寬度；以及形成一模塑層以覆蓋該上半導體層的各側壁，並填滿該至少一固定孔。
本揭露之另一實施例提供一種半導體封裝件的製備方法。該製備方法包括將一上半導體層貼合在一下半導體層的一貼合區上；在該下半導體層的一固定區中形成至少一固定孔，其中該固定孔具有一開口以及一第二擴張部，該第二擴張部位在該開口下方，該開口具有一第一寬度，該第二擴張部具有一第二寬度，該第二寬度大於該開口的該第一寬度；以及形成一模塑層以覆蓋該上半導體層的各側壁，並填滿該至少一固定孔。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
100:製備方法 s101:操作 s103:操作 s105:操作 s107:操作 s109:操作 s111:操作 200:半導體封裝件 210:上半導體層 211:側壁 220:下半導體層 221:頂表面 222:貼合區 223:固定區 224:固定結構 225:氧化層 227:固定孔 228:開口 230:第一寬度 231:第二擴張部 233:第二寬度 237:直通矽穿孔 240:黏貼層 250:蝕刻遮罩 251:蝕刻穿孔 260:模塑層 261:固定突出物 263:第一擴張部 270:接觸墊 700:製備方法 s701:操作 s703:操作 s705:操作 s707:操作 s709:操作 800:半導體封裝 824:固定結構
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1為依據本揭露一些實施例的一種半導體封裝件的製備方法之流程示意圖。 圖2為依據本揭露一些實施例以圖1的製備方法製造的一種半導體封裝件之結構示意圖。 圖3至圖5為依據本揭露一些實施例以圖1的製備方法製造一種半導體封裝件於不同製備階段之部分放大示意圖。 圖6為依據本揭露一些實施例的一種半導體封裝件之結構示意圖。 圖7為依據本揭露一些實施例的一種半導體封裝件之平面示意圖。 圖8為依據本揭露一些實施例的一種半導體封裝件的製備方法之流程示意圖。 圖9為依據本揭露一些實施例以圖8的製備方法製造的一種半導體封裝件之結構示意圖。 圖10至圖12為依據本揭露一些實施例以圖8的製備方法製造一種半導體封裝件於不同製備階段之部分放大示意圖。 圖13為依據本揭露一些實施例的一種半導體封裝件之結構示意圖。 圖14為依據本揭露一些實施例的一種半導體封裝件之結構示意圖。
200:半導體封裝
210:上半導體層
211:側壁
220:下半導體層
221:頂表面
222:貼合區
223:固定區
224:固定結構
225:氧化層
227:固定孔
237:直通矽穿孔
240:黏貼層
260:模塑層
270:接觸墊

Claims (15)

  1. 一種半導體封裝件，包括：一下半導體層，具有一貼合區以及一固定區，該固定區鄰近該貼合區設置，其中該下半導體層為一控制器晶片；一上半導體層，配置在該貼合區上；一氧化層，圍繞該上半導體層配置，其中該氧化層具有至少一固定孔，該固定孔具有一開口，該開口相對應該固定區設置，且該開口具有一第一寬度；一模塑層，覆蓋該上半導體層的各側壁，其中該模塑層具有至少一固定突出物，該固定突出物延伸進入該固定孔中，該固定突出物具有一第一擴張部，該第一擴張部位在該開口下方，且該第一擴張部具有一第二寬度，該第二寬度大於該第一寬度；以及多個直通矽穿孔(through silicon vias)，位於該下半導體層中，以將該下半導體層下的多個接觸墊電性連接到該上半導體層，其中該氧化層位於該下半導體層和該模塑層之間。
  2. 如請求項1所述之半導體封裝件，其中該上半導體層為一晶片堆疊(chip stack)，該晶片堆疊具有複數個半導體晶片。
  3. 如請求項1所述之半導體封裝件，其中該氧化層位在該下半導體層的該固定區上。
  4. 如請求項3所述之半導體封裝件，其中該至少一固定孔位在該氧化層中。
  5. 如請求項1所述之半導體封裝件，其中該至少一固定孔位在該下半導體層中。
  6. 如請求項5所述之半導體封裝件，其中該固定突出物從該下半導體層的一頂表面延伸進入到該固定孔中。
  7. 如請求項1所述之半導體封裝件，還具有一黏貼層，該黏貼層配置在該下半導體層與該上半導體層之間。
  8. 如請求項1所述之半導體封裝件，其中該固定結構圍繞該上半導體層設置。
  9. 如請求項8所述之半導體封裝件，其中該固定結構為一多孔結構(porosity structure)，且該固定結構具有複數個固定孔，該等固定孔圍繞該上半導體層配置。
  10. 如請求項9所述之半導體封裝件，其中該等固定孔為盲孔。
  11. 一種半導體封裝件的製備方法，包括：將一上半導體層貼合在一下半導體層的一貼合區上； 在該下半導體層鄰近該貼合區的一固定區上，形成一氧化層，該氧化層圍繞該上半導體層配置，並且形成多個直通矽穿孔(through silicon vias)於該下半導體層中，其中該下半導體層為一控制器晶片；在該氧化層中形成至少一固定孔，其中該固定孔具有一開口以及一第二擴張部，該第二擴張部位在該開口下方，該開口具有一第一寬度，且該第二擴張部具有一第二寬度，該第二寬度大於該開口的該第一寬度；以及形成一模塑層以覆蓋該上半導體層的各側壁，並填滿該至少一固定孔，其中該氧化層位於該下半導體層和該模塑層之間。
  12. 如請求項11所述之製備方法，其中透過濕蝕刻該氧化層以形成該至少一固定孔。
  13. 如請求項11所述之製備方法，還包括：在該氧化層中形成該至少一固定孔之前，在該氧化層上提供一蝕刻遮罩，其中該蝕刻遮罩具有至少一蝕刻穿孔，該至少一蝕刻穿孔分別地相對應該固定孔的該至少一開口設置；以及在該至少一固定孔形成之後，移除該蝕刻遮罩。
  14. 如請求項11所述之製備方法，還包括：固化(curing)該模塑層。
  15. 如請求項11所述之製備方法，還包括：在該上半導體層與該下半導體層之間形成一黏貼層(adhesive layer)。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200605298A (en) * 2004-04-13 2006-02-01 Vertical Circuits Inc Stacked die BGA or LGA component assembly
TWM426143U (en) * 2011-06-17 2012-04-01 Lextar Electronics Corp Package substrate and package structure thereof
TW201535545A (zh) * 2014-03-14 2015-09-16 Toshiba Kk 半導體裝置之製造方法及半導體裝置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5205036A (en) * 1988-10-17 1993-04-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with selective coating on lead frame
US5045151A (en) * 1989-10-17 1991-09-03 Massachusetts Institute Of Technology Micromachined bonding surfaces and method of forming the same
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE102005028704B4 (de) * 2005-06-20 2016-09-08 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten
TWI585904B (zh) * 2016-04-22 2017-06-01 矽品精密工業股份有限公司 電子封裝件及基板結構
KR102467034B1 (ko) * 2016-05-17 2022-11-14 삼성전자주식회사 반도체 패키지
KR20190015661A (ko) * 2017-08-03 2019-02-14 에스케이하이닉스 주식회사 복수의 다이들이 적층된 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200605298A (en) * 2004-04-13 2006-02-01 Vertical Circuits Inc Stacked die BGA or LGA component assembly
TWM426143U (en) * 2011-06-17 2012-04-01 Lextar Electronics Corp Package substrate and package structure thereof
TW201535545A (zh) * 2014-03-14 2015-09-16 Toshiba Kk 半導體裝置之製造方法及半導體裝置

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