TWI741121B - 用於選擇性磊晶之方法及設備 - Google Patents

用於選擇性磊晶之方法及設備 Download PDF

Info

Publication number
TWI741121B
TWI741121B TW107100164A TW107100164A TWI741121B TW I741121 B TWI741121 B TW I741121B TW 107100164 A TW107100164 A TW 107100164A TW 107100164 A TW107100164 A TW 107100164A TW I741121 B TWI741121 B TW I741121B
Authority
TW
Taiwan
Prior art keywords
substrate
silicon
germanium
processing chamber
dielectric surface
Prior art date
Application number
TW107100164A
Other languages
English (en)
Other versions
TW201839798A (zh
Inventor
李學斌
華 仲
芳松 張
紹芳 諸
阿布希雪克 督比
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201839798A publication Critical patent/TW201839798A/zh
Application granted granted Critical
Publication of TWI741121B publication Critical patent/TWI741121B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0227Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0236Pretreatment of the material to be coated by cleaning or etching by etching with a reactive gas
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/38Borides
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/186Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02576N-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02592Microstructure amorphous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02614Transformation of metal, e.g. oxidation, nitridation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • H01L21/02661In-situ cleaning

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

在具有矽表面和介電表面的基板上形成膜的方法包括以下步驟:預清洗基板;將抑制劑物質施加於介電表面;以及在保持小於約攝氏600度的溫度同時將基板暴露於前驅物。

Description

用於選擇性磊晶之方法及設備
本揭示案的實施例一般係關於半導體製造製程和元件領域,更具體地來說,係關於用於形成半導體元件之沉積含矽或含鍺的膜的沉積方法。
一般來說,選擇性磊晶製程允許以在介電表面(如氧化物或氮化物)上最小化磊晶層生長來在矽表面上生長磊晶層。為了在磊晶製程期間保持選擇性(即,以在介電表面上最小化生長來在基板的矽表面上實現選定的結晶生長),可在整個磊晶製程調節及調整沉積氣體、鹵素前驅物和反應溫度。
當前的選擇性磊晶製程有一些缺點。為了在現在的磊晶製程期間保持選擇性,必須在整個沉積過程中調節和調整前驅物的化學濃度和/或反應溫度。若沒有施用足夠的矽前驅物,則蝕刻反應可能佔優(dominate),且總體製程減慢。再者,可能發生有害的基板特徵的過度蝕刻。若沒有施用足夠的蝕刻劑前驅物,則沉積反應可能主導降低選擇性,而在基板表面上形成單晶和多晶材料。再者,當前的選擇性磊晶製程通常需要高的反應溫度,如高於800℃或更高。在某些製造過程中,由於熱預算考慮以及對基板表面可能不受控制的氮化反應,而不需要有此類高溫。此外,以傳統方式處理,在低於約800℃的溫度下同時沉積和蝕刻,在某些情況下導致不可接受的低生長速率。
在較低的生長溫度下(如在約600℃或低於約600℃下),選擇性磊晶製程可能變得更具挑戰性。在此類溫度下,氯化氫(HCl)分解效率變差。如此一來,在介電表面(如SiO2 或SiN)上可能有非晶矽(aSi)或非晶鍺(aGe)成核發生。因此,需要一種用於選擇性和磊晶沉積含矽或含鍺化合物的製程,同時保持低的製程溫度,如約600℃或更低。
在本說明書揭示的一個或更多個實施例中,一種在具有矽表面和介電表面的基板上形成膜的方法包括以下步驟:預清洗基板;將抑制劑物質施加於介電表面;以及在保持小於約攝氏600度的溫度同時將基板暴露於前驅物。
本說明書揭示的實施例包括用於將抑制劑物質附著於基板的選定表面(如介電表面)或從基板的選定表面去除抑制劑物質的方法和設備。在接下來的磊晶膜沉積期間,這種附著的抑制劑物質可阻止在所選表面上源前驅物的成核。如此一來,由於抑制劑物質的阻斷劑化學性質的選擇特性,可實現在較低溫度下的選擇性磊晶。
本說明書揭示的實施例通常提供在製造電子元件期間在基板表面上選擇性地和磊晶地沉積含矽或含鍺材料的製程。基板表面可具有單晶表面(如矽或矽鍺;摻雜或沒有摻雜硼、磷、砷等)和介電表面(如SiO2 或SiN)。可將抑制劑物質施加於基板表面。抑制劑物質可優先地(preferentially)附著於介電表面。在隨後的磊晶沉積製程中,抑制劑物種也可以是熱穩定的。也可在對下面的表面輕微損害或沒有損害的情況下去除抑制劑物質。
在整個本申請案中,術語「含矽或含鍺」材料、化合物、膜或層應解釋為包括至少含有矽或鍺以及亦可含有碳、硼、砷,磷、鎵和/或鋁的化合物。其他元素(如金屬、鹵素或氫)可結合在含矽或含鍺的材料、化合物、膜或層中,通常為百萬分之一(ppm)的濃度。含矽或含鍺材料的化合物或合金可用縮寫表示,如針對矽的Si、針對鍺的Ge、針對矽鍺的SiGe、針對矽碳的SiC和針對矽鍺碳的SiGeC。縮寫不代表具有化學計量關係的化學方程式,也不代表含矽或含鍺材料的任何特定的還原/氧化態。
根據一個或更多個實施例,磊晶製程包括重複沉積製程和蝕刻製程的循環,直到生長出所需厚度的磊晶層。在一些實施例中,抑制劑的施加過程可以在第一循環的磊晶製程之前。在一些實施例中,抑制劑的施加過程可以在多個循環的磊晶製程中的沉積製程之前。
在一個或更多個實施例中,沉積製程包括將基板表面暴露於前驅物(如含有至少矽或鍺源的沉積氣體)。沉積氣體通常也會包含載體氣體。在一個或更多個實施例中,沉積氣體亦可包括碳源以及摻雜劑源。在沉積製程期間,可在基板的單晶表面上形成磊晶層,而在介電表面上形成很少的矽或鍺(結晶或非晶形)或者沒有形成矽或鍺。
在一個或更多個實施例中,蝕刻製程包括將基板暴露於蝕刻氣體。蝕刻氣體通常包括載體氣體和蝕刻劑,如氯氣或氯化氫。蝕刻氣體可去除在沉積製程期間沉積的含矽或含鍺的材料。根據某些實施例,在蝕刻製程期間,可以以比磊晶層更快的速率去除抑制劑物質。因此,沉積和蝕刻製程的最終結果是在單晶表面上形成磊晶生長的含矽或含鍺材料,同時使介電表面上的含矽或含鍺材料(若有的話)的生長最小化。在一個或更多個實施例中,在沉積和蝕刻步驟之間調整處理腔室內的壓力,使得蝕刻期間的壓力可以高於沉積期間的壓力。根據一個或更多個實施例,增加的壓力可能導致基板溫度的增加。在其他實施例中,可在沉積和蝕刻步驟之間調整和改變到處理腔室的某些區域的氣體分佈。可根據需要重複沉積和蝕刻製程的循環以獲得所需厚度的含矽或含鍺材料。本發明實施例可以沉積的含矽或含鍺的材料包括矽、鍺、矽鍺、矽碳、矽鍺碳和摻雜劑變體。
在一個實施例中,使用氯氣作為蝕刻劑可將總體製程溫度降低到約600℃之下。一般來說,沉積製程可在比蝕刻反應更低的溫度下進行,因為蝕刻劑通常需要高溫來活化。例如,矽烷可在約500℃或更低的溫度下被熱分解以沉積矽,而氯化氫可能需要約700℃或更高的活化溫度以作為有效的蝕刻劑。因此,若在製程期間使用氯化氫,則整個製程的溫度可由活化蝕刻劑所需的較高溫度決定。氯可藉由降低所需的整個製程的溫度而有助於整個製程。氯可在低至約300℃的溫度下被活化。因此,藉由將氯作為蝕刻劑加入製程中,整個製程的溫度可顯著降低,如在使用氯化氫作為蝕刻劑的製程中降低300℃至400℃。再者,氯比氯化氫更快地蝕刻含矽或含鍺的材料。因此,氯蝕刻劑可增加整個製程的速度。
載體氣體可以是任何合適的惰性氣體或氫氣。雖然稀有氣體(如氬或氦)可用作惰性載體氣體,但根據某些實施例,氮在經濟考量上可以為優選的惰性載體氣體。使用氮氣作為載體氣體可能發生的一個缺點是在沉積製程中基板上的材料氮化。然而,可能需要高溫(如高於800℃)以這種方式活化氮氣。因此,在一個或更多個實施例中,在低於氮活化閾值的溫度下進行的製程中,氮可以用作惰性載體氣體。使用氯作為蝕刻劑和氮氣作為載體氣體的綜合效果可大大提高整個製程的速度。
圖1繪示可在一個或更多個實施例中應用的一系列處理過程。方法100從步驟110開始,其中預清洗基板。例如,基板可以是具有原生氧化物的晶圓。在一些實施例中,可使用SiCoNiTM 預清洗腔室將原生氧化物自晶圓上清洗掉,SiCoNiTM 預清洗腔室可自美國加州聖塔克拉拉的應用材料公司取得。SiCoNiTM 預清洗製程可透過使用NF3 和NH3 的低溫兩步驟乾式化學清洗製程去除原生氧化物。在一些實施例中,可使用Collins等人的美國專利第7,288,491和7,291,545號中揭示的腔室或方法將原生氧化物自晶圓清洗掉。在一些實施例中,步驟110可包括額外的準備步驟。例如,步驟110亦可包括預烘烤晶圓。在預烘烤期間,晶圓可暴露於H2 ,以進一步清洗表面。預烘烤可在磊晶(Epi)腔室中完成。預烘烤可包括將基板的溫度升高至約600℃至800℃。在一些實施例中,步驟110包括基板的HF清洗,其可能導致矽(單晶)表面上的-H終端(termination)和氧化物(介電)表面上的-OH終端。
方法100繼續到步驟120,其中將抑制劑物質施加於暴露的介電表面。例如,抑制劑物質可以是應用於暴露的SiO2 和SiN表面的阻斷劑層。抑制劑物質可施加於基板的表面且優先地附著於介電表面。例如,介電表面上的阻斷劑層可能鈍化,但單晶表面上阻斷劑層的鈍化很少或沒有鈍化。在阻斷劑化學腔室中可將抑制劑物質施加於基板。阻斷劑層可以是單層。抑制劑物質可來自於將基板暴露於各式各樣的分子(如三氯矽烷、三烷氧基矽烷或矽烷基胺)而產生。抑制劑物質可包括碳。抑制劑物質可包括聚合物,如長鏈分子或短鏈分子。阻斷劑化學腔室可整合到與預清洗腔室相同的主框架。在一些實施例中,抑制劑物質優先與-OH終端的氧化物(介電)表面反應,同時與-H終端的矽(單晶)表面最低限度地反應。
方法100繼續到步驟130,其中基板暴露於用於含矽或含鍺層磊晶沉積的前驅物。磊晶沉積製程的實例包括矽(Si)、矽碳(SiC)、矽磷(SiP)、矽鍺(SiGe)、矽鍺硼(SiGeB)、矽硼(SiB)、鍺(Ge)、鍺硼(GeB)和鍺磷(GeP)。在一些實施例中,當基板暴露於前驅物時,方法100包括將磊晶腔室內的條件調整至所需的溫度和壓力。例如,方法100可包括將基板保持在不超過約600℃的溫度的步驟135。在一些實施例中,基板溫度可保持在約400℃或低於約400℃。在一些實施例中,前驅物可包括GeB,且可將基板維持在300℃至320℃之間的溫度以沉積厚度為10nm級的層。在一些實施例中,阻斷劑層可有利地改善在較低磊晶溫度(如低於約400℃)下的選擇性以及因此能夠實現低熱預算處理。
根據一個或更多個實施例,磊晶腔室中的壓力保持相對低,如低於約50Torr。取決於磊晶厚度,由於阻斷劑化學性質,在介電表面上可能沒有生長或生長很少。若任何材料在介電層上生長,則由於材料所生長的介電表面的形態,材料通常具有非晶形結構。 相反地,若在晶體半導體材料上生長的話,則在半導體層上生長的材料通常具有結晶結構。使用本說明書所述之阻斷劑化學物質,減少隨著結晶磊晶層生長而在介電層上的非晶形材料(如非晶矽(aSi))的生長。相信阻斷劑化學可起到減少、延遲或減緩介電層上磊晶位點成核的作用。因此,由於阻斷劑化學物質引起的成核延遲,與半導體表面上的磊晶層相比,結果介電表面上可能是非常薄的aSi層。
在一些實施例中,方法100在可選步驟140繼續,其中藉由將基板暴露於蝕刻氣體來去除殘留物層。例如,可去除介電表面上的任何aSi。殘留物層可以是非晶膜,如aSi。可藉由用HCl、Cl2 或GeH4 /HCl回蝕可去除aSi。在一些實施例中,可在磊晶腔室中去除aSi。
方法100可在步驟150繼續,其中抑制劑物質被去除。例如,可用氧化處理從介電表面去除抑制劑物質。可在去除腔室(如灰化腔室、蝕刻腔室或遠端電漿氧腔室)中去除抑制劑物質。如本發明所屬領域中具有通常知識者根據本揭示案將理解的那樣,通常不會在磊晶腔室中去除抑制劑物質,因為在半導體工業中,磊晶腔室通常保持無氧。在一些實施例中,可在阻斷劑化學腔室中去除抑制劑物質。在一些實施例中,可藉由在抑制劑物質中包含碳來提前去除抑制劑物質。在一些實施例中,在去除抑制劑物質期間,基板的溫度低(如低於沉積製程期間的溫度)。與濺射相比,去除抑制劑物質可導致相對平滑的介電表面。
在一些實施例中,基板可接著經受下游處理。在一些實施例中,方法100的一個或更多個步驟可作為磊晶製程循環而重複。
圖2A至2F圖示一系列顯微照片(圖2A至2F),說明幾個實施例中抑制劑物質的影響。施用相同GeB磊晶製程來測試施加或不施加抑制劑物質的不同介電基板上的選擇性。圖2A表示具有熱氧化物介電層及在熱氧化物介電層上的GeB層的基板。 圖2A中沒有抑制劑施加於熱氧化物層。圖2B顯示了與圖2A相似的基板,除了是在形成GeB層之前將抑制劑物質施加於熱氧化物層之外。在這種情況下,即使沒有施加抑制劑物質,GeB處理過程本身對熱氧化物也是有選擇性的,且在圖2A中沒有觀察到可見的沉積GeB結核。但是GeB處理過程對氮化物介電表面沒有選擇性。且具有抑制劑的氮化物介電基板使得不具有抑制劑的基板有不同的結果,如圖2C至2F所示。圖2C表示在經歷GeB沉積之後,沒有抑制劑物質的熱氮化物介電質。圖2D表示在經歷GeB沉積之後,有抑制劑物質的熱氮化物介電質。圖2C表示沉積在沒有被阻擋的熱氮化物介電質上的可見的GeB微小結核(nodule)。圖2E繪示在經受GeB沉積之後沒有抑制劑物質的ALD氮化物介電質。圖2F繪示在經受GeB沉積之後具有抑制劑物質的ALD氮化物介電質。圖2E表示沉積在沒有被阻擋的ALD氮化物介電質上的可見的GeB微小結核。因此,在適當的抑制劑材料的施用情況下,在氮化物介電基板上實現GeB製程的選擇性。基於這些結果,使用可從本說明書所述之阻斷劑化學取得的抑制劑來控制基板的介電表面上的磊晶沉積是可能的。
在一個實施例中,一種在基板上形成膜的方法,該方法具有矽表面和介電表面,該方法包括以下步驟:預清洗基板;將抑制劑物質施加於介電表面;以及在保持小於約攝氏600度的溫度同時將基板暴露於前驅物。
在本說明書揭示的一個或更多個實施例中,前驅物包含矽源和鍺源中的至少一個。
在本說明書揭示的一個或更多個實施例中,前驅物包含碳源和摻雜劑源中的至少一個。
在本說明書揭示的一個或更多個實施例中,該方法進一步包括以下步驟:在基板上沉積包含磷的含矽磊晶層。
在本說明書揭示的一個或更多個實施例中,該方法進一步包括以下步驟:在基板上沉積包含硼的含鍺磊晶層。
在本說明書揭示的一個或更多個實施例中,施加抑制劑物質的步驟包括以下步驟:將基板暴露於以下各者中的至少一個:三氯矽烷、三烷氧基矽烷、矽烷基胺、碳和聚合物。
在本說明書揭示的一個或更多個實施例中,該方法進一步包括以下步驟:從介電表面去除非晶矽和非晶鍺中的至少一個。
在本說明書揭示的一個或更多個實施例中,去除非晶矽和非晶鍺中的至少一個之步驟包括以下步驟:將基板暴露於蝕刻氣體。
在本說明書揭示的一個或更多個實施例中,該方法進一步包括以下步驟:從介電表面去除抑制劑物質。
在本說明書揭示的一個或更多個實施例中,去除抑制劑物質的步驟包括氧化處理。
在本說明書揭示的一個或更多個實施例中,該方法進一步包括以下步驟:在從介電表面去除抑制劑物質之前,從介電表面去除非晶矽和非晶鍺中的至少一個。
在一個實施例中,用於處理基板的系統包括:預清洗腔室,該預清洗腔室用於將原生氧化物自基板清洗掉;阻斷劑化學腔室,該阻斷劑化學腔室用於將抑制劑物質施加於該基板;及第一磊晶腔室,該第一磊晶腔室用於將基板暴露於用於磊晶沉積一層的前驅物,該前驅物包含矽材料和鍺材料中的至少一個;其中預清洗腔室和阻斷劑化學腔室被整合於單個主框架上。
在本說明書揭示的一個或更多個實施例中,該系統亦包括用於預烘烤基板的預烘烤腔室。
在本說明書揭示的一個或更多個實施例中,預烘烤腔室是第二磊晶腔室。
在本說明書揭示的一個或更多個實施例中,第一磊晶腔室和第二磊晶腔室是相同的磊晶腔室。
在本說明書揭示的一個或更多個實施例中,該系統亦包括用於從基板去除抑制劑物質的去除腔室。
在本說明書揭示的一個或更多個實施例中,去除腔室包括以下各者中的至少一個:灰化腔室、蝕刻腔室、遠端電漿氧腔室和阻斷劑化學腔室。
雖然前面所述係針對特定實施例,但在不背離本揭示的基本範圍下,可設計其他與進一步的實施例。
100‧‧‧方法110‧‧‧步驟120‧‧‧步驟130‧‧‧步驟135‧‧‧步驟140‧‧‧步驟150‧‧‧步驟
本揭露之特徵已簡要概述於前,並在以下有更詳盡之討論,可以藉由參考所附圖式中繪示之本案實施例以作瞭解。然而,值得注意的是,所附圖式只繪示了示範實施例且不會視為其範圍之限制,本揭示可允許其他等效之實施例。
圖1繪示可在一個或更多個實施例中應用的一系列處理過程。
圖2A至2F表示一系列顯微照片(2A-2F),說明幾個實施例中抑制劑物質的影響。
為便於理解,在可能的情況下,使用相同的數字編號代表圖示中相同的元件。可以預期的是一個實施例中的元件與特徵可有利地用於其他實施例中而無需贅述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
100‧‧‧方法
110‧‧‧步驟
120‧‧‧步驟
130‧‧‧步驟
135‧‧‧步驟
140‧‧‧步驟
150‧‧‧步驟

Claims (12)

  1. 一種在一基板上形成一膜的方法,該方法包括以下步驟:預清洗一基板,其中該基板的一表面包括矽表面和介電表面;在一第一處理腔室中,將一抑制劑物質施加於該基板的該表面,使得該抑制劑物質優先地附著於該基板的該表面的該介電表面;在一第二處理腔室中,將在該介電表面上具有該抑制劑物質之該基板暴露於一前驅物,以磊晶地沉積一含矽或含鍺的層,該第二處理腔室不同於該第一處理腔室,同時將該基板保持在小於約攝氏600度的一第一溫度;及在一第三處理腔室中,使用一氧化處理以從該介電表面去除該抑制劑物質,該第三處理腔室不同於該第二處理腔室,同時將該基板保持在低於該第一溫度之一第二溫度。
  2. 如請求項1所述之方法,其中該前驅物包括矽源或鍺源中的至少一個。
  3. 如請求項2所述之方法,其中該前驅物包括碳源或摻雜劑源中的至少一個。
  4. 如請求項1所述之方法,進一步包括以下步 驟:在該基板上沉積包含磷的含矽磊晶層。
  5. 如請求項1所述之方法,進一步包括以下步驟:在該基板上沉積包含硼的含鍺磊晶層。
  6. 如請求項1所述之方法,其中施加該抑制劑物質的步驟包括以下步驟:將該基板暴露於以下各者中的至少一個:三氯矽烷、三烷氧基矽烷、矽烷基胺、碳、或聚合物。
  7. 如請求項1所述之方法,進一步包括以下步驟:從該介電表面去除非晶矽或非晶鍺中的至少一個。
  8. 如請求項7所述之方法,其中去除非晶矽或非晶鍺中的至少一個之步驟包括以下步驟:將該基板暴露於一蝕刻氣體。
  9. 如請求項1所述之方法,進一步包括以下步驟:在從該介電表面去除該抑制劑物質之前,從該介電表面去除非晶矽或非晶鍺中的至少一個。
  10. 如請求項1所述之方法,進一步包括在該第二處理腔室中預烘烤該基板。
  11. 如請求項1所述之方法,進一步包括在一第四處理腔室中預烘烤該基板。
  12. 如請求項1所述之方法,其中該預清洗步驟在一預清洗腔室中執行。
TW107100164A 2017-01-05 2018-01-03 用於選擇性磊晶之方法及設備 TWI741121B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762442753P 2017-01-05 2017-01-05
US62/442,753 2017-01-05
US15/661,124 2017-07-27
US15/661,124 US10504723B2 (en) 2017-01-05 2017-07-27 Method and apparatus for selective epitaxy

Publications (2)

Publication Number Publication Date
TW201839798A TW201839798A (zh) 2018-11-01
TWI741121B true TWI741121B (zh) 2021-10-01

Family

ID=62711320

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107100164A TWI741121B (zh) 2017-01-05 2018-01-03 用於選擇性磊晶之方法及設備

Country Status (4)

Country Link
US (1) US10504723B2 (zh)
KR (1) KR102480359B1 (zh)
TW (1) TWI741121B (zh)
WO (1) WO2018128789A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10695794B2 (en) 2015-10-09 2020-06-30 Asm Ip Holding B.V. Vapor phase deposition of organic films
US10453701B2 (en) 2016-06-01 2019-10-22 Asm Ip Holding B.V. Deposition of organic films
US10217630B2 (en) * 2016-11-24 2019-02-26 Tokyo Electron Limited Method of forming silicon-containing film
JP7146690B2 (ja) * 2018-05-02 2022-10-04 エーエスエム アイピー ホールディング ビー.ブイ. 堆積および除去を使用した選択的層形成
KR102138149B1 (ko) * 2019-08-29 2020-07-27 솔브레인 주식회사 박막 형성용 성장 억제제, 이를 이용한 박막 형성 방법 및 이로부터 제조된 반도체 기판
KR102141547B1 (ko) * 2019-09-25 2020-09-14 솔브레인 주식회사 박막 제조 방법
KR102156663B1 (ko) * 2019-09-25 2020-09-21 솔브레인 주식회사 박막 제조 방법
TWI847071B (zh) * 2020-12-18 2024-07-01 美商應用材料股份有限公司 沉積膜的方法
WO2024064161A1 (en) * 2022-09-21 2024-03-28 Lam Research Corporation Semiconductor stacks and processes thereof
KR102603788B1 (ko) 2023-05-30 2023-11-17 주식회사 한성넥스 가구용 손잡이

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090111246A1 (en) * 2007-10-26 2009-04-30 Asm America, Inc. Inhibitors for selective deposition of silicon containing films

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429084B1 (en) 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains
US7390739B2 (en) * 2005-05-18 2008-06-24 Lazovsky David E Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
US20070134821A1 (en) 2004-11-22 2007-06-14 Randhir Thakur Cluster tool for advanced front-end processing
US7312128B2 (en) 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
JP4847152B2 (ja) * 2006-02-22 2011-12-28 富士通セミコンダクター株式会社 半導体装置とその製造方法
US9064960B2 (en) 2007-01-31 2015-06-23 Applied Materials, Inc. Selective epitaxy process control
US7776698B2 (en) * 2007-10-05 2010-08-17 Applied Materials, Inc. Selective formation of silicon carbon epitaxial layer
US7888220B2 (en) 2008-06-26 2011-02-15 Intel Corporation Self-aligned insulating etchstop layer on a metal contact
US8293658B2 (en) 2010-02-17 2012-10-23 Asm America, Inc. Reactive site deactivation against vapor deposition
US10011920B2 (en) * 2011-02-23 2018-07-03 International Business Machines Corporation Low-temperature selective epitaxial growth of silicon for device integration
US8871617B2 (en) * 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
US9343356B2 (en) * 2013-02-20 2016-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Back end of the line (BEOL) interconnect scheme
JP5931780B2 (ja) * 2013-03-06 2016-06-08 東京エレクトロン株式会社 選択エピタキシャル成長法および成膜装置
CN105019019B (zh) * 2014-04-30 2019-04-19 应用材料公司 用于选择性外延硅沟槽填充的方法
US9653291B2 (en) * 2014-11-13 2017-05-16 Applied Materials, Inc. Method for removing native oxide and residue from a III-V group containing surface
US9564312B2 (en) * 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
CN114551229A (zh) 2015-04-10 2022-05-27 应用材料公司 提高选择性外延生长的生长速率的方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090111246A1 (en) * 2007-10-26 2009-04-30 Asm America, Inc. Inhibitors for selective deposition of silicon containing films

Also Published As

Publication number Publication date
TW201839798A (zh) 2018-11-01
US10504723B2 (en) 2019-12-10
US20180190489A1 (en) 2018-07-05
WO2018128789A1 (en) 2018-07-12
KR102480359B1 (ko) 2022-12-21
KR20190095325A (ko) 2019-08-14

Similar Documents

Publication Publication Date Title
TWI741121B (zh) 用於選擇性磊晶之方法及設備
JP5661083B2 (ja) エピタキシャル膜を形成する方法、及び、エピタキシャル膜の形成に使用するためのクラスターツール
US10199211B2 (en) Atomic layer deposition of silicon carbon nitride based materials
JP5090451B2 (ja) 炭素含有シリコンエピタキシャル層の形成方法
US9171718B2 (en) Method of epitaxial germanium tin alloy surface preparation
US8445389B2 (en) Etchant treatment processes for substrate surfaces and chamber surfaces
US7588980B2 (en) Methods of controlling morphology during epitaxial layer formation
JP2009543357A (ja) エピタキシーチャンバにおける基板の予備洗浄
KR100938301B1 (ko) 기판 표면 및 챔버 표면을 위한 식각액 처리 공정
JP2987926B2 (ja) 気相成長方法
JP2024524999A (ja) 新規の酸化剤及び歪環前駆体