TWI740678B - 完全互連之異質多層的經重建矽裝置 - Google Patents

完全互連之異質多層的經重建矽裝置 Download PDF

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TWI740678B
TWI740678B TW109135438A TW109135438A TWI740678B TW I740678 B TWI740678 B TW I740678B TW 109135438 A TW109135438 A TW 109135438A TW 109135438 A TW109135438 A TW 109135438A TW I740678 B TWI740678 B TW I740678B
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dies
die
reconstructed
3dic
package level
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TW109135438A
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TW202117950A (zh
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軍 翟
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美商蘋果公司
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Abstract

描述經重建3DIC結構及製造方法。在一實施例中，在3DIC之各封裝級中的一或更多晶粒係功能晶片及/或拼接裝置以用於一相鄰封裝級中的兩或更多晶粒。因此，除了執行單獨的晶片核心功能之外，各晶粒可作用為兩個其他晶粒/小晶片之間的通訊橋。

Description

完全互連之異質多層的經重建矽裝置
本文描述之實施例係關於積體電路(integrated circuit, IC)製造及多個晶粒之互連。
多晶片模組(multi-chip module, MCM)通常係將多個晶粒整合在基材上的電子總成。MCM的各種實施方案包括2D、2.5D、及3D封裝。一般而言，2D封裝模組包括並排配置在封裝基材上的多個晶粒。在2.5D封裝技術中，多個晶粒及接合至具有微凸塊的中介層。然後該中介層繼而接合至封裝基材。該中介層可包括佈線以使相鄰晶粒互連。因此，2.5D封裝中的晶粒可直接連接至中介層，並透過中介層內的佈線彼此連接。一般而言，3D封裝模組包括垂直堆疊在彼此之上的多個晶粒。因此，3D封裝中的晶粒可直接彼此連接，其中底部晶粒直接連接至封裝基材。3D封裝中的頂部晶粒可使用各種組態（包括打線、及通過底部晶粒之穿矽通孔(through-silicon via, TSV)）連接至封裝基材。
3D封裝技術之一子集包括3D堆疊式積體電路（或稱3DIC），其係指使用穿矽通孔(TSV)之IC晶片堆疊。3DIC的傳統堆疊方式包括晶粒對晶粒堆疊(die-to-die stacking)、隨後進行單切(singulation)的晶粒對晶圓堆疊(die-to-wafer stacking)、及隨後進行單切的晶圓對晶圓堆疊(wafer-to-wafer stacking)。在各個情況中，習知的3DIC封裝方式假設底部晶粒係用於最終3DIC封裝的超集合足跡(super-set footprint)。
描述經重建3DIC結構及製造方法。在一實施例中，經重建3DIC包括一第一封裝級及一第二封裝級，該第一封裝級包括第一複數個晶粒，該第二封裝級包括接合至該第一封裝級的第二複數個晶粒。存在一通訊路徑，其在該第一封裝級與該第二封裝級之間上下行進，其中在該第一複數個晶粒中之一或多個晶粒之一第一群組作用為功能晶粒及拼接裝置以用於該第二複數個晶粒之兩者或更多者，且在該第二複數個晶粒中之一或多個晶粒之一第二群組作用為功能晶粒及拼接裝置以用於該第一複數個晶粒之兩者或更多者。
在一實施例中，製造經重建3DIC之方法包括將第二複數個晶粒接合至一第一經重建晶圓，該第一經重建晶圓包括嵌入於一第一間隙填充材料中之第一複數個晶粒。在一實施例中，可利用混合接合(hybrid bonding)將該第二複數個晶粒接合至該第一經重建晶圓。例如，接合可以是晶圓至晶圓上的(wafer-on-wafer)，其中該第二複數個晶粒係在一第二經重建晶圓中，或可以是晶片至晶圓上的(chip-on-wafer)，其中該第二複數個晶粒是離散的，且在混合接合之後，隨後施加一第二間隙填充材料於該第二複數個晶粒周圍。
[相關申請案之交互參照]
本申請案主張於2019年10月24日申請之美國臨時專利申請案序號第62/925,562號之優先權，其全文揭示以引用方式併入本文中。
實施例描述3DIC結構，其中各封裝級之晶粒係功能晶片及/或拼接裝置以用於一相鄰封裝級之兩個或更多晶粒。因此，除了執行單獨的晶片核心功能之外，各晶粒可作用為兩個其他晶粒/小晶片(chiplet)之間的通訊橋。例示性晶片核心功能包括運算（例如中央處理單元、一般處理單元）、記憶體（靜態隨機存取記憶體(static random-access memory, SRAM)、動態隨機存取記憶體(dynamic random-access memory, DRAM)、磁阻式隨機存取記憶體(magnetoresistive random-access memory, MRAM)等）、類比/混合信號（輸入/輸出(I/O)、功率放大器(power amplifier, PA)、射頻(radio frequency, RF)、實體層(physical layer, PHY)等）。以此方式，晶粒可在所有的封裝級上所有晶粒之間形成完整的3DIC互連架構(interconnect fabric)。被動矽中介層拼接晶粒亦可包括於晶粒互連架構內。
在一態樣中，已觀察到，使用習知的3DIC封裝方式時，底部晶粒是用於最終3DIC封裝的超集合足跡。此外，已知的底部晶粒拼接技術可限制於具有粗互連密度及低產率之主動晶粒中的被動矽中介層或上部金屬層。此外，此類晶粒拼接技術仍可能需要兩倍光罩尺寸(2x reticle size)。相反地，使用根據實施例之3DIC封裝解決方案時，底部晶粒大小並不限制最終足跡。根據實施例之3DIC結構可使用異質主動晶粒以經重建晶圓方式來製造，其中所有晶粒皆為已知良好晶粒，且一通訊路徑（亦即通訊橋路徑）可存在於任何給定之終端對之間。因此，通訊橋可被併入於各個及所有（主動）晶粒內的矽中，其中各晶粒可接合至在一相對封裝級中之一對晶粒，以提供兩晶粒之間的通訊路徑（或晶粒拼接）。此外，可減小晶粒的尺寸。根據許多實施例，晶粒可係小晶片，其中可按所欲將功能性減至最低，例如至智財銀行(IP banks)，但仍包括通訊橋。
在各種實施例中，參照圖式進行說明。然而，某些實施例可在無這些特定細節之一或多者的情況下實行或可與其他已知的方法及組態結合實行。在下列敘述中，為了提供對實施例的全面瞭解而提出眾多特定細節（例如，特定組態、尺寸、及程序等）。在其他例子中，為了避免不必要地使本實施例失焦，所以並未特別詳細地敘述公知的半導體程序及製造技術。此專利說明書通篇指稱的「一實施例(one embodiment)」係指與該實施例一同描述之具體特徵、結構、組態、或特性係包括在至少一實施例中。因此，此專利說明書通篇於各處出現之詞組「在一實施例中(in one embodiment)」不必然指稱相同實施例。此外，在一或多個實施例中，可以任何合適的方式結合特定特徵、結構、組態、或特性。
如本文所用之「在…上方(over)」、「至(to)」、「在…之間(between)」、及「在…上(on)」之用語可指稱一層相對於其他層的相對位置。一層在另一層「上方」或在另一層「上」或接合「至」另一層或與另一層「接觸(contact)」可與另一層直接接觸或可具有一或多個中介層。一層介於（多個）層「之間」可直接與該等層接觸或可具有一或多個中介層。
圖1A係根據一實施例之具有混合接合之經重建3DIC結構100的截面側視圖。圖1B係根據一實施例之具有微凸塊800之經重建3DIC結構100的截面側視圖。圖1C係根據一實施例之包括重分佈層(redistribution layer, RDL) 190及微凸塊800之經重建3DIC結構100的截面側視圖。在以下說明中，應瞭解，可利用混合接合及微凸塊兩者來形成本文所述之經重建3DIC結構。微凸塊800可使用更為習知的總成技術，但是具有金屬-金屬及氧化物-氧化物接合的混合接合可針對較高端的應用達成高連接密度、及較低的延時、以及較小的z高度(z-height)。此外，可包括RDL 190以放寬封裝級之間的墊間距。
如圖所示，經重建3DIC結構100可包括一第一上層封裝級115及一第二下層封裝級125。圖1A至圖1C中僅繪示兩個封裝級，但實施例可延伸至額外的封裝級。如所示，上層封裝級可包括複數個晶粒110、120、130（或小晶片）。複數個晶粒110、120、130之全體或僅一群組可包括通訊橋佈線150，其係用以自一相鄰封裝級連接至少兩晶片。通訊橋佈線150可包括一或多個主動裝置，諸如但不限於中繼器、觸發器(flop)、緩衝器、及電晶體。
如在圖1A中所示，晶粒110、120、130之各者具有面朝下的主動側，其包括複數個接觸墊102及介電（氧化物）層104。在一實施例中，在第一封裝級115中之複數個晶粒110、120、130係嵌入於間隙填充材料106中。例如，此可以是用於混合接合的氧化物，但可使用其他材料，例如矽。
第二封裝級125可類似於第一封裝級115，包括複數個晶粒210、230、240。可選地，中介層小晶片220可包括在封裝級115、125之任一者中。應瞭解，雖然在第一封裝級及第二封裝級繪示三個晶粒，但此僅是用於說明之目的，且可包括任何數目的晶粒。
類似於第一封裝級晶粒110、120、130，第二封裝級晶粒210、230、240，及被動中介層小晶片220可包括面朝上的主動面（朝向第一封裝級115），其包括複數個接觸墊202及一個介電（氧化）層204。複數個晶粒210、230、240之全體或僅一群組可包括通訊橋佈線150，其係用以自一相鄰封裝級連接至少兩晶片。在一實施例中，在第二封裝級125中之複數個晶粒210、230、240係嵌入於間隙填充材料206中。例如，此可以是用於混合接合的氧化物，但可使用其他材料，例如矽。此外，在第二封裝級中之晶粒210、230、240及被動中介層小晶片220之一些或全體可具有延伸至面朝下之背側的一或多個穿矽通孔(through silicon via, TSV) 270。例如，TSV 270可耦合至背側著陸墊272。在一實施例中，銲點凸塊180可係可選地置於背側著陸墊272，其中第二封裝級125係用於安裝至封裝基材上的最低封裝級。TSV 270可提供封裝基材與第二封裝級125之間的電連接。在一實施例中，一或多個穿氧化物通孔(through oxide via, TOV) 275係穿過間隙填充材料206至第一封裝級115而形成。在間隙填充材料206不是氧化物材料的替代實施例中，TOV 275可係可選地以穿模通孔或替代互連來取代。
在一例示性應用中，第一封裝級晶粒組及第二封裝級晶粒組可包括多個小晶片以用於計算（例如中央處理單元、一般處理單元）、記憶體（SRAM、DRAM、MRA等）、類比/混合信號（I/O、PA、RF、PHY等）。以此方式，晶粒可在所有的封裝級上所有晶粒之間形成完整的3DIC互連架構。被動矽中介層拼接晶粒亦可包括於晶粒互連架構內。
在圖1B所繪示之具體實施例中，頂部晶粒210、230、240（且可選地，一或多個被動中介層小晶片220）可使用複數個微凸塊800接合至第一封裝級115。可使用隨後形成間隙填充材料206的晶片至晶圓上的接合技術來個別地接合第一封裝級晶粒110、120、130，或使用晶圓至晶圓上接合技術將第二封裝級晶粒125接合至第一封裝級115。如圖1C所示，RDL 190可係根據實施例可選地形成為第一封裝級115的一部分。RDL 190可橫跨第一封裝級晶粒110、120、150及間隙填充材料106。RDL 190可自第一封裝級115之接觸墊102至第二封裝級125之接觸墊202展開扇出型佈線。RDL可包括一或更多的重分佈線194（例如銅）、介電層192（例如氧化物、聚合物、或其他介電材料）、及著陸墊196，例如用以接收微凸塊800。RDL 190可以可選地使用在介電層192中形成（例如，鑽孔產生）之微通孔198而接觸接觸墊102。
圖2係根據一實施例之流動通過經重建3DIC結構100之多個封裝級一通訊路徑的示意圖。應理解此繪示係例示性的，並且意欲繪示相鄰封裝級之晶粒之間的互連架構。如所示，晶粒之一些或所有者可包括通訊橋佈線150，以自一相鄰封裝級連接至少兩個晶粒。因此，通訊橋佈線150在實行上可將相鄰晶粒拼接在一起。這些互連通訊橋佈線150形成晶粒間(die-to-die)及在相鄰封裝級之晶粒之間的互連架構。
如圖2所示，通訊橋佈線150中之任一者可包括一或多個主動裝置152，諸如中繼器、觸發器、緩衝器、及/或電晶體。如圖所示，亦可將被動中介層小晶片220包括在任一封裝級中，且通訊路徑可行進通過被動中介層小晶片220。在一實施例中，通訊路徑可以可選地包括一或多個收發器154及接收器160，以及序列器156及解除序列器158。應理解，雖然組件係繪示為在特定晶粒內，但組件可依需要分佈於任何晶粒/小晶片中。在所繪示之實施例中，通訊路徑中的終端晶粒不包括通訊橋佈線150。這可以歸因於其中僅單一晶粒對晶粒互連係可用的邊緣位置。在一實施例中，晶粒110對應於一I/O晶粒。在一實施例中，晶粒240對應於一CPU晶粒。
在一實施例中，經重建3DIC100包括第一封裝級115及第二封裝級125，該第一封裝級包括第一複數個晶粒110、120、130，該第二封裝級包括接合至第一封裝級115的第二複數個晶粒210、230、240（及可選的中介層小晶片220）。存在一通訊路徑，其在第一封裝級115與第二封裝級125之間上下行進，其中在該第一複數個晶粒中之一或多個晶粒120、130之一第一群組作用為功能晶粒及拼接裝置以用於該第二複數個晶粒之兩者或更多者，且在該第二複數個晶粒中之一或多個晶粒210、230之一第二群組作用為功能晶粒及拼接裝置以用於該第一複數個晶粒之兩者或更多者。此可包括將晶粒拼接至被動中介層小晶片220。
第一晶粒群組及第二晶粒群組中之各晶粒可包括對應的通訊橋佈線150，通訊路徑透過該通訊橋佈線來延伸。例如，各對應的通訊橋佈線150可以是不同的，並且可包括一或多個主動裝置152，諸如中繼器、觸發器、緩衝器、及電晶體、及其組合。一或多個被動中介層小晶片220可位於第一封裝級115及第二封裝級125之任一者或兩者中，其中通訊路徑行進通過（多個）被動中介層小晶片220。在一實施例中，通訊路徑可進一步包括收發器154及接收器160。
在各種實施例中，可使用複數個微凸塊800（如圖1B至圖1C所示）或混合接合（如圖1A所示）將第二複數個晶粒210、230、240接合至第一封裝級115。氧化物（例如氧化矽）間隙填充材料可進一步促進混合接合。在一實施例中，第一複數個晶粒係嵌入於氧化物間隙填充材料106中。同樣地，第二複數個晶粒可嵌入於第二氧化物間隙填充材料（例如氧化矽）206中，特別是當用於混合接合時。第一氧化物間隙填充材料及第二氧化物間隙填充材料皆可以是相同材料，且可直接接合至一相對封裝級中的晶粒。
在一實施例中，複數個TSV 270延伸穿過第二複數個晶粒210、230、240之至少一部分或全部，及，可選地，被動中介層小晶片220。可將對應的複數個著陸墊272與複數個TSV 270耦合，且複數個銲點凸塊180可以可選地附接至複數個著陸墊272。可視需要在額外封裝級中提供額外的TSV及著陸墊，以用於垂直佈線。
圖3係根據實施例之製造一經重建3DIC結構之方法的流程圖。圖4A至圖4D係根據一實施例之用於形成一經重建晶圓之流程的示意截面側視圖。圖5A至圖5C係根據一實施例之用於形成一經重建3DIC結構之晶片至晶圓上之流程的示意截面側視圖。圖6A至圖6B係根據一實施例之用於形成一經重建3DIC結構之晶圓至晶圓上之流程的示意截面側視圖。為了清楚及簡明起見，在圖3中的流程係與圖4A至圖4D、圖5A至圖5C、及圖6A至圖6B所繪示之流程同時討論。
在操作3010，形成具有底部晶粒的一底部經重建晶圓。例如，可使用繪示於圖4A至圖4D之程序來製造此一底部經重建晶圓。如圖所示，可使用拾取及放置設備將複數個晶粒組410放置在載體基材400上，諸如矽晶圓或剛性玻璃基材。圖4B係安裝在載體基材上的單一晶粒組410的特寫圖，其中各晶粒110、120、130經面朝下安裝。如圖4C所示，接著可將間隙填充材料106沉積在複數個晶粒110、120、130上方。舉例來說，間隙填充材料106可為氧化物材料（例如氧化矽）。形成氧化物間隙填充的例示性方法包括化學氣相沉積(chemical vapor deposition, CVD)、電漿增強CVD (PECVD)、次大氣壓CVD (SA-CVD)、及選擇性氧化物沉積(selective oxide deposition, SELOX)。
在一替代組態中，間隙填充材料106可由諸如矽之另一材料所形成。矽可以是用於與晶粒熱膨脹匹配的適合材料。用於形成矽間隙填充的例示性方法包括磊晶技術，諸如CVD、PECVD、低壓CVD (LPCVD)、及熱絲CVD，以及濺鍍、矽墨水、矽膏、及電沉積。
如圖4D所示，間隙填充材料106可以可選地經薄化以暴露晶粒，接著將機械支撐基材402附接於晶粒的頂部。例如，此可以是簡單的晶圓至晶圓上之熔合接合(fusion wafer to wafer bond)。
如圖4D所示，接著可將載體基材400移除，以暴露複數個接觸墊102及介電（氧化物）層104。此時，底部經重建晶圓101可包括混合接合表面105，其包括經暴露的接觸墊102、介電（氧化物）層104、及間隙填充材料106。在間隙填充材料106係由氧化物所形成的情況下，間隙填充材料106可在混合接合期間促進氧化物-氧化物接合。RDL 190亦可在此階段形成。在此一實施例中，間隙填充材料106不需要用於混合接合，並且可由各種材料形成，包括聚合物。
再次參照圖3，在操作3020，頂部晶粒及底部經重組晶圓係可選地經條件化以用於混合接合。舉例而言，此可包括氧化（例如經暴露矽之氧化）、氧化層之沉積、清潔經暴露金屬層以移除氧化物等。可使用多種表面處理或薄膜沉積以條件化各種組件以用於混合接合。在操作3030，將圖4D之底部經重建晶圓101翻轉過來，且頂部晶粒210、230、240（且可選地，一或多個被動中介層小晶片220）係混合接合至底部經重建晶圓101，如在圖5A中所示。具體而言，此一處理步驟可以是晶片至晶圓上的接合技術，其中個別組件（晶粒、小晶片）係接合至底部經重建晶圓101。此後可接著在第二複數個晶粒周圍、之間、或可選地上方沉積第二間隙填充材料206。第二間隙填充材料206可由多種材料形成，包括氧化物、矽、及甚至是模制化合物。在一實施例中，一或多個穿氧化物通孔(TOV) 275係穿過間隙填充材料206至底部經重建晶圓101而形成。在間隙填充材料206不是氧化物材料的替代實施例中，TOV 275可係可選地以穿模通孔或替代互連來取代。接著可於TSV 270及TOV 275上形成複數個背側著陸墊272。
參照圖5C，複數個銲點凸塊180可係可選地置於背側著陸墊272上，接著切割個別的3DIC結構100。
現在參照圖6A，在晶圓至晶圓上流程中，在操作3025可形成頂部經重建晶圓201，其具有頂部晶粒210、230、240及可選地一或多個被動中介層小晶片220。頂部經重建晶圓201可以可選地包括一預先形成之TOV 275（或等同物），以及可選的著陸墊272。類似於操作3030，在操作3035，頂部及底部經重建晶圓201、101可以可選地經條件化以用於混合接合表面205、105的混合接合。此後，在操作3045，接著對頂部及底部經重建晶圓201、101進行混合接合。在一替代配置中，可在混合接合之後形成（多個）替代配置TOV及著陸墊272。替代地，如圖1B至圖1C所示，頂部及底部經重建晶圓201、101可與微凸塊800接合。參照圖6B，複數個銲點凸塊180可係可選地置於背側著陸墊172上，接著切割個別的3DIC結構100。
在一實施例中，一種製造經重建3DIC的方法包括將第二複數個晶粒210、230、240接合在第一經重建晶圓101上，該第一經重建晶圓包括嵌入於第一間隙填充材料中之第一複數個晶粒110、120、130。該等晶粒經配置使得通訊路徑在該第一複數個晶粒110、120、130與該第二複數個晶粒210、230、240之間上下行進。在該第一複數個晶粒中之一或多個晶粒120、130之一第一群組作用為功能晶粒及拼接裝置以用於該第二複數個晶粒210、230、240之兩者或更多者。同樣地，在該第二複數個晶粒中之一或多個晶粒210、230之一第二群組作用為功能晶粒及拼接晶粒以用於該第一複數個晶粒110、120、130之兩者或更多者。此亦包括將晶粒拼接至被動中介層小晶片220。如所述，在一實施例中，可利用混合接合將第二複數個晶粒接合至第一經重建晶圓101。例如，接合可以是晶圓至晶圓上的，其中該第二複數個晶粒係在一第二經重建晶圓中，或可以是晶片至晶圓上的，其中該第二複數個晶粒是離散的，且在混合接合之後，隨後施加一第二間隙填充材料於該第二複數個晶粒周圍。
應理解，雖然圖3、圖4A至圖4D、圖5A至圖5C、及圖6A至圖6B已針對混合接合來描述，但可預見的是可利用其他接合技術，諸如圖1B至圖1C所示之微凸塊800。此外，雖然特定程序是以兩個封裝級結束，但可持續進行該程序以加入額外封裝級。
圖7係根據一實施例之多層經重建3DIC結構700的截面側視圖。根據實施例，可持續進行程序以加入額外封裝級，而非在圖5C及圖6B進行切割。在圖7所繪示的具體實施例中，圖5C或圖6B的經重建晶圓可堆疊在彼此之上，並使用諸如混合接合或微凸塊之技術來接合。在所繪示的實施例中，背側TSV著陸墊172、272及間隙填充材料106、206可經混合接合。在所繪示之具體實施例中，經重建3DIC結構包括延伸穿過第一複數個晶粒110、120、130之第一複數個TSV 170。第三複數個晶粒210、230、240（且可選地，被動中介層小晶片220）經混合接合至第一複數個晶粒110、120、130，其例如使用背側TSV著陸墊172、272及間隙填充材料106、206。替代地，可將3DIC結構100與微凸塊接合。同樣地，個別的3DIC結構100內的封裝級可與微凸塊接合，且可選地可包括一或多個RDL。
在使用實施例的各種態樣的過程中，所屬技術領域中具有通常知識者將明白上述實施例的組合或變化對於形成經重建3D結構而言係可行的。雖然已經以結構特徵及/或方法動作之特定語言敘述實施例，應了解附加的申請專利範圍不必受限於所述的特定特徵或行為。替代地，所揭示之特定的特徵及動作應理解為可用於說明之申請專利範圍的實施例。
參考表
101 經重建晶圓
102 接觸墊
106 間隙填充材料
115 第一封裝級
120 晶粒
125 第二封裝級
130 晶粒
150 通訊橋佈線
154 收發器
172 著陸墊
201 經重建晶圓
206 間隙填充材料
210 晶粒
220 中介層小晶片
230 晶粒
240 晶粒
272 著陸墊
275 穿氧化物通孔(TOV)
410 晶粒組
100:3DIC結構 101:底部經重建晶圓/第一經重建晶圓 102:接觸墊 104:介電（氧化物）層 105:混合接合表面 106:間隙填充材料 110:晶粒 115:第一上層封裝級/第一封裝級 120:晶粒 125:第二下層封裝級/第二封裝級 130:晶粒 150:通訊橋佈線/第一封裝級晶粒 152:主動裝置 154:收發器 156:序列器 158:解除序列器 160:接收器 170:TSV 172:著陸墊 180:銲點凸塊 190:重分佈層(redistribution layer, RDL) 192:介電層 194:重分佈線 196:著陸墊 198:微通孔 201:頂部經重建晶圓 202:接觸墊 204:介電（氧化）層 205:混合接合表面 206:間隙填充材料 210:晶粒 220:中介層小晶片 230:晶粒 240:晶粒 270:穿矽通孔(through silicon via, TSV)/TSV 272:著陸墊 275:穿氧化物通孔(through oxide via, TOV)/TOV 400:載體基材 402:機械支撐基材 410:晶粒組 700:多層經重建3DIC結構 800:微凸塊 3010-3045:步驟
〔圖1A〕係根據一實施例之具有混合接合之一經重建3DIC結構的截面側視圖。 〔圖1B〕至〔圖1C〕係根據一實施例之具有微凸塊之一經重建3DIC結構的截面側視圖。 〔圖2〕係根據一實施例之流動通過一經重建3DIC結構之多個封裝級的一通訊路徑的示意圖。 〔圖3〕係根據實施例之製造一經重建3DIC結構之方法的流程圖。 〔圖4A〕至〔圖4D〕係根據一實施例之用於形成一經重建晶圓之流程的示意截面側視圖。 〔圖5A〕至〔圖5C〕係根據一實施例之用於形成一經重建3DIC結構之晶片至晶圓上之流程的示意截面側視圖。 〔圖6A〕至〔圖6B〕係根據一實施例之用於形成一經重建3DIC結構之晶圓至晶圓上之流程的示意截面側視圖。 〔圖7〕係根據一實施例之一多層經重建3DIC結構的截面側視圖。
100:3DIC結構
102:接觸墊
104:介電(氧化物)層
106:間隙填充材料
110:晶粒
115:第一上層封裝級/第一封裝級
120:晶粒
125:第二下層封裝級/第二封裝級
130:晶粒
150:通訊橋佈線/第一封裝級晶粒
180:銲點凸塊
202:接觸墊
204:介電(氧化)層
206:間隙填充材料
210:晶粒
220:中介層小晶片
230:晶粒
240:晶粒
270:穿矽通孔(through silicon via,TSV)/TSV
272:著陸墊
275:穿氧化物通孔(through oxide via,TOV)/TOV

Claims (17)

  1. 一種經重建之三維積體電路(three dimensional integrated circuit,3DIC)結構，其包含：一第一封裝級，其包括第一複數個晶粒；一第二封裝級，其包括接合至該第一封裝級的第二複數個晶粒；及一通訊路徑，其在該第一封裝級與該第二封裝級之間上下行進，其中在該第一複數個晶粒中之一或多個晶粒之一第一群組作用為功能晶粒及拼接裝置以用於該第二複數個晶粒之兩者或更多者；且在該第二複數個晶粒中之一或多個晶粒之一第二群組作用為功能晶粒及拼接裝置以用於該第一複數個晶粒之兩者或更多者；及其中在該第一晶粒群組及該第二晶粒群組中之各晶粒包括一對應通訊橋佈線，該通訊路徑透過該對應通訊橋佈線來延伸；延伸穿過該第二複數個晶粒之複數個穿矽通孔(through silicon via,TSV)；複數個著陸墊，其與該複數個TSV耦合；及複數個銲點凸塊，其附接至該複數個著陸墊。
  2. 如請求項1之經重建3DIC結構，其中一通訊橋佈線包括一或多個主動裝置，其係選自由一中繼器、一觸發器、一緩衝器、及一電晶體組成的群組。
  3. 如請求項2之經重建3DIC結構，其進一步包含在該第一封裝級或該第二封裝級中的一被動中介層小晶片，其中該通訊路徑行進通過該被動中介層小晶片。
  4. 如請求項2之經重建3DIC結構，其中該通訊路徑進一步包含一收發器及一接收器。
  5. 如請求項1之經重建3DIC結構，其中該第二複數個晶粒係以複數個微凸塊接合至該第一封裝級。
  6. 如請求項5之經重建3DIC結構，其中該第二複數個晶粒係以該複數個微凸塊接合至該第一封裝級之一重分佈層。
  7. 如請求項1之經重建3DIC結構，其中該第二複數個晶粒係混合接合至該第一封裝級。
  8. 如請求項7之經重建3DIC結構，其中該第二複數個晶粒混合接合至該第一複數個晶粒。
  9. 如請求項8之經重建3DIC結構，其中該第一複數個晶粒係嵌入於一氧化物間隙填充材料中。
  10. 如請求項9之經重建3DIC結構，其中該第二複數個晶粒係嵌入於一第二氧化物間隙填充材料中，且該氧化物間隙填充材料及該第二氧化物間隙填充材料係一相同材料。
  11. 如請求項1之經重建3DIC結構，其進一步包含延伸穿過該第一複數個晶粒之第一複數個TSV。
  12. 如請求項11之經重建3DIC結構，其進一步包含混合接合至該第一複數個晶粒之第三複數個晶粒。
  13. 一種製造一經重建之三維積體電路(3DIC)結構的方法，其包含： 將第二複數個晶粒接合至一第一經重建晶圓上，該第一經重建晶圓包括嵌入於一第一間隙填充材料中之第一複數個晶粒，其中該第二複數個晶粒包含延伸穿過該第二複數個晶粒之複數個穿矽通孔(through silicon via,TSV)；其中一通訊路徑在該第一複數個晶粒與該第二複數個晶粒之間上下行進，其中在該第一複數個晶粒中之一或多個晶粒之一第一群組作用為功能晶粒及拼接裝置以用於該第二複數個晶粒之兩者或更多者；且在該第二複數個晶粒中之一或多個晶粒之一第二群組作用為功能晶粒及拼接裝置以用於該第一複數個晶粒之兩者或更多者；其中在該第一晶粒群組及該第二晶粒群組中之各晶粒包括一對應通訊橋佈線，該通訊路徑透過該對應通訊橋佈線來延伸；以及放置複數個銲點凸塊於複數個著陸墊，該複數個著陸墊與該複數個TSV耦合。
  14. 如請求項13之方法，其中將該第二複數個晶粒接合至該第一經重建晶圓包含混合接合。
  15. 如請求項14之方法，其中將該第二複數個晶粒接合至該第一經重建晶圓包含將一第二經重建晶圓混合接合至該第一經重建晶圓。
  16. 如請求項14之方法，其進一步包含在將該第二複數個晶粒混合接合至該第一經重建晶圓之後，施加一第二間隙填充材料於該第二複數個晶粒周圍。
  17. 如請求項13之方法，其中將該第二複數個晶粒接合至該第一經重建晶圓包含以複數個微凸塊將該第二複數個晶粒接合至該第一經重建晶圓之一重分佈層。
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