TWI737087B - Semicoudcutor structure and manufacturing method therefore - Google Patents

Abstract

A semiconductor structure including a substrate, a dielectric layer, a capacitor structure, and a wire. The dielectric layer is located on the substrate. The capacitor structure includes a first electrode, an insulating layer, a second electrode, and a spacer. The first electrode is located on the dielectric layer. The insulating layer is located on the first electrode. The second electrode is located on the insulating layer. The spacer covers a sidewall of the first electrode. The wire is located on the dielectric layer on one side of the capacitor structure.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure and a manufacturing method thereof that can improve the electrical performance of a capacitor.

In today's semiconductor industry, capacitors are very important basic components. For example, a metal-insulator-metal (MIM) capacitor is a common capacitor structure. Its basic design is to insert an insulating material between the metal plates as electrodes, so that two adjacent The metal plate and the insulating material between them can form a capacitor unit. However, how to effectively improve the electrical performance of the capacitor is the current goal of the industry's continuous efforts.

The invention provides a semiconductor structure and a manufacturing method thereof, which can improve the electrical performance of a capacitor.

The present invention provides a semiconductor structure, including a substrate, a dielectric layer, and a capacitor Device structure and wire. The dielectric layer is located on the substrate. The capacitor structure includes a first electrode, an insulating layer, a second electrode and a spacer. The first electrode is located on the dielectric layer. The insulating layer is located on the first electrode. The second electrode is located on the insulating layer. The gap wall covers the side wall of the first electrode. The wires are located on the dielectric layer on one side of the capacitor structure.

According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the material of the first electrode may be a metal material that does not contain aluminum.

According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the spacer can further cover the sidewall of the insulating layer.

According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the width of the first electrode may be greater than the width of the second electrode.

According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the wire and the second electrode may be composed of the same conductor layer.

The present invention provides a method for manufacturing a semiconductor structure, which includes the following steps. A dielectric layer is formed on the substrate. A capacitor structure is formed on the dielectric layer. The capacitor structure includes a first electrode, an insulating layer, a second electrode and a spacer. The first electrode is located on the dielectric layer. The insulating layer is located on the first electrode. The second electrode is located on the insulating layer. The gap wall covers the side wall of the first electrode. A wire is formed on the dielectric layer on one side of the capacitor structure. The second electrode and the wire are simultaneously formed by the same manufacturing process.

According to an embodiment of the present invention, in the method for manufacturing the semiconductor structure described above, the method for forming the first electrode and the insulating layer may include the following steps. A first electrode material layer is formed on the dielectric layer. An insulating material layer is formed on the first electrode material layer. The insulating material layer and the first electrode material layer are patterned.

According to an embodiment of the present invention, in the manufacturing method of the semiconductor structure described above, the spacer can further cover the sidewall of the insulating layer.

According to an embodiment of the present invention, in the method for manufacturing the semiconductor structure described above, the method for forming the spacer may include the following steps. A spacer material layer covering the insulating layer and the first electrode is formed. Perform an etching back process on the spacer material layer.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned semiconductor structure, the following steps may be further included. After performing an etch-back process on the spacer material layer, a sputter etching process is performed.

According to an embodiment of the present invention, in the method for manufacturing the semiconductor structure described above, the method for forming the second electrode and the wire may include the following steps. A conductor layer is formed on the dielectric layer, the insulating layer and the spacer. The conductive layer and the first electrode can be isolated from each other by the insulating layer and the spacer. The conductive layer is patterned to form wires on the dielectric layer, and at the same time, a second electrode is formed on the insulating layer.

Based on the above, in the semiconductor structure and its manufacturing method proposed by the present invention, the spacer covers the sidewall of the first electrode. Therefore, in the process of forming the first electrode and then forming the second electrode, the spacer can prevent the first electrode from A short circuit with the second electrode further enhances the electrical performance of the capacitor. In addition, in the manufacturing method of the semiconductor structure proposed in the present invention, the second electrode and the wire can be formed at the same time by the same manufacturing process, thereby reducing the complexity of the manufacturing process. In addition, in the manufacturing method of the semiconductor structure proposed in the present invention, since the first electrode and the wire are formed by different manufacturing processes, the material of the first electrode can be optimized separately to improve the breakdown voltage and reliability of the capacitor , And then improve the electrical performance of the capacitor.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10: Semiconductor structure

100: base

102: Dielectric layer

104: electrode material layer

104a: Electrode

106: insulating material layer

106a: insulating layer

108, 118: patterned photoresist layer

110: spacer material layer

110a: interstitial wall

112: barrier material layer

112a, 112b: barrier layer

114: Conductor layer

114a: Electrode

114b: Wire

116: anti-reflective material layer

116a, 116b: anti-reflection layer

120: Capacitor structure

200: Sputter etching process

1A to 1G are cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.

1A to 1G are cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.

1A, a dielectric layer 102 is formed on the substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, according to product requirements, required semiconductor elements (eg, transistors, etc.) (not shown) can be formed on the substrate 100. The dielectric layer 102 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 102 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The method for forming the dielectric layer 102 is, for example, a chemical vapor deposition method. In addition, according to product requirements, a required interconnection structure (not shown) can be formed in the dielectric layer 102, and the interconnection structure can be electrically connected to a corresponding semiconductor device.

Next, an electrode material layer 104 is formed on the dielectric layer 102. The electrode material layer 104 can be used to make the bottom electrode of the capacitor. The material of the electrode material layer 104 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. Electrode material layer The formation method of 104 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

In some embodiments, the material of the electrode material layer 104 may be a metal material that does not contain aluminum. In the case where the material of the lower electrode of the capacitor contains aluminum, since the grains of aluminum are large, the roughness of the upper surface of the lower electrode will increase. As a result, the quality of the insulating layer subsequently formed on the upper surface of the lower electrode will be poor, which will result in a decrease in the breakdown voltage and reliability of the capacitor, which will result in poor electrical performance of the capacitor. In this embodiment, when the material of the electrode material layer 104 is a metal material that does not contain aluminum, the material of the electrode material layer 104 (for example, Ti, TiN, Ta, TaN or a combination thereof) may have a smaller crystallinity. Therefore, the electrode material layer 104 can have a relatively flat upper surface, so that the insulating material layer subsequently formed on the electrode material layer 104 can have better quality, thereby increasing the breakdown voltage and reliability of the capacitor, thereby improving The electrical performance of the capacitor.

Then, an insulating material layer 106 is formed on the electrode material layer 104. The material of the insulating material layer 106 is, for example, silicon nitride, silicon oxide, silicon oxide/silicon nitride-oxide (ONO), high-k material (high-k material), or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), or a combination thereof. The method of forming the insulating material layer 106 is, for example, a chemical vapor deposition method.

Next, a patterned photoresist layer 108 is formed on the insulating material layer 106. The patterned photoresist layer 108 can be formed by a photolithography process.

1B, using the patterned photoresist layer 108 as a mask, a part of the insulating material layer 106 and a part of the electrode material layer 104 are removed. With this, the insulating material layer can be 106 and the electrode material layer 104 are patterned, an electrode 104a is formed on the dielectric layer 102, and an insulating layer 106a is formed on the electrode 104a. The electrode 104a can be used as the lower electrode of the capacitor. The method for removing part of the insulating material layer 106 and part of the electrode material layer 104 is, for example, a dry etching method. In this embodiment, although the method for forming the electrode 104a and the insulating layer 106a is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

Referring to FIG. 1C, the patterned photoresist layer 108 is removed. The removal method of the patterned photoresist layer 108 is, for example, dry stripping or wet stripping.

Next, a spacer material layer 110 covering the insulating layer 106a and the electrode 104a is formed. The material of the spacer material layer 110 is, for example, silicon oxide or silicon nitride. The formation method of the spacer material layer 110 is, for example, a chemical vapor deposition method.

1D, an etch-back process is performed on the spacer material layer 110 to form a spacer 110a covering the sidewall of the electrode 104a. In addition, the spacer 110a can further cover the sidewall of the insulating layer 106a. The above-mentioned etch-back process is, for example, a dry etching process. In this embodiment, although the method for forming the spacer 110a is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

In addition, after the etch-back process is performed on the spacer material layer 110, the sputter etching process 200 may be selectively performed to perform surface cleaning treatment. The above-mentioned sputter etching process 200 is, for example, an argon sputter etching process (Ar sputter etching).

1E, a barrier material layer 112 may be formed on the insulating layer 106a and the spacer 110a. The material of the barrier material layer 112 is, for example, Ti, TiN, Ta, TaN Or a combination. The formation method of the barrier material layer 112 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

Next, a conductive layer 114 is formed on the dielectric layer 102, the insulating layer 106a, and the spacer 110a. For example, the conductive layer 114 may be formed on the barrier material layer 112. The conductive layer 114 and the electrode 104a can be isolated from each other by the insulating layer 106a and the spacer 110a, so as to prevent the conductive layer 114 and the electrode 104a from being short-circuited. The material of the conductor layer 114 is, for example, aluminum copper alloy (AlCu) or aluminum. The formation method of the conductor layer 114 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

Then, an anti-reflective material layer 116 may be formed on the conductor layer 114. The material of the anti-reflective material layer 116 is, for example, Ti, TiN, Ta, TaN or a combination thereof. The method for forming the anti-reflective material layer 116 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

Next, a patterned photoresist layer 118 is formed on the anti-reflective material layer 116. The patterned photoresist layer 118 can be formed by a photolithography process.

1F, using the patterned photoresist layer 118 as a mask, a part of the anti-reflective material layer 116, a part of the conductive layer 114, and a part of the barrier material layer 112 are removed. Thereby, the anti-reflective material layer 116, the conductive layer 114, and the barrier material layer 112 can be patterned to form the anti-reflective layer 116a, the anti-reflective layer 116b, the electrode 114a, the wire 114b, the barrier layer 112a, and the barrier layer 112b. . In this way, the wire 114b can be formed on the dielectric layer 102, and the electrode 114a can be formed on the insulating layer 106a at the same time. The method for removing the part of the anti-reflective material layer 116, the part of the conductor layer 114 and the part of the barrier material layer 112 is, for example, a dry etching method. In this embodiment, although the method for forming the electrode 104a and the insulating layer 106a is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

In this way, the capacitor structure 120 can be formed on the dielectric layer 102. The capacitor structure 120 is, for example, a MIM capacitor structure. In addition, a wire 114b may be formed on the dielectric layer 102 on one side of the capacitor structure 120. The electrode 114a and the wire 114b are simultaneously formed by the same process, thereby reducing the process complexity. That is, the wire 114b and the electrode 114a may be formed of the same conductor layer 114.

The capacitor structure 120 includes an electrode 104a, an insulating layer 106a, an electrode 114a, and a spacer 110a. In addition, the capacitor structure 120 may further include at least one of the barrier layer 112a and the anti-reflection layer 116a. The electrode 104 a is located on the dielectric layer 102. The electrode 104a can be used as the lower electrode of the capacitor structure 120. The material of the electrode 104a may be a metal material that does not contain aluminum. The insulating layer 106a is located on the electrode 104a. The electrode 114a is located on the insulating layer 106a. The electrode 114a can serve as the upper electrode of the capacitor structure 120. The width of the electrode 104a may be greater than the width of the electrode 114a, which facilitates subsequent formation of an interconnection structure (such as a contact window) electrically connected to the electrode 104a. The spacer 110a covers the sidewall of the electrode 104a, and can further cover the sidewall of the insulating layer 106a. Since the spacer 110a covers the sidewall of the electrode 104a, in the process of forming the electrode 104a first and then forming the electrode 114a, the spacer 110a can prevent the electrode 104a and the electrode 114a from being short-circuited, thereby improving the electrical performance of the capacitor. The barrier layer 112a is located between the electrode 114a and the insulating layer 106a. The anti-reflection layer 116a is located on the electrode 114a.

In addition, the wire 114 b is located on the dielectric layer 102 on one side of the capacitor structure 120. Since the electrode 104a and the wire 114b are formed by different manufacturing processes, the material of the electrode 104a can be individually optimized to improve the breakdown voltage and reliability of the capacitor, thereby improving the electrical performance of the capacitor. The barrier layer 112b is located on the wire 114b Between and the dielectric layer 102. The anti-reflection layer 116b is located on the wire 114b.

Referring to FIG. 1G, the patterned photoresist layer 118 is removed. The removal method of the patterned photoresist layer 118 is, for example, a dry photoresist removal method or a wet photoresist removal method.

In addition, the semiconductor structure 10 can be formed by the above-mentioned method. The semiconductor structure 10 includes a substrate 100, a dielectric layer 102, a capacitor structure 120, and wires 114b. The dielectric layer 102 is located on the substrate 100, and the capacitor structure 120 and the wire 114 b are located on the dielectric layer 102. In addition, the semiconductor structure 10 may further include at least one of the barrier layer 112b and the anti-reflection layer 116b. In addition, the materials, arrangement methods, forming methods and effects of the components in the semiconductor structure 10 have been described in detail in the above-mentioned embodiments, and the description will not be repeated here. In this embodiment, although the method for forming the semiconductor structure 10 is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

Based on the above embodiments, in the semiconductor structure 10 and its manufacturing method, since the spacer 110a covers the sidewall of the electrode 104a, the spacer 110a can prevent the electrode 104a and the electrode 114a from forming the electrode 104a before forming the electrode 114a. In the event of a short circuit, the electrical performance of the capacitor is improved. In addition, in the manufacturing method of the semiconductor structure 10, the electrode 114a and the wire 114b can be formed at the same time by the same process, thereby reducing the process complexity. In addition, in the manufacturing method of the semiconductor structure 10, since the electrode 104a and the wire 114b are formed by different processes, the material of the electrode 104a can be individually optimized to increase the breakdown voltage and reliability of the capacitor, thereby improving the capacitor's performance. Electrical performance.

In summary, with the semiconductor structure and the manufacturing method of the foregoing embodiment, the electrical performance of the capacitor can be effectively improved and the manufacturing process complexity can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10: Semiconductor structure

100: base

102: Dielectric layer

104a: Electrode

106a: insulating layer

110a: interstitial wall

112a, 112b: barrier layer

114a: Electrode

114b: Wire

116a, 116b: anti-reflection layer

120: Capacitor structure

Claims (9)

A semiconductor structure includes: a substrate; a dielectric layer located on the substrate; a capacitor structure including: a first electrode located on the dielectric layer; an insulating layer located on the first electrode; Two electrodes located on the insulating layer; and spacers covering the sidewalls of the first electrode; and a wire located on the dielectric layer on one side of the capacitor structure, wherein the wire and the The second electrode is composed of the same conductor layer. According to the semiconductor structure described in claim 1, wherein the material of the first electrode is a metal material that does not contain aluminum. According to the semiconductor structure described in claim 1, wherein the spacers further cover the sidewalls of the insulating layer. According to the semiconductor structure described in claim 1, wherein the width of the first electrode is greater than the width of the second electrode. A method for manufacturing a semiconductor structure includes: forming a dielectric layer on a substrate; forming a capacitor structure on the dielectric layer, wherein the capacitor structure includes: a first electrode located on the dielectric layer; an insulating layer , Located on the first electrode; A second electrode located on the insulating layer; and spacers covering the sidewall of the first electrode; and a wire is formed on the dielectric layer on one side of the capacitor structure, wherein the second electrode The wires are formed simultaneously by the same process, wherein the method for forming the second electrode and the wires includes: forming a conductive layer on the dielectric layer, the insulating layer and the spacer, wherein the The conductive layer and the first electrode are isolated from each other by the insulating layer and the spacer; and the conductive layer is patterned to form the wire on the dielectric layer, and at the same time The second electrode is formed on the insulating layer. The method for manufacturing a semiconductor structure according to the fifth item of the scope of patent application, wherein the method for forming the first electrode and the insulating layer includes: forming a first electrode material layer on the dielectric layer; Forming an insulating material layer on an electrode material layer; and patterning the insulating material layer and the first electrode material layer. According to the method for manufacturing a semiconductor structure as described in item 5 of the scope of patent application, the spacer further covers the sidewall of the insulating layer. According to the manufacturing method of the semiconductor structure described in claim 7, wherein the method of forming the spacer includes: forming a spacer material layer covering the insulating layer and the first electrode; and applying the spacer to the spacer The material layer undergoes an etch-back process. As described in item 8 of the scope of patent application, the manufacturing method of the semiconductor structure further includes: performing a sputtering etching process after performing an etch-back process on the spacer material layer.

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