CN113013331B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN113013331B CN113013331B CN202010004398.1A CN202010004398A CN113013331B CN 113013331 B CN113013331 B CN 113013331B CN 202010004398 A CN202010004398 A CN 202010004398A CN 113013331 B CN113013331 B CN 113013331B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000003990 capacitor Substances 0.000 claims abstract description 49
- 125000006850 spacer group Chemical group 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 46
- 239000007772 electrode material Substances 0.000 claims description 20
- 239000011810 insulating material Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 153
- 230000004888 barrier function Effects 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 230000003667 anti-reflective effect Effects 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The dielectric layer is disposed on the substrate. The capacitor structure includes a first electrode, an insulating layer, a second electrode and a spacer. The first electrode is located on the dielectric layer. The insulating layer is positioned on the first electrode. The second electrode is positioned on the insulating layer. The spacer covers the sidewall of the first electrode. The conductive line is located on the dielectric layer on one side of the capacitor structure.
Description
Technical Field
The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure capable of improving electrical performance of a capacitor and a method for fabricating the same.
Background
Capacitors are a fundamental element of considerable importance in the semiconductor industry today. For example, a metal-insulator-metal (MIM) capacitor is a common capacitor structure that is basically designed to insert an insulating material between metal plates as electrodes, so that two adjacent metal plates and the insulating material located therebetween can form one capacitor unit. However, how to effectively improve the electrical performance of the capacitor is a goal of continuous efforts in the industry.
Disclosure of Invention
The invention provides a semiconductor structure and a manufacturing method thereof, which can improve the electrical performance of a capacitor.
The invention provides a semiconductor structure, which comprises a substrate, a dielectric layer, a capacitor structure and a wire. The dielectric layer is disposed on the substrate. The capacitor structure includes a first electrode, an insulating layer, a second electrode and a spacer. The first electrode is located on the dielectric layer. The insulating layer is positioned on the first electrode. The second electrode is positioned on the insulating layer. The spacer covers the sidewall of the first electrode. The conductive line is located on the dielectric layer on one side of the capacitor structure.
In an embodiment of the present invention, in the semiconductor structure, a material of the first electrode may be a metal material containing no aluminum.
In an embodiment of the present invention, in the semiconductor structure, the spacer may further cover a sidewall of the insulating layer.
In an embodiment of the present invention, in the semiconductor structure, a width of the first electrode may be greater than a width of the second electrode.
In an embodiment of the present invention, in the semiconductor structure, the conductive line and the second electrode may be formed of the same conductive layer.
The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps. A dielectric layer is formed on a substrate. A capacitor structure is formed on the dielectric layer. The capacitor structure includes a first electrode, an insulating layer, a second electrode and a spacer. The first electrode is located on the dielectric layer. The insulating layer is positioned on the first electrode. The second electrode is positioned on the insulating layer. The spacer covers the sidewall of the first electrode. A conductive line is formed on the dielectric layer on one side of the capacitor structure. The second electrode and the wire are formed simultaneously by the same manufacturing process.
In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the method for forming the first electrode and the insulating layer may include the following steps. A first electrode material layer is formed on the dielectric layer. An insulating material layer is formed on the first electrode material layer. The insulating material layer and the first electrode material layer are patterned.
In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the spacer may further cover a sidewall of the insulating layer.
In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the method for forming the spacer may include the following steps. A spacer material layer is formed to cover the insulating layer and the first electrode. And performing back etching manufacturing process on the spacer material layer.
According to an embodiment of the present invention, the method for manufacturing a semiconductor structure may further include the following steps. After the spacer material layer is subjected to the etching back process, a sputter etching process (sputtering etching) is performed.
In an embodiment of the present invention, in the method for manufacturing a semiconductor structure, the method for forming the second electrode and the conductive line may include the following steps. A conductive layer is formed on the dielectric layer, the insulating layer and the spacer. The conductor layer and the first electrode may be isolated from each other by an insulating layer and a spacer. The conductor layer is patterned to form a conductive line on the dielectric layer and a second electrode on the insulating layer at the same time.
Based on the above, in the semiconductor structure and the manufacturing method thereof provided by the present invention, since the spacer covers the sidewall of the first electrode, the spacer can prevent the first electrode and the second electrode from being shorted in the manufacturing process of forming the first electrode and then forming the second electrode, thereby improving the electrical performance of the capacitor. In addition, in the method for manufacturing the semiconductor structure provided by the invention, the second electrode and the wire can be formed simultaneously through the same manufacturing process, so that the complexity of the manufacturing process can be reduced. In addition, in the method for manufacturing the semiconductor structure provided by the invention, the first electrode and the conducting wire are formed by different manufacturing processes, so that the material of the first electrode can be independently optimized to improve the breakdown voltage and the reliability of the capacitor, and further improve the electrical performance of the capacitor.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1G are cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present invention.
Symbol description
10: semiconductor structure
100: substrate
102: dielectric layer
104: electrode material layer
104a: electrode
106: insulating material layer
106a: insulating layer
108. 118: patterning a photoresist layer
110: spacer material layer
110a: spacer wall
112: barrier material layer
112a, 112b: barrier material layer
114: conductor layer
114a: electrode
114b: conducting wire
116: anti-reflection material layer
116a, 116b: antireflection layer
120: capacitor structure
200: sputtering etching manufacturing process
Detailed Description
Fig. 1A to 1G are cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1A, a dielectric layer 102 is formed on a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, a desired semiconductor element (e.g., a transistor, etc.) (not shown) may be formed on the substrate 100 according to product requirements. The dielectric layer 102 may have a single-layer structure or a multi-layer structure. The material of the dielectric layer 102 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The dielectric layer 102 is formed by, for example, chemical vapor deposition. In addition, a desired interconnect structure (not shown) may be formed in the dielectric layer 102 according to product requirements, and the interconnect structure may be electrically connected to a corresponding semiconductor device.
Next, an electrode material layer 104 is formed on the dielectric layer 102. The electrode material layer 104 may be used to fabricate the bottom electrode of the capacitor. The material of the electrode material layer 104 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The electrode material layer 104 is formed by physical vapor deposition or chemical vapor deposition, for example.
In some embodiments, the material of the electrode material layer 104 may be a metal material that does not contain aluminum. In the case where the material of the lower electrode of the capacitor contains aluminum, since the grain size (grain) of aluminum is large, the roughness of the upper surface of the lower electrode increases. In this way, the quality of the insulating layer formed on the upper surface of the lower electrode is poor, resulting in reduced breakdown voltage and reliability of the capacitor, and poor electrical performance of the capacitor. In the present embodiment, in the case that the material of the electrode material layer 104 is a metal material containing no aluminum, the material of the electrode material layer 104 (e.g., ti, tiN, ta, taN or a combination thereof) may have smaller grains, so that the electrode material layer 104 may have a relatively flat upper surface, so that the insulating material layer subsequently formed on the electrode material layer 104 may have a relatively good quality, thereby improving the breakdown voltage and reliability of the capacitor, and further improving the electrical performance of the capacitor.
Then, an insulating material layer 106 is formed on the electrode material layer 104. The material of the insulating material layer 106 is, for example, silicon nitride, silicon oxide/nitride/oxide (ONO), a high-k material, or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta) 2 O 5 ) Alumina (Al) 2 O 3 ) Hafnium oxide (HfO) 2 ) Titanium oxide (TiO) 2 ) Zirconium oxide (ZrO) 2 ) Or a combination thereof. The insulating material layer 106 is formed by, for example, chemical vapor deposition.
Next, a patterned photoresist layer 108 is formed over the insulating material layer 106. The patterned photoresist layer 108 may be formed by a photolithographic fabrication process.
Referring to fig. 1B, a portion of the insulating material layer 106 and a portion of the electrode material layer 104 are removed using the patterned photoresist layer 108 as a mask. Thus, the insulating material layer 106 and the electrode material layer 104 may be patterned, the electrode 104a may be formed on the dielectric layer 102, and the insulating layer 106a may be formed on the electrode 104 a. The electrode 104a may serve as a lower electrode of the capacitor. The method for removing the portion of the insulating material layer 106 and the portion of the electrode material layer 104 is, for example, dry etching. In the present embodiment, the method of forming the electrode 104a and the insulating layer 106a is described by way of example, but the invention is not limited thereto.
Referring to fig. 1C, the patterned photoresist layer 108 is removed. The removal method of the patterned photoresist layer 108 is, for example, a dry photoresist stripping method (dry stripping) or a wet stripping method (wet stripping).
Next, a spacer material layer 110 is formed to cover the insulating layer 106a and the electrode 104 a. The material of the spacer material layer 110 is, for example, silicon oxide or silicon nitride. The spacer material layer 110 is formed by, for example, chemical vapor deposition.
Referring to fig. 1D, an etching back process is performed on the spacer material layer 110 to form a spacer 110a covering the sidewall of the electrode 104 a. In addition, the spacer 110a may also cover the sidewall of the insulating layer 106a. The etching back process is, for example, a dry etching process. In the present embodiment, the method of forming the spacer 110a is described by taking the above method as an example, but the invention is not limited thereto.
In addition, after the back etching process is performed on the material layer of the spacer 110a, the sputter etching process 200 may be selectively performed to perform the surface cleaning process. The sputter etch process 200 is, for example, an argon sputter etch process (Ar sputter etching).
Referring to fig. 1E, a barrier material layer 112 may be formed on the insulating layer 106a and the spacers 110a. The material of the barrier material layer 112 is, for example, ti, tiN, ta, taN or a combination thereof. The formation method of the barrier material layer 112 is, for example, physical vapor deposition or chemical vapor deposition.
Next, a conductive layer 114 is formed on the dielectric layer 102, the insulating layer 106a and the spacer 110a. For example, the conductor layer 114 may be formed on the barrier material layer 112. The conductive layer 114 and the electrode 104a may be isolated from each other by the insulating layer 106a and the spacer 110a to prevent the conductive layer 114 and the electrode 104a from being shorted. The material of the conductor layer 114 is, for example, aluminum copper alloy (AlCu) or aluminum. The conductive layer 114 is formed by, for example, physical vapor deposition or chemical vapor deposition.
Then, an anti-reflection material layer 116 may be formed on the conductor layer 114. The material of the anti-reflective material layer 116 is, for example, ti, tiN, ta, taN or a combination thereof. The anti-reflective material layer 116 is formed by physical vapor deposition or chemical vapor deposition, for example.
Next, a patterned photoresist layer 118 is formed over the anti-reflective material layer 116. The patterned photoresist layer 118 may be formed by a photolithographic fabrication process.
Referring to fig. 1F, portions of the anti-reflective material layer 116, the conductive layer 114 and the barrier material layer 112 are removed using the patterned photoresist layer 118 as a mask. Thus, the anti-reflective material layer 116, the conductive layer 114 and the barrier material layer 112 can be patterned to form an anti-reflective layer 116a, an anti-reflective layer 116b, an electrode 114a, a conductive line 114b, a barrier layer 112a and a barrier layer 112b. Thus, the conductive line 114b can be formed on the dielectric layer 102, and the electrode 114a can be formed on the insulating layer 106a at the same time. The partial anti-reflective material layer 116, the partial conductor layer 114 and the partial barrier material layer 112 are removed by dry etching. In the present embodiment, the method of forming the electrode 104a and the insulating layer 106a is described by way of example, but the invention is not limited thereto.
Thus, the capacitor structure 120 may be formed on the dielectric layer 102. The capacitor structure 120 is, for example, a MIM capacitor structure. In addition, a conductive line 114b may be formed on the dielectric layer 102 on one side of the capacitor structure 120. The electrode 114a and the conductive line 114b are formed simultaneously by the same manufacturing process, thereby reducing the complexity of the manufacturing process. That is, the conductive line 114b and the electrode 114a may be formed of the same conductive layer 114.
The capacitor structure 120 includes the electrode 104a, the insulating layer 106a, the electrode 114a and the spacer 110a. In addition, the capacitor structure 120 may further include at least one of a barrier layer 112a and an anti-reflective layer 116 a. An electrode 104a is located on the dielectric layer 102. Electrode 104a may serve as a bottom electrode of capacitor structure 120. The material of the electrode 104a may be a metal material containing no aluminum. An insulating layer 106a is located over the electrode 104 a. Electrode 114a is located on insulating layer 106a. Electrode 114a may serve as the upper electrode of capacitor structure 120. The width of the electrode 104a may be greater than the width of the electrode 114a, thereby facilitating subsequent formation of an interconnect structure (e.g., a contact) electrically connected to the electrode 104 a. The spacers 110a cover sidewalls of the electrode 104a and may also cover sidewalls of the insulating layer 106a. Since the spacer 110a covers the sidewall of the electrode 104a, the spacer 110a can prevent the electrode 104a from shorting with the electrode 114a during the process of forming the electrode 104a and then forming the electrode 114a, thereby improving the electrical performance of the capacitor. The barrier layer 112a is located between the electrode 114a and the insulating layer 106a. An anti-reflective layer 116a is positioned on the electrode 114a.
In addition, the conductive line 114b is located on the dielectric layer 102 on one side of the capacitor structure 120. Since the electrode 104a and the conductive line 114b are formed by different manufacturing processes, the material of the electrode 104a can be optimized independently to improve the breakdown voltage and reliability of the capacitor, thereby improving the electrical performance of the capacitor. Barrier layer 112b is located between conductive line 114b and dielectric layer 102. An anti-reflective layer 116b is over the conductive line 114b.
Referring to fig. 1G, the patterned photoresist layer 118 is removed. The removal method of the patterned photoresist layer 118 is, for example, a dry photoresist removal method or a wet photoresist removal method.
Further, the semiconductor structure 10 may be formed by the above-described method. Semiconductor structure 10 includes a substrate 100, a dielectric layer 102, a capacitor structure 120, and a conductive line 114b. The dielectric layer 102 is disposed on the substrate 100, and the capacitor structure 120 and the conductive line 114b are disposed on the dielectric layer 102. In addition, the semiconductor structure 10 may further include at least one of a barrier layer 112b and an anti-reflective layer 116 b. In addition, materials, arrangement, forming method, and effects of each component in the semiconductor structure 10 are described in detail in the above embodiments, and will not be repeated here. In the present embodiment, the method of forming the semiconductor structure 10 is described by taking the above method as an example, but the invention is not limited thereto.
As can be seen from the above embodiments, in the semiconductor structure 10 and the manufacturing method thereof, the spacer 110a covers the sidewall of the electrode 104a, so that the spacer 110a can prevent the electrode 104a from being shorted with the electrode 114a during the manufacturing process of forming the electrode 104a and then forming the electrode 114a, thereby improving the electrical performance of the capacitor. In addition, in the manufacturing method of the semiconductor structure 10, the electrode 114a and the conductive line 114b can be formed simultaneously by the same manufacturing process, thereby reducing the complexity of the manufacturing process. In addition, in the manufacturing method of the semiconductor structure 10, since the electrode 104a and the conductive line 114b are formed by different manufacturing processes, the material of the electrode 104a can be optimized independently, so as to improve the breakdown voltage and reliability of the capacitor, and further improve the electrical performance of the capacitor.
In summary, through the semiconductor structure and the manufacturing method thereof in the above embodiments, the electrical performance of the capacitor can be effectively improved and the complexity of the manufacturing process can be reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification and variation without departing from the spirit and scope of the present invention.
Claims (9)
1. A semiconductor structure, comprising:
a substrate;
a dielectric layer on the substrate;
a capacitor structure, comprising:
a first electrode on the dielectric layer;
an insulating layer on the first electrode;
a second electrode on the insulating layer; and
a spacer covering the sidewall of the first electrode; and
and the conducting wire is positioned on the dielectric layer at one side of the capacitor structure, wherein the conducting wire and the second electrode are formed by the same conductor layer through the same manufacturing process.
2. The semiconductor structure of claim 1, wherein a material of said first electrode is a metal material free of aluminum.
3. The semiconductor structure of claim 1, wherein said spacer further covers sidewalls of said insulating layer.
4. The semiconductor structure of claim 1, wherein a width of the first electrode is greater than a width of the second electrode.
5. A method of fabricating a semiconductor structure, comprising:
forming a dielectric layer on a substrate;
forming a capacitor structure on the dielectric layer, wherein the capacitor structure comprises:
a first electrode on the dielectric layer;
an insulating layer on the first electrode;
a second electrode on the insulating layer; and
a spacer covering the sidewall of the first electrode; and
forming a conductive line on the dielectric layer at one side of the capacitor structure, wherein the second electrode and the conductive line are simultaneously formed through the same manufacturing process,
the forming method of the second electrode and the lead comprises the following steps:
forming a conductor layer on the dielectric layer, the insulating layer and the spacer, wherein the conductor layer and the first electrode are isolated from each other by the insulating layer and the spacer; and
the conductor layer is patterned to form the conductive lines on the dielectric layer and simultaneously form the second electrodes on the insulating layer.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein the method for forming the first electrode and the insulating layer comprises:
forming a first electrode material layer on the dielectric layer;
forming an insulating material layer on the first electrode material layer; and
patterning the insulating material layer and the first electrode material layer.
7. The method of claim 5, wherein said spacer further covers a sidewall of said insulating layer.
8. The method of claim 7, wherein the forming the spacers comprises:
forming a spacer material layer covering the insulating layer and the first electrode; and
and performing back etching manufacturing process on the spacer material layer.
9. The method of manufacturing a semiconductor structure of claim 8, further comprising:
and performing a sputtering etching manufacturing process after performing an etching back manufacturing process on the spacer material layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108146564A TWI737087B (en) | 2019-12-19 | 2019-12-19 | Semicoudcutor structure and manufacturing method therefore |
| TW108146564 | 2019-12-19 |
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| Publication Number | Publication Date |
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| CN113013331A CN113013331A (en) | 2021-06-22 |
| CN113013331B true CN113013331B (en) | 2024-04-05 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW439273B (en) * | 1998-06-06 | 2001-06-07 | United Microelectronics Corp | Cylindrical capacitor structure and fabricating method |
| US6294425B1 (en) * | 1999-10-14 | 2001-09-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors by electroplating electrodes from seed layers |
| US6756262B1 (en) * | 1999-11-11 | 2004-06-29 | Hitachi, Ltd. | Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof |
| CN101118873A (en) * | 2006-08-04 | 2008-02-06 | 联华电子股份有限公司 | Semiconductor component and its making method |
| TW201036110A (en) * | 2009-03-30 | 2010-10-01 | Vanguard Int Semiconduct Corp | Method for fabricating a semiconductor device |
| CN106298980A (en) * | 2015-05-29 | 2017-01-04 | 力晶科技股份有限公司 | Capacitor structure and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8405135B2 (en) * | 2010-10-05 | 2013-03-26 | International Business Machines Corporation | 3D via capacitor with a floating conductive plate for improved reliability |
| FR3012664B1 (en) * | 2013-10-29 | 2016-01-01 | Ipdia | STRUCTURE WITH IMPROVED CAPACITY |
-
2019
- 2019-12-19 TW TW108146564A patent/TWI737087B/en active
-
2020
- 2020-01-03 CN CN202010004398.1A patent/CN113013331B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW439273B (en) * | 1998-06-06 | 2001-06-07 | United Microelectronics Corp | Cylindrical capacitor structure and fabricating method |
| US6294425B1 (en) * | 1999-10-14 | 2001-09-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors by electroplating electrodes from seed layers |
| US6756262B1 (en) * | 1999-11-11 | 2004-06-29 | Hitachi, Ltd. | Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof |
| CN101118873A (en) * | 2006-08-04 | 2008-02-06 | 联华电子股份有限公司 | Semiconductor component and its making method |
| TW201036110A (en) * | 2009-03-30 | 2010-10-01 | Vanguard Int Semiconduct Corp | Method for fabricating a semiconductor device |
| CN106298980A (en) * | 2015-05-29 | 2017-01-04 | 力晶科技股份有限公司 | Capacitor structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI737087B (en) | 2021-08-21 |
| TW202125842A (en) | 2021-07-01 |
| CN113013331A (en) | 2021-06-22 |
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