CN100543965C - Semiconductor element and manufacture method thereof - Google Patents
Semiconductor element and manufacture method thereof Download PDFInfo
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- CN100543965C CN100543965C CNB2006101009687A CN200610100968A CN100543965C CN 100543965 C CN100543965 C CN 100543965C CN B2006101009687 A CNB2006101009687 A CN B2006101009687A CN 200610100968 A CN200610100968 A CN 200610100968A CN 100543965 C CN100543965 C CN 100543965C
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Abstract
A kind of manufacture method of semiconductor element, the method is, one substrate is provided earlier, at least have the transistor area that comprises grid structure in the substrate, comprise the capacitor area of first electrode and the resistor area that comprises second electrode, wherein capacitor area and resistor area all comprise isolation structure.Then, form the LDD district and the doped region of first clearance wall and grid both sides in regular turn, wherein LDD district and doped region are as source/drain regions.Then, form the dielectric layer and first conductor material layer in regular turn in the substrate top.Afterwards, patterning first conductor material layer is with the third electrode of formation capacitor area and the conductor layer of resistor area.Subsequently, form second clearance wall.Then, remove the dielectric layer that not lining covers.Afterwards, carry out self-aligned metal silicate technology, form metal silicide layer, with the cladding element surface.
Description
Technical field
The present invention relates to a kind of technology of integrated circuit component, relate in particular to a kind of semiconductor element and manufacture method thereof.
Background technology
The circuit function that integrated circuit uses multiple element to be desired to reach to realize.These elements can comprise bipolar and mos field effect transistor, junction rectifier, resistor and capacitor etc.Along with electronic product constantly develops, people are for the character of integrated circuit (Integrated Circuit, be called for short IC), for example high power capacity, high efficiency, small size etc. require standard, also constantly in the middle of improving.
For instance, industry is not apply under the voltage condition for the requirement of capacitor now, and capacitor still can have high accuracy, and promptly capacitor need have good charge storage capacity, and reduces to the phenomenon of charge loss minimum.Wherein, widely one of capacitor type that industry adopted is polysilicon-insulating layer-polysilicon (Polysilicon-Insulator-Polysilicon is called for short PIP) capacitor.
Generally speaking, when in integrated circuit technology, needing to integrate PIP capacitor and transistor unit, can increase by one photo-marsk process and come the patterned polysilicon layer, to define the top electrode of PIP capacitor.In addition, if desire to carry out silicification technics, then in the part that need not form metal silicide, can be by covering one deck barrier layer, to avoid the generation of silicification reaction.And the making on above-mentioned barrier layer need increase by one photo-marsk process equally, defines the zone that desire covers.Particularly because the generation of silicification reaction because of not needing additionally to cover other rete, promptly can be avoided in zone that the barrier layer covered again, so this barrier layer be called again the self-aligned metal silicate barrier layer (Salicide Block Layer, SABLayer).
Owing to adopt PIP type capacitor will make the technology of whole integrated circuit component increase the twice photo-marsk process at least, for example the definition on the patterning of polysilicon layer and self-aligned metal silicate barrier layer etc. all need use photo-marsk process, therefore comparatively complicated on the technology, and can improve the technology cost.
In addition, exposure is also arranged about the above-mentioned correlation technique of mentioning in the patented technology of some U.S., for example US 6,218, and 234 and US 5,434,098 etc.More than can be used as list of references of the present invention.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of semiconductor element can be integrated PIP capacitor, resistor and transistor unit technology, forms metal silicide layer on each element, and is comparatively simple and easy not complicated on the technology, and can save the technology cost.
A further object of the present invention provides a kind of manufacture method of semiconductor element, can integrate PIP capacitor and transistor unit technology, to form metal silicide layer on each element.
Another purpose of the present invention provides a kind of semiconductor element, has transistor, capacitor and the resistor of self-aligned metal silicate laminar surface.
Another object of the present invention provides a kind of semiconductor element, has the transistor AND gate capacitor of self-aligned metal silicate laminar surface.
The present invention proposes a kind of manufacture method of semiconductor element, and this manufacture method comprises provides a substrate, has transistor area, capacitor area and resistor area in the substrate at least, and wherein capacitor area and resistor area all comprise isolation structure.Then, in the substrate of transistor area, form grid structure, and form first electrode, and form second electrode in resistor area in capacitor area.Subsequently, on the sidewall of grid structure, first electrode and second electrode, form first clearance wall.Afterwards, form LDD district and doped region in the grid structure substrate on two sides, wherein this LDD district and this doped region are as source/drain regions.Next, form the dielectric layer and first conductor material layer in regular turn in the substrate top.Then, carry out first Patternized technique, define first conductor material layer, with simultaneously in forming third electrode on the dielectric layer of capacitor area and on the dielectric layer of resistor area, forming conductor layer.Then, on third electrode and conductor layer sidewall, form second clearance wall.Afterwards, remove the dielectric layer that is not covered by third electrode, conductor layer and second clearance wall.Then, carry out self-aligned metal silicate technology, form metal silicide layer in the surface of grid structure, source/drain regions, first electrode, third electrode, conductor layer and second electrode.
According to the described semiconductor device manufacturing method of embodiments of the invention, the first above-mentioned Patternized technique for example is to comprise a photoetching process and an etch process.
According to the described semiconductor device manufacturing method of embodiments of the invention, the formation method of above-mentioned grid structure, first electrode and second electrode for example is to form a dielectric materials layer in the substrate of transistor area.Then, form second conductor material layer, cover dielectric materials layer and isolation structure in the substrate top.Then, carry out second Patternized technique, define second conductor material layer, in the substrate of transistor area, to form grid simultaneously, to form first electrode and form second electrode in resistor area in capacitor area.Subsequently, remove the dielectric materials layer that is not covered by grid, to form gate dielectric layer, gate dielectric layer and grid are as grid structure.The material of the second above-mentioned conductor material layer for example is polysilicon or doped polycrystalline silicon.Second Patternized technique for example is to comprise a photoetching process and an etch process.
According to the described semiconductor device manufacturing method of embodiments of the invention, the material of the first above-mentioned conductor material layer for example is polysilicon or doped polycrystalline silicon.
According to the described semiconductor device manufacturing method of embodiments of the invention, the material of above-mentioned dielectric layer for example is silica or silicon nitride.
According to the described semiconductor device manufacturing method of embodiments of the invention, above-mentioned metal silicide layer for example is a heating resisting metal silicide.Heating resisting metal is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.
The present invention proposes a kind of manufacture method of semiconductor element, and this manufacture method comprises provides a substrate, has transistor area and capacitor area in the substrate at least, and wherein capacitor area comprises isolation structure.Then in the substrate of transistor area, form first dielectric layer.Then, form first conductor layer, second dielectric layer and second conductor layer in regular turn, to cover the isolation structure and first dielectric layer in the substrate top.Subsequently, carry out first Patternized technique, define second conductor layer and second dielectric layer, to form first electrode and capacitance dielectric layer in capacitor area as capacitor.Next, carry out second Patternized technique, define first conductor layer, form grid to form in capacitor area as second electrode of capacitor and in transistor area.Afterwards, remove first dielectric layer that is not covered, to form gate dielectric layer by grid.Then, in the grid substrate on two sides, form LDD.Subsequently, on the sidewall of grid, gate dielectric layer, first electrode, capacitance dielectric layer and second electrode, form first clearance wall.Afterwards, in the first clearance wall substrate on two sides of transistor area, form doped region.Wherein, LDD and doped region are as source.And carry out self-aligned metal silicate technology, form metal silicide layer, with the surface of cover gate, source/drain regions, first electrode and second electrode.
According to the described semiconductor device manufacturing method of embodiments of the invention, the first above-mentioned Patternized technique for example is to comprise a photoetching process and an etch process.
According to the described semiconductor device manufacturing method of embodiments of the invention, the second above-mentioned Patternized technique for example is to comprise a photoetching process and an etch process.
According to the described semiconductor device manufacturing method of embodiments of the invention, the first above-mentioned conductor material layer and the material of second conductor material layer for example are polysilicon or doped polycrystalline silicon.
According to the described semiconductor device manufacturing method of embodiments of the invention, the material of the second above-mentioned dielectric layer for example is silica or silicon nitride.
According to the described semiconductor device manufacturing method of embodiments of the invention, above-mentioned metal silicide layer for example is a heating resisting metal silicide.Heating resisting metal is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.
The present invention proposes a kind of semiconductor element, and this semiconductor element comprises substrate, transistor, capacitor and resistor.Wherein, have transistor area, capacitor area and resistor area in the substrate, capacitor area and resistor area all comprise isolation structure.Transistor is positioned in the substrate of transistor area, and transistor comprises the source/drain regions that is arranged in suprabasil grid structure, is positioned at the grid structure substrate on two sides, is positioned at the clearance wall of grid structure sidewall and is positioned at grid structure and first metal silicide layer on the surface of source/drain regions.Wherein, grid structure comprises gate dielectric layer and grid, and source/drain regions comprises LDD district and doped region.Capacitor is positioned on the isolation structure of capacitor area, and capacitor comprises first electrode, capacitance dielectric layer, second electrode and second metal silicide layer.First electrode is positioned on the capacitor area isolation structure.Capacitance dielectric layer is positioned on first electrode, and covers part first electrode surface.Second electrode is positioned on the capacitance dielectric layer.Second metal silicide layer is positioned on first electrode that is exposed and is positioned on second electrode.In addition, resistor is positioned on the isolation structure of resistor area, and resistor comprises third electrode and the 3rd metal silicide layer.Third electrode is positioned on the isolation structure of resistor area.The 3rd metal silicide layer is positioned on the third electrode, and covers the third electrode edge.
According to the described semiconductor element of embodiments of the invention, above-mentioned grid, first electrode are identical with the material of third electrode, and its material for example is polysilicon or doped polycrystalline silicon.
According to the described semiconductor element of embodiments of the invention, the material of the second above-mentioned electrode for example is polysilicon or doped polycrystalline silicon.
According to the described semiconductor element of embodiments of the invention, the material of above-mentioned capacitance dielectric layer for example is silica or silicon nitride.
According to the described semiconductor element of embodiments of the invention, first, second, third above-mentioned metal silicide layer for example is a heating resisting metal silicide.Heating resisting metal is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.
The present invention proposes a kind of semiconductor element, and this semiconductor element comprises substrate, transistor and capacitor.Wherein, have transistor area and capacitor area in the substrate at least, capacitor area comprises isolation structure.Transistor is positioned in the substrate of transistor area, and transistor comprises the source/drain regions that is arranged in suprabasil grid structure, is positioned at the grid structure substrate on two sides, is positioned at the clearance wall of grid structure sidewall and is positioned at grid structure and first metal silicide layer on the surface of source/drain regions.Wherein, grid structure comprises gate dielectric layer and grid, and source/drain regions comprises LDD district and doped region.Capacitor is positioned on the isolation structure of capacitor area, and capacitor comprises first electrode, capacitance dielectric layer, second electrode and second metal silicide layer.First electrode is positioned on the isolation structure of capacitor area.Capacitance dielectric layer is positioned on first electrode, and cover part first electrode surface.Second electrode is positioned on the capacitance dielectric layer.Second metal silicide layer is positioned on first electrode that is exposed and is positioned on second electrode.
According to the described semiconductor element of embodiments of the invention, the material of the above-mentioned grid and first electrode is identical, and its material for example is polysilicon or doped polycrystalline silicon.
According to the described semiconductor element of embodiments of the invention, the material of the second above-mentioned electrode for example is polysilicon or doped polycrystalline silicon.
According to the described semiconductor element of embodiments of the invention, the material of above-mentioned capacitance dielectric layer for example is silica or silicon nitride.
According to the described semiconductor element of embodiments of the invention, first, second above-mentioned metal silicide layer for example is a heating resisting metal silicide.Heating resisting metal is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.
The present invention utilizes photo-marsk process one, can define the top electrode of PIP capacitor, and define the self-aligned metal silicate barrier layer simultaneously, so that in the part that need not form metal silicide, can avoid the generation of silicification reaction, therefore method of the present invention can make technology comparatively simplify, and escapable cost.In addition, the present invention can form metal silicide layer on capacitor and resistor, therefore can improve the accuracy and the element efficiency of capacitor.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, several embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A is the manufacturing process generalized section according to the semiconductor element that one embodiment of the invention illustrated to Fig. 1 G;
Fig. 2 A is the flow process generalized section according to the manufacture method of the semiconductor element that another embodiment of the present invention illustrated to Fig. 2 E.
The main element symbol description
100,200: substrate
102,202: transistor area
104,204: capacitor area
106: resistor area
108a, 108b, 208: isolation structure
110,225: grid structure
110a, 222: grid
110b, 224: gate dielectric layer
112,114,124,216,220: electrode
116,128,228,229: clearance wall
118,226: source/drain regions
120,127,129,206,212,218: dielectric layer
122: conductor material layer
126,210,214: conductor layer
130a, 130b, 130c, 230a, 203b: metal silicide layer
132,232: transistor
134,234: the polysilicon-insulating layer-polysilicon capacitance device
136: resistor
226a：LDD
226b: doped region
Embodiment
Figure 1A is the flow process generalized section according to the manufacture method of the semiconductor element that one embodiment of the invention illustrated to Fig. 1 G.
At first, please refer to Figure 1A, a substrate 100 is provided, substrate 100 can for example be silicon main body (bulk) substrate, and substrate 100 also can for example be silicon-on-insulator (Silicon On Insulator is called for short SOI) substrate certainly.This substrate 100 has at least one transistor area 102, a capacitor area 104 and a resistor area 106.In the substrate 100 of capacitor area 104, has an isolation structure 108a, and in the substrate 100 of resistor area 106, has an isolation structure 108b, isolation structure 108a, 108b can for example be fleet plough groove isolation structures (STI), or with formed isolation structure of regional area oxidation technology (LOCOS).
Then, please continue with reference to Figure 1A, form a grid structure 110 in the substrate 100 in transistor area 102, go up in the isolation structure 108a of capacitor area 104 and form an electrode 112, and go up formation one electrode 114 in the isolation structure 108b of resistor area 106.Electrode 114 can be used as a resistor element.
Above-mentioned, grid structure 110, electrode 112 with the formation method of electrode 114 for example are, form one deck dielectric materials layer (not illustrating) in the substrate 100 in transistor area 102 earlier, the material of dielectric materials layer for example is a silica, and its formation method for example is a chemical vapour deposition technique.Then, form one deck conductor material layer (not illustrating), to cover whole substrate, the material of conductor material layer for example is polysilicon or doped polycrystalline silicon.Then, carry out a Patternized technique, define this conductor material layer, forming grid 110a in the substrate 100 in transistor area 102 in simultaneously, to go up in the isolation structure 108a of capacitor area 104 and form electrode 112, and go up formation electrode 114 in the isolation structure 108b of resistor area 106.Above-mentioned Patternized technique for example is to comprise a photoetching process and an etch process.Then, remove the dielectric materials layer that is not covered by grid 110a, to form gate dielectric layer 110b, grid 110a and gate dielectric layer 110b then constitute grid structure 110.
Then, please refer to Figure 1B, on the sidewall of grid structure 110, electrode 112 and electrode 114, form a clearance wall 116.The formation method of clearance wall 116 for example is, utilizes chemical vapour deposition (CVD) (Chemical Vapor Deposition is called for short CVD) to form one deck silicon nitride layer earlier, carries out a dry-etching (Dry Etching) technology afterwards more unnecessary silicon nitride is removed.Next, after clearance wall 116 forms, in grid structure 110 substrate on two sides 100, form source 118, and the formation method of source/drain regions 118 for example utilizes ion implantation (Ion Implantation) to form.The grid structure 110 of above-mentioned transistor area 102, clearance wall 116 and source/drain regions 118 can constitute a transistor unit.
Then, please refer to Fig. 1 C, compliance ground forms one dielectric layer 120 above substrate 100, to cover whole substrate 100.The material of dielectric layer 120 for example is silica, silicon nitride or other suitable dielectric materials, and the formation method of dielectric layer 120 for example is a chemical vapour deposition technique.Then, on dielectric layer 120, form one deck conductor material layer 122.The material of conductor material layer 122 for example is polysilicon or doped polycrystalline silicon.
Then, please refer to Fig. 1 D, carry out a Patternized technique, definition conductor material layer 122 with formation electrode 124 on the dielectric layer 120 of capacitor area 104, and forms conductor layer 126 simultaneously on the dielectric layer 120 of resistor area 106.Above-mentioned, the Patternized technique of definition conductor material layer 122 for example is to comprise a photoetching process and an etch process.
What deserves to be mentioned is that present embodiment is to utilize to carry out a Patternized technique, to define electrode 124 in the capacitor area 104 and the conductor layer 126 in the resistor area 106.Wherein, dielectric layer 120 between the electrode 112,124 of capacitor area 104 can be used as capacitance dielectric layer, and the dielectric layer 120 that conductor layer 126 is covered can be regarded self-aligned metal silicate barrier layer (Salicide BlockLayer, SAB Layer), so that, can avoid the generation of silicification reaction in the part that need not form metal silicide.In other words, present embodiment carries out photo-marsk process one, can define the electrode and the self-aligned metal silicate barrier layer of PIP capacitor simultaneously, so can make technology comparatively simple and easy, and can save the technology cost.
Then, please refer to Fig. 1 E, on the sidewall of the sidewall of electrode 124 and conductor layer 126, form clearance wall 128.The formation method of clearance wall 128 for example is, utilizes chemical vapour deposition (CVD) to form one deck silicon nitride layer earlier, carries out a dry etch process afterwards more unnecessary silicon nitride is removed.The effect of clearance wall 128 can be avoided the undesired electric connection of electrode 112 with the electrode 124 of capacitor area 104, and can avoid the undesired electric connection of electrode 114 with the conductor layer 126 of resistor area 106.
Then, please refer to Fig. 1 F, remove the dielectric layer 120 that is not covered, to form dielectric layer 127,129 respectively by electrode 124, conductor layer 126 and clearance wall 128.The method that removes part dielectric layer 120 for example is to utilize wet etching.Wherein, the dielectric layer 129 of capacitor area 104 can be used as capacitance dielectric layer, and the electrode 112 of capacitor area 104, dielectric layer 129 and electrode 124 can be formed polysilicon-insulating layer-polysilicon (PIP) capacitor element.
Subsequently, please refer to Fig. 1 G, carry out a self-aligned metal silicate technology, to form metal silicide layer.Wherein, metal silicide layer comprises the metal silicide layer 130b that is formed at electrode 112 and electrode 124 surfaces, the metal silicide layer 130a that is formed at grid structure 110 and source/drain regions 118 surfaces, and the metal silicide layer 130c that is formed at conductor layer 126 and electrode 114 surfaces.
Wherein, the grid structure 110 of above-mentioned transistor area 102, clearance wall 116, source/drain regions 118 and metal silicide layer 130a constitute the transistor 132 of present embodiment.And the electrode 112 of above-mentioned capacitor area 104, dielectric layer 129, electrode 124 and metal silicide layer 130b constitute the capacitor 134 of present embodiment.The metal silicide layer 130c on conductor layer 114 and conductor layer 114 surfaces then constitutes the resistor 136 of present embodiment in addition.
Above-mentioned metal silicide layer 130a, 130b, 130c for example are the heating resisting metal silicides, and heating resisting metal then is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.And the method for autoregistration silication technique for metal for example is, utilizes direct current sputtering method (DC sputtering) in whole substrate 100 surface deposition layer of metal layers (not illustrating) earlier.Thereafter, carry out a heat treatment, make metal level and pasc reaction form metal silicide layer.Then, with wet etching the unreacted metal layer is removed.Afterwards, carry out the heat treatment of a higher temperature, to reduce the impedance of metal silicide layer.Photo-marsk process is carried out in the present embodiment utilization one, can define the top electrode and the self-aligned metal silicate barrier layer of PIP capacitor simultaneously, therefore can make technology comparatively simple and easy not complicated, and can save the technology cost.In addition, present embodiment can form on transistor unit in the metal silicide layer, form metal silicide layer in the surface of PIP capacitor element and resistor element, can reduce the impedance with plain conductor thus, and can improve the accuracy of capacitor and resistor and the usefulness of element.
Below, with the semiconductor element of Fig. 1 G explanation one embodiment of the invention.
Please referring again to Fig. 1 G, semiconductor element comprises substrate 100, transistor 132, capacitor 134 and resistor 136.
Wherein, have transistor area 102, capacitor area 104 and resistor area 106 in the substrate 100, and capacitor area 104 and resistor area 106 comprise isolation structure 108a, 108b all respectively.
136 of resistors are positioned on the isolation structure 108b of resistor area 106.Resistor 136 comprises electrode 114 and metal silicide layer 130c.Electrode 114 is positioned on the isolation structure 108b of resistor area 106, and the material of electrode 114 for example is polysilicon or doped polycrystalline silicon.Metal silicide layer 130c then is positioned on the electrode 114 that is exposed.Metal silicide layer 130c for example is the heating resisting metal silicide, and heating resisting metal is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.
The semiconductor element of present embodiment includes transistor, capacitor and resistor, and all has metal silicide layer at these element surfaces, so can reduce the impedance between element and the plain conductor, and all can promote to some extent for the accuracy and the integral member performance of capacitor and resistor.
Fig. 2 A is the flow process generalized section according to the manufacture method of the semiconductor element that another embodiment of the present invention illustrated to Fig. 2 E.
At first, please refer to Fig. 2 A, substrate 200 is provided, and have transistor area 202 and capacitor area 204 in the substrate 200.Wherein, capacitor area 204 comprises the isolation structure 208 that is formed in the substrate 200, has been formed with one dielectric layer 206 in the substrate 200 of transistor area 202.The material of dielectric layer 206 for example is a silica, and its formation method for example is a thermal oxidation method.
Then, in substrate 200, form conductor layer 210, dielectric layer 212 and conductor layer 214 in regular turn, and cover isolation structure 208 and dielectric layer 206.Wherein conductor layer 210 is identical with the material of conductor layer 214, for example is polysilicon or doped polycrystalline silicon.The material of dielectric layer 212 for example is silica or silicon nitride.
Afterwards, please refer to Fig. 2 B, carry out a Patternized technique, definition conductor layer 214 and dielectric layer 212 forming the electrode 216 of a conductor layer as capacitor in capacitor area 204, and form the capacitance dielectric layer of a dielectric layer 218 as capacitor.Above-mentioned Patternized technique for example is to comprise a photoetching process and an etch process.
Next, please refer to Fig. 2 C, carry out Patternized technique again one time, definition conductor layer 210, with the electrode 220 that forms as capacitor in capacitor area 204, and at transistor area 202 formation grids 222.
Then, remove the dielectric layer 206 that is not covered, to form gate dielectric layer 224 by grid 222.The method that removes not the dielectric layer 206 that is covered by grid 222 comprises wet etching, and it for example is as etchant with hydrofluoric acid.Above-mentioned, grid 222 constitutes a grid structure 225 with gate dielectric layer 224.
Subsequently, please refer to Fig. 2 D, in grid 222 substrate on two sides 200, form LDD226a.Then, on the sidewall of grid 222 and gate dielectric layer 224, form clearance wall 228, and on the sidewall of electrode 216, dielectric layer 218 and electrode 220, form clearance wall 229.Clearance wall 228,229 can for example be to form simultaneously, and its formation method for example is to form one deck spacer material layer (not illustrating), to cover whole substrate 200.Then, carry out an anisotropic etching process, remove part spacer material layer, with what form.
Next, please continue D, in clearance wall 228 substrate on two sides 200, form a doped region 226b, and LDD 226a and doped region 226b be as source/drain regions 226 with reference to Fig. 2.
Then, please refer to Fig. 2 E, carry out a self-aligned metal silicate technology, form a metal silicide layer, with cover grid 222, source/drain regions 226, electrode 216 and electrode 220 surfaces.Wherein, metal silicide layer comprises the metal silicide layer 230a that is formed at grid 222 and source/drain regions 226 surfaces, and the metal silicide layer 230b that is formed at electrode 216 and electrode 220 surfaces. Metal silicide layer 230a, 230b for example are the heating resisting metal silicides, and heating resisting metal for example is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.Above-mentioned, grid 222, gate dielectric layer 224, source/drain regions 226, clearance wall 228 and metal silicide layer 230a can form a transistor 232.Electrode 216, dielectric layer 218, electrode 220 and metal silicide layer 230b can form polysilicon-insulating layer-polysilicon (PIP) capacitor 234.
The semiconductor element technology of present embodiment can be integrated PIP capacitor and transistorized technology, to form metal silicide layer simultaneously on PIP capacitor and transistor, so helps to increase the accuracy of capacitor, and can improve element efficiency.On the other hand, the method for present embodiment does not also need additionally to increase photo-marsk process again, can obtain having the transistor AND gate capacitor of metal silicide layer, therefore can not improve the complexity and the technology cost of technology.
Below, with the semiconductor element of Fig. 2 E explanation another embodiment of the present invention.
Please referring again to Fig. 2 E, semiconductor element comprises substrate 200, transistor 232 and capacitor 234.
Wherein, have transistor area 202 and capacitor area 204 in the substrate 200, and capacitor area 204 comprises isolation structure 208.
In sum, the present invention has following advantage at least:
1. in the method for the invention, photo-marsk process can be only utilized one, the top electrode and the self-aligned metal silicate barrier layer of PIP capacitor can be defined simultaneously.Therefore can make technology comparatively simple and easy not complicated, and can save the technology cost.
Therefore 2. semiconductor element of the present invention has metal silicide layer, can improve the accuracy of capacitor and resistor, and can reduce the impedance with plain conductor.
Though the present invention discloses as above with several embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (7)
1. the manufacture method of a semiconductor element comprises:
Substrate is provided, has at least one transistor area and at least one capacitor area in this substrate, wherein this capacitor area comprises isolation structure;
In this substrate of this transistor area, form first dielectric layer;
Form first conductor material layer, second dielectric layer and second conductor material layer in regular turn in this substrate top, to cover this isolation structure and this first dielectric layer;
Carry out first Patternized technique, define this second conductor material layer and this second dielectric layer, to form first electrode and capacitance dielectric layer in this capacitor area as capacitor;
Carry out second Patternized technique, define this first conductor material layer, form grid to form in this capacitor area as second electrode of capacitor and in this transistor area;
Remove this first dielectric layer that is not covered, to form gate dielectric layer by this grid;
In this substrate of these grid both sides, form LDD;
On the sidewall of this grid, this gate dielectric layer, this first electrode, this capacitance dielectric layer and this second electrode, form first clearance wall;
Form doped region in this substrate of this first clearance wall both sides of this transistor area, wherein this LDD and this doped region are as source/drain regions; And
Carry out self-aligned metal silicate technology, form metal silicide layer, to cover the surface of this grid, this source/drain regions, this first electrode and this second electrode.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein this first Patternized technique comprises photoetching process and etch process.
3. the manufacture method of semiconductor element as claimed in claim 1, wherein this second Patternized technique comprises photoetching process and etch process.
4. the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this first conductor material layer and this second conductor material layer comprises polysilicon or doped polycrystalline silicon.
5. the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this second dielectric layer comprises silica or silicon nitride.
6. the manufacture method of semiconductor element as claimed in claim 1, wherein this metal silicide layer comprises the heating resisting metal silicide.
7. the manufacture method of semiconductor element as claimed in claim 6, wherein this heating resisting metal is to be selected from the group that nickel, tungsten, cobalt, titanium, molybdenum and platinum are formed.
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| CN101853811B (en) * | 2009-04-03 | 2012-02-15 | 世界先进积体电路股份有限公司 | Method for manufacturing semiconductor device |
| CN102194695B (en) * | 2010-03-15 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Method for removing clearance wall structure |
| JPWO2012086169A1 (en) * | 2010-12-20 | 2014-05-22 | 株式会社アルバック | Dielectric device manufacturing method and ashing method |
| US9240454B1 (en) * | 2014-10-22 | 2016-01-19 | Stmicroelectronics, Inc. | Integrated circuit including a liner silicide with low contact resistance |
| CN105632891A (en) * | 2014-11-28 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of PIP capacitor |
| CN108538833B (en) * | 2017-03-01 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Resistor structure, semiconductor device and forming method thereof |
| TWI725767B (en) * | 2020-03-12 | 2021-04-21 | 力晶積成電子製造股份有限公司 | Memory structure and manufacturing method therefore |
| CN111613725A (en) * | 2020-06-15 | 2020-09-01 | 华虹半导体(无锡)有限公司 | Method for manufacturing capacitor |
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