TWI731328B - Semiconductor power device - Google Patents

Semiconductor power device Download PDF

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TWI731328B
TWI731328B TW108114782A TW108114782A TWI731328B TW I731328 B TWI731328 B TW I731328B TW 108114782 A TW108114782 A TW 108114782A TW 108114782 A TW108114782 A TW 108114782A TW I731328 B TWI731328 B TW I731328B
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power device
aforementioned
device wafer
mosfet
igbt
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TW202005017A (en
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劉偉
劉磊
袁願林
毛振東
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大陸商蘇州東微半導體股份有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本發明實施例提供一種半導體功率器件，包含MOSFET功率器件晶片及IGBT功率器件晶片。其中，前述MOSFET功率器件晶片及前述IGBT功率器件晶片封裝在同一個封裝體內；前述MOSFET功率器件晶片的源極與前述IGBT功率器件晶片的發射極均與前述封裝體的源極引腳連接；前述MOSFET功率器件晶片的漏極與前述IGBT功率器件晶片的集電極均與前述封裝體的漏極引腳連接；前述MOSFET功率器件晶片的柵極與前述IGBT功率器件晶片的柵極均與前述封裝體的柵極引腳連接。本發明實施型態提供的半導體功率器件能夠降低半導體功率器件的通態損耗，提高系統效率。 The embodiment of the present invention provides a semiconductor power device, including a MOSFET power device wafer and an IGBT power device wafer. Wherein, the aforementioned MOSFET power device chip and the aforementioned IGBT power device chip are packaged in the same package; the source of the aforementioned MOSFET power device chip and the emitter of the aforementioned IGBT power device chip are both connected to the source pin of the aforementioned package; The drain of the MOSFET power device wafer and the collector of the aforementioned IGBT power device wafer are both connected to the drain pin of the aforementioned package; the gate of the aforementioned MOSFET power device wafer and the gate of the aforementioned IGBT power device wafer are both connected to the aforementioned package The gate pin is connected. The semiconductor power device provided by the embodiment of the present invention can reduce the on-state loss of the semiconductor power device and improve the system efficiency.

Description

半導體功率器件 Semiconductor power device

本發明實施型態關於半導體功率器件技術領域，例如關於一種半導體功率器件。 The embodiment of the present invention relates to the technical field of semiconductor power devices, for example, to a semiconductor power device.

隨著新能源及高效節能產業的不斷發展，針對低功耗的MOSFET(metal-oxide-semiconductor field-effect transistor，金屬-氧化層半導體場效電晶體)功率器件的要求越來越高，對單顆MOSFET功率器件晶片的電流處理能力的要求亦越來越高。因MOSFET功率器件晶片可以處理的電流密度相對較小，並且MOSFET功率器件具有比較大的電阻-溫度係數，MOSFET功率器件的導通電阻隨著溫度的增加而迅速增大。上述問題不僅增加MOSFET功率器件的通態損耗，亦降低系統效率。 With the continuous development of new energy and high-efficiency energy-saving industries, the requirements for low-power MOSFET (metal-oxide-semiconductor field-effect transistor, metal-oxide semiconductor field-effect transistor) power devices are getting higher and higher. The requirements for current handling capabilities of MOSFET power device wafers are also getting higher and higher. Because the current density that MOSFET power device wafers can handle is relatively small, and the MOSFET power device has a relatively large resistance-temperature coefficient, the on-resistance of the MOSFET power device increases rapidly with the increase of temperature. The above-mentioned problems not only increase the on-state loss of MOSFET power devices, but also reduce system efficiency.

本發明實施型態的目的是提供一種半導體功率器件，以解決先前技術中的MOSFET功率器件的通態損耗高以及進一步提升MOSFET功率器件可處理的電流密度的問題。 The purpose of the embodiment of the present invention is to provide a semiconductor power device to solve the problem of high on-state loss of the MOSFET power device in the prior art and to further improve the current density that the MOSFET power device can handle.

為達到本發明實施型態的上述目的，本發明實施型態提供一種半導體功率器件，包含：MOSFET功率器件晶片及IGBT(Insulated Gate Bipolar Transistor，絕緣柵雙極型電晶體)功率器件晶片；其中，前述MOSFET功率器件晶片及前述IGBT功率器件晶片封裝在同一個封裝體內；前述MOSFET功率器件晶片的源極與前述IGBT功率器件晶片的發射極均與前述封裝體的源極引腳連接；前述MOSFET功率器件晶片的漏極與前述IGBT功率器件晶片的集電極均與前述封裝體的漏極引腳連接；前述MOSFET功率器件晶片的柵極與前述IGBT功率器件晶片的柵極均與前述封裝體的柵極引腳連接。 In order to achieve the above objectives of the embodiment of the present invention, the embodiment of the present invention provides a semiconductor power device, including: a MOSFET power device wafer and an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) power device wafer; wherein, The aforementioned MOSFET power device chip and the aforementioned IGBT power device chip are packaged in the same package; the source of the aforementioned MOSFET power device chip and the emitter of the aforementioned IGBT power device chip are both connected to the source pin of the aforementioned package; the aforementioned MOSFET power The drain of the device wafer and the collector of the aforementioned IGBT power device wafer are both connected to the drain pin of the aforementioned package; the gate of the aforementioned MOSFET power device wafer and the gate of the aforementioned IGBT power device wafer are both connected to the gate of the aforementioned package. Pole pin connection.

在一實施型態中，前述IGBT功率器件晶片為溝槽柵結構的IGBT功率電晶體。 In one embodiment, the aforementioned IGBT power device wafer is an IGBT power transistor with a trench gate structure.

在一實施型態中，前述IGBT功率器件晶片為平面柵結構的IGBT功率電晶體。 In one embodiment, the aforementioned IGBT power device wafer is an IGBT power transistor with a planar gate structure.

在一實施型態中，前述IGBT功率器件晶片具有負的電阻-溫度係數。 In one embodiment, the aforementioned IGBT power device wafer has a negative resistance-temperature coefficient.

在一實施型態中，前述MOSFET功率器件晶片為垂直雙擴散金屬-氧化物半導體場效應電晶體。 In one embodiment, the aforementioned MOSFET power device wafer is a vertical double diffused metal-oxide semiconductor field effect transistor.

在一實施型態中，前述MOSFET功率器件晶片為超級結結 構的功率電晶體。 In one embodiment, the aforementioned MOSFET power device wafer is a super-structured power transistor.

本發明實施型態提供的一種半導體功率器件由MOSFET功率器件晶片及IGBT功率器件晶片並聯後封裝在同一個封裝體內，使得半導體功率器件的電阻隨溫度上升的電阻-溫度係數低，能夠降低半導體功率器件的通態損耗，提高系統效率，特別適用於大電流、大功率及高溫下的系統。 The semiconductor power device provided by the embodiment of the present invention consists of a MOSFET power device chip and an IGBT power device chip connected in parallel and then packaged in the same package, so that the resistance-temperature coefficient of the semiconductor power device's resistance with temperature rise is low, and the semiconductor power can be reduced The on-state loss of the device improves the system efficiency, and is especially suitable for the system under high current, high power and high temperature.

11、61‧‧‧發射極 11、61‧‧‧Emitter

12‧‧‧集電極 12‧‧‧ Collector

13、23‧‧‧柵極 13, 23‧‧‧Grid

21、51‧‧‧源極 21, 51‧‧‧Source

22‧‧‧漏極 22‧‧‧Drain

31‧‧‧源極電壓 31‧‧‧Source voltage

32‧‧‧漏極電壓 32‧‧‧Drain voltage

33‧‧‧柵極電壓 33‧‧‧Grid voltage

50‧‧‧MOSFET功率器件晶片 50‧‧‧MOSFET power device chip

53、63‧‧‧柵極 53, 63‧‧‧Grid

60‧‧‧IGBT功率器件晶片 60‧‧‧IGBT power device chip

71‧‧‧源極金屬導線 71‧‧‧Source metal wire

73‧‧‧柵極金屬導線 73‧‧‧Grid metal wire

81‧‧‧源極引腳 81‧‧‧Source pin

82‧‧‧漏極引腳 82‧‧‧Drain pin

83‧‧‧柵極引腳 83‧‧‧Gate pin

101‧‧‧IGBT功率器件 101‧‧‧IGBT power device

202‧‧‧MOSFET功率器件 202‧‧‧MOSFET power device

【圖1】係本發明實施型態提供的一種半導體功率器件中的MOSFET功率器件晶片及IGBT功率器件晶片封裝在同一個封裝體內的內部結構示意圖；【圖2】係本發明實施型態提供的一種半導體功率器件的等效電路示意圖；【圖3】係先前技術的一種MOSFET功率器件的輸出特性曲線圖；【圖4】係先前技術的一種IGBT功率器件的輸出特性曲線圖；【圖5】係本發明實施型態提供的一種半導體功率器件的輸出特性曲線圖。 [Figure 1] is a schematic diagram of the internal structure of the MOSFET power device chip and the IGBT power device chip packaged in the same package in a semiconductor power device provided by the embodiment of the present invention; [Figure 2] is provided by the embodiment of the present invention A schematic diagram of the equivalent circuit of a semiconductor power device; [Figure 3] is the output characteristic curve of a MOSFET power device of the prior art; [Figure 4] is the output characteristic curve of an IGBT power device of the prior art; [Figure 5] It is a graph of the output characteristic of a semiconductor power device provided by the embodiment of the present invention.

為使本發明實施例的目的、技術手段及優點更加清楚，下 述將結合本發明實施例中的圖式，藉由具體方式，完整地描述本發明實施例的技術手段。顯然，所描述的實施例是本發明實施例的一部分實施例，而不是全部的實施例。 In order to make the purpose, technical means, and advantages of the embodiments of the present invention clearer, the following description will combine the drawings in the embodiments of the present invention to fully describe the technical means of the embodiments of the present invention in a specific manner. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments.

應當理解，本發明實施例所使用的諸如「具有」、「包含」以及「包括」等術語並不配出一個或複數個其它元件或其組合的存在或添加。說明書圖式為示意性的，不應限定本發明實施例的範圍。 It should be understood that the terms such as "having", "including" and "including" used in the embodiments of the present invention do not equate the existence or addition of one or more other elements or combinations thereof. The drawings in the description are schematic and should not limit the scope of the embodiments of the present invention.

圖1是本發明實施例提供的一種半導體功率器件中的MOSFET功率器件晶片及IGBT功率器件晶片封裝在同一個封裝體內的內部結構示意圖，圖1中僅示例性的示出MOSFET功率器件晶片50及IGBT功率器件晶片60封裝在同一個封裝體內的打線結構示意圖。如圖1所示，MOSFET功率器件晶片50的源極(源極pad層)51與IGBT功率器件晶片60的發射極(發射極pad層)61均藉由源極金屬導線71與封裝體的源極引腳81連接，MOSFET功率器件晶片50的漏極與IGBT功率器件晶片60的集電極均與封裝體的漏極引腳82(MOSFET功率器件晶片50的漏極金屬層與IGBT功率器件晶片60的集電極金屬層均是位於其晶片的背面，從而均與封裝體中的金屬框架直接接觸接漏極引腳82，而不需要打線)連接；MOSFET功率器件晶片50的柵極(柵極pad層)53與IGBT功率器件晶片60的柵極(柵極pad層)63均藉由柵極金屬導線73與封裝體的柵極引腳83連接。 Figure 1 is a schematic diagram of the internal structure of a MOSFET power device chip and an IGBT power device chip packaged in the same package in a semiconductor power device provided by an embodiment of the present invention. Figure 1 only exemplarily shows the MOSFET power device chip 50 and A schematic diagram of the wire bonding structure in which the IGBT power device chip 60 is packaged in the same package. As shown in FIG. 1, the source (source pad layer) 51 of the MOSFET power device chip 50 and the emitter (emitter pad layer) 61 of the IGBT power device chip 60 are both provided by the source metal wire 71 and the source of the package. The pole pin 81 is connected, the drain of the MOSFET power device die 50 and the collector of the IGBT power device die 60 are both connected to the drain pin 82 of the package (the drain metal layer of the MOSFET power device die 50 and the IGBT power device die 60 The collector metal layers are all located on the backside of the wafer, so that they are directly connected to the metal frame in the package to connect to the drain pin 82 without wiring); the gate of the MOSFET power device wafer 50 (gate pad The layer 53 and the gate (gate pad layer) 63 of the IGBT power device wafer 60 are both connected to the gate pin 83 of the package through the gate metal wire 73.

需要說明的是，圖1中的MOSFET功率器件晶片50及IGBT功率器件晶片60僅是示例性的結構，根據不同的設計要求，MOSFET功率器件晶片50及IGBT功率器件晶片60均可以有不同的晶片 尺寸及耐壓，亦可以均有不同的pad層形狀或結構。此外，MOSFET功率器件晶片50及IGBT功率器件晶片60亦皆可內置柵極電阻。 It should be noted that the MOSFET power device wafer 50 and the IGBT power device wafer 60 in FIG. 1 are only exemplary structures. According to different design requirements, both the MOSFET power device wafer 50 and the IGBT power device wafer 60 can have different wafers. The size and pressure resistance can also have different pad shapes or structures. In addition, both the MOSFET power device wafer 50 and the IGBT power device wafer 60 can also have built-in gate resistors.

本發明實施例所提供的一種半導體功率器件中的MOSFET功率器件晶片可以為超級結構的功率電晶體，亦可以是垂直雙擴散金屬-氧化物半導體場效應電晶體。IGBT功率器件晶片可以是溝槽柵結構的IGBT功率電晶體，亦可以是平面柵結構的IGBT功率電晶體。本發明實施例對MOSFET功率器件晶片及IGBT功率器件晶片的類型及結構不作限制。 The MOSFET power device wafer in a semiconductor power device provided by the embodiment of the present invention can be a super structure power transistor, or a vertical double diffused metal-oxide semiconductor field effect transistor. The IGBT power device wafer can be an IGBT power transistor with a trench gate structure or an IGBT power transistor with a planar gate structure. The embodiment of the present invention does not limit the types and structures of MOSFET power device wafers and IGBT power device wafers.

圖2是本發明實施例提供的一種半導體功率器件的等效電路示意圖，如圖2所示，本發明實施例的一種半導體功率器件的等效電路包含MOSFET功率器件202及IGBT功率器件101，其中：MOSFET功率器件202的源極21與IGBT功率器件101的發射極11連接並接入源極電壓31，MOSFET功率器件202的漏極22與IGBT功率器件101的集電極12連接並接入漏極電壓32，MOSFET功率器件202的柵極23與IGBT功率器件101的柵極13連接並接入柵極電壓33。 FIG. 2 is a schematic diagram of an equivalent circuit of a semiconductor power device according to an embodiment of the present invention. As shown in FIG. 2, the equivalent circuit of a semiconductor power device according to an embodiment of the present invention includes a MOSFET power device 202 and an IGBT power device 101, wherein : The source 21 of the MOSFET power device 202 is connected to the emitter 11 of the IGBT power device 101 and connected to the source voltage 31, and the drain 22 of the MOSFET power device 202 is connected to the collector 12 of the IGBT power device 101 and connected to the drain At voltage 32, the gate 23 of the MOSFET power device 202 is connected to the gate 13 of the IGBT power device 101 and is connected to the gate voltage 33.

選擇性地，本發明實施例的一種半導體功率器件中的IGBT功率器件晶片具有負電阻-溫度係數，以盡可能地抵消MOSFET功率器件晶片的正的電阻-溫度係數，進一步降低半導體功率器件在高溫下的通態損耗。 Optionally, the IGBT power device wafer in a semiconductor power device of the embodiment of the present invention has a negative resistance-temperature coefficient, so as to offset the positive resistance-temperature coefficient of the MOSFET power device wafer as much as possible, and further reduce the high temperature of the semiconductor power device. Under the on-state loss.

本發明實施例的一種半導體功率器件中的MOSFET功率器件晶片及IGBT功率器件晶片屬於並聯的結構，因IGBT功率器件晶片具有較小的電阻-溫度係數甚至是負電阻-溫度係數，此可以降低或者抵消MOSFET功率器件晶片的正電阻-溫度係數，從而使得本發明實施例的半 導體功率器件具有低的電阻-溫度係數，進而能夠降低半導體功率器件在高溫下的通態損耗，提高系統效率，特別適用於大電流、大功率及高溫下的系統。 The MOSFET power device chip and the IGBT power device chip in a semiconductor power device of the embodiment of the present invention are in a parallel structure. Because the IGBT power device chip has a small resistance-temperature coefficient or even a negative resistance-temperature coefficient, this can be reduced or Offset the positive resistance-temperature coefficient of the MOSFET power device wafer, so that the semiconductor power device of the embodiment of the present invention has a low resistance-temperature coefficient, thereby reducing the on-state loss of the semiconductor power device at high temperatures and improving the system efficiency, which is particularly suitable For systems under high current, high power and high temperature.

本發明實施例的一種半導體功率器件，當漏源電壓Vds較小時，半導體功率器件的電流主要從MOSFET功率器件晶片中流過，當漏源電壓Vds增大時，流過IGBT功率器件晶片的電流亦會增大，隨著漏源電壓Vds的繼續增大，流過IGBT功率器件晶片的電流可以等於或者大於流過MOSFET功率器件晶片的電流。因本發明實施例的半導體功率器件的電流是由流過MOSFET功率器件晶片的電流及流過IGBT功率器件晶片的電流組成的，而IGBT功率器件晶片可以處理的電流密度往往大於MOSFET功率器件晶片可以處理的電流密度，因此，本發明實施例提出的半導體功率器件可以處理的電流密度大於傳統MOSFET功率器件可以處理的電流密度。同時，MOSFET功率器件晶片在較低的漏源電壓Vds時就可以實現遠小於IGBT功率器件晶片的導通電阻，因此，本發明實施例提出的半導體功率器件可以實現遠小於傳統的IGBT功率器件的飽和導通壓降。 In a semiconductor power device according to an embodiment of the present invention, when the drain-source voltage Vds is small, the current of the semiconductor power device mainly flows from the MOSFET power device wafer, and when the drain-source voltage Vds increases, the current flows through the IGBT power device wafer It will also increase. As the drain-source voltage Vds continues to increase, the current flowing through the IGBT power device wafer can be equal to or greater than the current flowing through the MOSFET power device wafer. Because the current of the semiconductor power device in the embodiment of the present invention is composed of the current flowing through the MOSFET power device wafer and the current flowing through the IGBT power device wafer, the current density that the IGBT power device wafer can handle is often greater than that of the MOSFET power device wafer. The processed current density, therefore, the current density that the semiconductor power device proposed in the embodiment of the present invention can handle is greater than the current density that can be handled by a traditional MOSFET power device. At the same time, the MOSFET power device wafer can achieve much smaller on-resistance than the IGBT power device wafer when the drain-source voltage Vds is lower. Therefore, the semiconductor power device proposed in the embodiment of the present invention can achieve much smaller saturation than the traditional IGBT power device. Turn-on pressure drop.

圖3是先前技術的一種MOSFET功率器件的輸出特性曲線圖，圖4是先前技術的一種IGBT功率器件的輸出特性曲線圖，圖5是本發明實施例提供的一種半導體功率器件的輸出特性曲線圖。示例性的，圖3中的MOSFET功率器件選用蘇州東微半導體有限公司的OSG60R074HSZ產品進行測試得到輸出特性曲線圖，圖4中的IGBT功率器件選用英飛淩有限公司的IGW60N60H產品進行測試得到的輸出特性曲 線圖，圖5是將OSG60R074HSZ產品及IGW60N60H產品並聯後進行測試得到的輸出特性曲線圖。由圖3、圖4及圖5可知，將MOSFET功率器件晶片及IGBT功率器件晶片並聯後的半導體功率器件，其可以處理的電流密度大於MOSFET功率器件可以處理的電流密度，且其飽和導通壓降小於IGBT功率器件的飽和導通壓降。又，將MOSFET功率器件晶片及IGBT功率器件晶片封裝在同一個封裝體內，可以簡化應用電路板的設計。 Fig. 3 is an output characteristic curve diagram of a MOSFET power device of the prior art, Fig. 4 is an output characteristic curve diagram of an IGBT power device in the prior art, and Fig. 5 is an output characteristic curve diagram of a semiconductor power device provided by an embodiment of the present invention . Exemplarily, the MOSFET power device in Figure 3 is tested with the OSG60R074HSZ product of Suzhou Dongwei Semiconductor Co., Ltd. to obtain the output characteristic curve, and the IGBT power device in Figure 4 is the output obtained by testing the IGW60N60H product of Infineon Co., Ltd. Characteristic curve, Figure 5 is the output characteristic curve obtained by testing the OSG60R074HSZ product and IGW60N60H product in parallel. From Figure 3, Figure 4 and Figure 5, it can be seen that the current density of the semiconductor power device after the MOSFET power device wafer and the IGBT power device wafer are connected in parallel is greater than the current density that the MOSFET power device can handle, and its saturation conduction voltage drop Less than the saturated turn-on voltage drop of the IGBT power device. In addition, encapsulating the MOSFET power device chip and the IGBT power device chip in the same package can simplify the design of the application circuit board.

以上具體實施方式及實施例是對本發明實施例提出的一種半導體功率器件的技術思想的具體支援，不能以此限定本發明實施例的保護範圍，凡是按照本發明實施例提出的技術思想，在本技術手段基礎上所做的任何均等變化或等效的改動，均仍屬於本發明實施例技術手段保護的範圍。 The above specific implementations and examples are specific support for the technical ideas of a semiconductor power device proposed by the embodiments of the present invention, and cannot be used to limit the protection scope of the embodiments of the present invention. All technical ideas proposed in accordance with the embodiments of the present invention are described in this Any equal changes or equivalent changes made on the basis of the technical means still fall within the protection scope of the technical means of the embodiments of the present invention.

儘管本發明實施例的實施方案已揭示如上，但其並不僅限於說明書及實施方式中所列運用，它完全可以被適用於各種適合本發明實施例的領域，對於熟悉本領域具有通常知識者，可容易地實現另外的修改，因此在不背離申請專利範圍及均等範圍所限定的一般概念下，本發明實施例並不限於特定的細節及在此示出與描述的圖例。 Although the implementation of the embodiment of the present invention has been disclosed as above, it is not limited to the applications listed in the specification and implementation mode. It can be applied to various fields suitable for the embodiment of the present invention. For those who are familiar with the field and have general knowledge, Additional modifications can be easily implemented, so without departing from the general concept defined by the scope of the patent application and the equivalent scope, the embodiments of the present invention are not limited to specific details and the legends shown and described herein.

11‧‧‧發射極 11‧‧‧Emitter

12‧‧‧集電極 12‧‧‧ Collector

13、23‧‧‧柵極 13, 23‧‧‧Grid

21‧‧‧源極 21‧‧‧Source

22‧‧‧漏極 22‧‧‧Drain

31‧‧‧源極電壓 31‧‧‧Source voltage

32‧‧‧漏極電壓 32‧‧‧Drain voltage

33‧‧‧柵極電壓 33‧‧‧Grid voltage

101‧‧‧IGBT功率器件 101‧‧‧IGBT power device

202‧‧‧MOSFET功率器件 202‧‧‧MOSFET power device

Claims (5)

一種半導體功率器件，包含：MOSFET功率器件晶片及IGBT功率器件晶片；其特徵係，前述MOSFET功率器件晶片及前述IGBT功率器件晶片以並聯方式封裝在同一個封裝體內，前述IGBT功率器件晶片具有負電阻-溫度係數；前述MOSFET功率器件晶片的源極與前述IGBT功率器件晶片的發射極均與前述封裝體的源極引腳直接連接；前述MOSFET功率器件晶片的漏極與前述IGBT功率器件晶片的集電極均與前述封裝體的漏極引腳連接；前述MOSFET功率器件晶片的柵極與前述IGBT功率器件晶片的柵極均與前述封裝體的柵極引腳連接。 A semiconductor power device comprising: a MOSFET power device wafer and an IGBT power device wafer; the feature is that the aforementioned MOSFET power device wafer and the aforementioned IGBT power device wafer are packaged in parallel in the same package, and the aforementioned IGBT power device wafer has a negative resistance -Temperature coefficient; the source of the aforementioned MOSFET power device wafer and the emitter of the aforementioned IGBT power device wafer are directly connected to the source pin of the aforementioned package; the drain of the aforementioned MOSFET power device wafer is a collection of the aforementioned IGBT power device wafer The electrodes are all connected to the drain pin of the aforementioned package; the gate of the aforementioned MOSFET power device wafer and the gate of the aforementioned IGBT power device wafer are both connected to the gate pin of the aforementioned package. 如申請專利範圍第1項所記載之半導體功率器件，其中，前述IGBT功率器件晶片為溝槽柵結構的IGBT功率電晶體。 The semiconductor power device described in the first item of the scope of patent application, wherein the aforementioned IGBT power device wafer is an IGBT power transistor with a trench gate structure. 如申請專利範圍第1項所記載之半導體功率器件，其中，前述IGBT功率器件晶片為平面柵結構的IGBT功率電晶體。 The semiconductor power device described in item 1 of the scope of patent application, wherein the aforementioned IGBT power device wafer is an IGBT power transistor with a planar gate structure. 如申請專利範圍第1項所記載之半導體功率器件，其中，前述MOSFET功率器件晶片為垂直雙擴散金屬-氧化物半導體場效應電晶體。 The semiconductor power device described in the first item of the scope of patent application, wherein the aforementioned MOSFET power device wafer is a vertical double diffused metal-oxide semiconductor field effect transistor. 如申請專利範圍第1項所記載之半導體功率器件，其中，前述MOSFET功率器件晶片為超級結構的功率電晶體。 The semiconductor power device described in item 1 of the scope of patent application, wherein the aforementioned MOSFET power device wafer is a power transistor with a super structure.
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