CN109244057B - Gallium nitride device of cascode cascade structure - Google Patents

Gallium nitride device of cascode cascade structure Download PDF

Info

Publication number
CN109244057B
CN109244057B CN201810770430.XA CN201810770430A CN109244057B CN 109244057 B CN109244057 B CN 109244057B CN 201810770430 A CN201810770430 A CN 201810770430A CN 109244057 B CN109244057 B CN 109244057B
Authority
CN
China
Prior art keywords
copper layer
gallium nitride
gan
face
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810770430.XA
Other languages
Chinese (zh)
Other versions
CN109244057A (en
Inventor
孙辉
胡腾飞
刘美华
林信南
陈东敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University Shenzhen Graduate School
Original Assignee
Peking University Shenzhen Graduate School
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University Shenzhen Graduate School filed Critical Peking University Shenzhen Graduate School
Priority to CN201810770430.XA priority Critical patent/CN109244057B/en
Publication of CN109244057A publication Critical patent/CN109244057A/en
Application granted granted Critical
Publication of CN109244057B publication Critical patent/CN109244057B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

The invention discloses a packaging substrate and a cascode gallium nitride device formed on the basis of the packaging substrate, wherein the packaging substrate comprises a substrate body, one end face of the substrate body is printed with a device circuit copper layer, the other end face of the substrate body is printed with a hot exhaust copper layer, the device circuit copper layer comprises a first copper layer face and a second copper layer face, and the first copper layer face and the second copper layer face are electrically isolated; the hot exhaust copper layer is provided with a plurality of gaps extending to the boundary of the substrate. The invention optimizes the structure of the packaging substrate and the relative position of the device circuit copper layer, changes the connection relation of the device circuit copper layer of the packaging substrate, the silicon device and the GaN device, realizes the pin arrangement of the same-side Gate, Drain and Source sequences of the cascode gallium nitride device, and simultaneously optimizes the common Source parasitic inductance playing a main role in the cascode gallium nitride device to the minimum value.

Description

Gallium nitride device of cascode cascade structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride device with a cascode cascade structure.
Background
A wide bandgap semiconductor device typified by SiC and GaN is known as a third generation semiconductor device. GaN devices have attracted attention of scholars at home and abroad. Gallium nitride high electron mobility transistors (GaN HEMTs) are the most important device type in the field of gallium nitride devices, and are substantially equivalent to MOSFETs in Si devices. GaN HEMTs can be classified into enhancement and depletion modes. For the monomer enhanced HEMT, on one hand, the maximum voltage endurance which can be realized at present is 250V, which is lower than the requirement of people for the expected application; on the other hand, it needs a transition of 1.5V to 4.5V threshold voltage from turn-on to full-on, which puts high requirements on the driving design of a typical integrated circuit Vgs of 5V or 6V. For a monomer depletion HEMT, although the withstand voltage can reach more than 600V, the driving voltage range is-30-2V, the voltage of a completely-conducting grid of a device is generally-5V, and therefore negative-voltage driving is needed to turn off when the device is used, and the device has the potential risk of short-circuit and direct connection.
The Cascode cascade (Cascode) type GaN HEMT is formed by connecting an enhanced Si VDMOS with a GaNHEMT Cascode, so that the on-off operation of the high-voltage depletion type HEMT is realized by driving a low-voltage VDMOS. The structure avoids the design of a negative voltage drive circuit, realizes the application of the high-voltage HEMT, and is the fastest, quick and effective method for pushing the HEMT to the application at present.
The TO mode is the simplest and most mature packaging process of a three-terminal power device, and a traditional TO mode-based Cascode packaging design introduces large common source parasitic inductance (CSI), so that switching delay of a Cascode system is caused, large loss is generated, and the application of a packaging module is not facilitated; in addition, the design of large current and high voltage HEMTs makes the package pins arranged based on PAD and the current IC module assembly rule difficult to be compatible.
Disclosure of Invention
The application provides a gallium nitride device of cascode structure, has realized that the encapsulation pin arranges according TO the order of Gate, Drain, Source, and through changing the packaging substrate in traditional TO encapsulation mode and walking the line direction and the interrelation between the line, has reduced the common Source parasitic inductance TO the minimum moreover.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a packaging substrate comprises a substrate body, wherein one end face of the substrate body is printed with a device circuit copper layer, the other end face of the substrate body is printed with a hot exhaust copper layer, the device circuit copper layer comprises a first copper layer face and a second copper layer face, and the first copper layer face and the second copper layer face are electrically isolated; the hot exhaust copper layer is provided with a plurality of gaps extending to the boundary of the substrate.
Forming a gallium nitride device of a cascade structure according to the substrate, wherein the gallium nitride device comprises a silicon device and a GaN device, the GaN device and the silicon device are respectively welded on a first copper layer surface through welding fluxes, the GaN device is not adjacent to the silicon device, a Source end of the GaN device is connected with a first copper layer surface through a connecting line and then connected with a Drain end of the silicon device, and a conducting loop of the gallium nitride device of the cascade structure is formed; connecting a Gate end of the GaN device with a Source end of the silicon device to form a driving loop of the gallium nitride device with a cascade structure; the Drain end of the GaN device and the Gate end of the silicon device are directly led out to one side of the packaging substrate to serve as Drain and Gate pins of the gallium nitride device of the cascode structure, the Source end of the silicon device is connected with the surface of a second copper layer, and the second copper layer is led out towards the same side of the packaging substrate to serve as the Source pin of the gallium nitride device of the cascode structure.
The invention has the beneficial effects that:
the invention optimizes the structure of the packaging substrate and the relative position of the device circuit copper layer, changes the connection relation of the device circuit copper layer of the packaging substrate, the silicon device and the GaN device, realizes the pin arrangement of the same-side Gate, Drain and Source sequence of the cascode gallium nitride device, and simultaneously optimizes the common Source parasitic inductance playing a main role in the cascode gallium nitride device to the minimum value.
Drawings
FIG. 1 is a schematic diagram of a cascode gallium nitride device connection;
fig. 2 is a schematic diagram of parasitic inductance of a cascode gallium nitride device formed by a conventional TO package mode;
FIG. 3 is a schematic end view of a substrate body according to an embodiment of the invention;
FIG. 4 is another schematic end view of a substrate body according to an embodiment of the invention;
FIG. 5 is a schematic diagram of the PAD shape of a GaN HEMT device in an embodiment of the invention;
FIG. 6 is a schematic diagram of the PAD shape of a Si VDMOS device in an embodiment of the present invention;
FIG. 7 is a schematic view of the mounting positions of the GaN HEMT device and the Si VDMOS device on the substrate and the PAD connection line according to the embodiment of the invention;
fig. 8 is a schematic diagram of parasitic inductance of a cascode gallium nitride device in accordance with an embodiment of the present invention.
In the figure, 1-substrate bulk, 2-first copper level, 3-second copper level, 4-hot-vented copper layer, 5-GaN HEMT device, 6-Si VDMOS device.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The connection principle of the Cascode gallium nitride device is shown in fig. 1, as an example, the GaN device and the silicon device are respectively selected from a GaN HEMT device 5 and a Si VDMOS device 6, and the Cascode gallium nitride device may be abbreviated as a GaN HEMT Cascode.
In the manufacturing process of the GaN HEMT Cascode, on one hand, the Source end of the GaN HEMT needs to be connected with the Drain end of the SiVDMOS to form a conducting loop of the whole GaN HEMT Cascode structure; on the other hand, the Gate terminal of the GaN HEMT needs to be connected with the Source terminal of the Si VDMOS to form a driving circuit of the GaN HEMT. And finally, leading out the Drain end of the GaN HEMT, the Source end and the Gate end of the Si VDMOS as the Drain, the Source and the Gate of the GaN HEMT Cascode structure.
FIG. 2 is a schematic diagram of the parasitic inductance between the wire and device interconnect through a conventional TO-mode package structure, as can be seen in L1,L2,L3The common parasitic inductance is called common source parasitic inductance (CSI) which is shared by Power L oop of GaN HEMT Cascode, Si VDMOS and Drive L oop of GaN HEMT and is the most dominant parasitic inductance affecting the response speed and switching loss of the system, so it is urgently needed to design and develop a new package substrate and a connection method of GaN device and silicon device on the substrate, so as to reduce or eliminate L as much as possible1，L2And L3Is generated.
An embodiment of the invention is given below:
a gallium nitride device with a cascode structure comprises a substrate body 1, wherein one end face of the substrate body 1 is printed with a device circuit copper layer, the other end face of the substrate body 1 is printed with a hot exhaust copper layer, the device circuit copper layer comprises a first copper layer face 2 and a second copper layer face 3, and the first copper layer face 2 and the second copper layer face 3 are electrically isolated;
referring to fig. 3, the substrate body 1 has a rectangular structure, is made of aluminum nitride ceramic, and has a surface directly plated with copper, the first copper layer 2 and the second copper layer 3 are printed on the end surface of the substrate body 1, and a gap is left between the first copper layer 2 and the second copper layer 3 to form electrical isolation. In other embodiments, the first and second copper levels 2, 3 can also be designed in other shapes to form an electrical isolation.
Referring to fig. 4, in the present embodiment, the hot exhaust copper layer 4 includes a plurality of groups of equal-sized regular hexagonal copper layers, and the plurality of groups of regular hexagonal copper layers are adjacent to each other at small intervals on opposite sides in sequence; in other embodiments, the hot-exhaust copper layer 4 may also be an arrangement or combination of other shape units, and actually, only the copper metal needs to be removed uniformly on the whole surface of the hot-exhaust copper layer 4, so that the removal gap can extend to the boundary of the substrate body 1, and the hot exhaust is solved when the package is soldered on the back of the substrate body 1.
In order to enable the packaging substrate to have better conductivity, corrosion resistance and friction resistance, the packaging substrate needs to be subjected to surface treatment, and a nickel-palladium gold layer is arranged on a device circuit copper layer and a hot exhaust copper layer through chemical nickel-palladium-gold.
A specific set of shape and dimension parameters of the substrate body 1, the device circuit copper layer and the thermal copper-exhaust layer 4 are given below, and it should be noted that the design of the substrate body 1, the device circuit copper layer and the thermal copper-exhaust layer 4 obtained by adjusting the shape and dimension parameters without creative work by those skilled in the art also belongs to the protection scope of the present invention. In this embodiment, the thickness of the substrate body 1 ranges from 0.5mm to 0.55mm, and the thicknesses of the device circuit copper layer and the hot-exhaust copper layer are greater than 30 μm. The substrate body 1 is rectangular and has a size of 7.0 × 8.5mm2The first copper layer face 2 printed on the substrate body 1 has a size of 4.0 x 7.5mm2The second copper layer face 3 has a size of 1.0 x 7.5mm2The long sides of the first copper layer surface 2 and the second copper layer surface 3 are opposite, and the first copper layer surface 2 and the second copper layer surface 3 are separated by 1mm to form electrical isolation; the three other sides of the first and second copper levels 2 and 3, except the opposite side, are 0.5mm from the edge of the substrate body 1.
A gallium nitride device (GaN HEMT Cascode) with a Cascode structure is formed on the basis of the packaging substrate, and comprises a silicon device and a GaN device, wherein the silicon device and the GaN device are arranged on the packaging substrate, in the embodiment, the GaN device is a GaN HEMT device 5, the silicon device is a Si VDMOS device 6, the GaN device and the Si VDMOS device are both from samples of foundation 6inch Fab, the thickness of the device is 1mm of GaN HEMT and 250 μm of Si VDMOS, and PAD structures of the GaN HEMT device 5 and the Si VDMOS device 6 are shown in fig. 5 and 6; in other embodiments, the silicon device and the GaN device may be selected to have the same function but different layout structures.
Referring to fig. 7, the GaN HEMT device 5 and the Si VDMOS device 6 are respectively welded on the first copper layer 2 through conductive adhesive, the GaN HEMT device 5 and the Si VDMOS device 6 are not adjacent to each other, and are spaced by 2mm, the Source end of the GaN HEMT device 5 is connected with the first copper layer 2 and then connected with the Drain end of the Si VDMOS device 6, so as to form a conduction loop of the gallium nitride device in the cascode structure; the Gate end of the GaN HEMT device 5 is connected with the Source end of the Si VDMOS device 6 to form a driving loop of the gallium nitride device with a cascade structure; the Drain end of the GaN HEMT device 5 and the Gate end of the Si VDMOS device 6 are directly led out to one side of the packaging substrate to be used as a Drain pin and a Gate pin of the gallium nitride device of the cascade structure, the Source end of the Si VDMOS device 6 is connected with the second copper layer 3, and the second copper layer 3 leads out pins to the same side of the Drain pin and the Gate pin of the packaging substrate to be used as a Source pin of the gallium nitride device of the cascade structure. The Drain end of the Si VDMOS device 6 leads out a Drain pin to one side of the packaging substrate through a large-current channel, and the second copper layer 3 leads out a Source pin to one side of the packaging substrate through the large-current channel. Double-line representation is used in fig. 7.
Through the device arrangement, the pins are easily led out according TO the sequence of the Gate, Drain and Source pins, the position of a Gate end connecting wire terminal of the GaN HEMT device 5 is changed from the original substrate wire end TO the Source PAD of the SiVDMOS device 6, and common Source parasitic inductance L2 is removed from the Drive L oop of the GaN HEMT device 5, so that the influence of L2 on the whole GaN HEMT Cascode system is reduced.
The GaN HEMT Cascode is packaged by a packaging structure with proper size and good heat dissipation effect, the packaging has higher requirements on the thermal stability and the insulativity of a packaging filling material, the TO-3PN semi-packaging mode is finally selected in the embodiment, and the filling material is selected from the latest EMC thermal stability material.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (7)

1. A gallium nitride device of a cascode structure, comprising: the device comprises a substrate body (1), wherein one end face of the substrate body (1) is printed with a device circuit copper layer, the other end face of the substrate body is printed with a hot exhaust copper layer (4), the device circuit copper layer comprises a first copper layer face (2) and a second copper layer face (3), and the first copper layer face (2) and the second copper layer face (3) are electrically isolated; a plurality of gaps extending to the boundary of the substrate are arranged on the hot exhaust copper layer (4);
further comprising: the GaN device and the silicon device are respectively welded on the first copper layer surface (2) through welding fluxes, the GaN device and the silicon device are adjacent and not connected, and the Source end of the GaN device is connected with the first copper layer surface (2) and then connected with the Drain end of the silicon device to form a conduction loop of the gallium nitride device with a cascade structure; the Gate end of the GaN device is connected with the Source end of the silicon device to form a driving loop of the gallium nitride device with a cascade structure; the Drain end of the GaN device and the Gate end of the silicon device are directly led out to one side of the packaging substrate to serve as Drain and Gate pins of the gallium nitride device of the cascode structure, the Source end of the silicon device is connected with the second copper layer (3), and the second copper layer (3) is led out to the same side of the packaging substrate to serve as the Source pin of the gallium nitride device of the cascode structure.
2. Gallium nitride device according to claim 1, characterized in that the first (2) and second (3) copper levels are both rectangular structures, the first (2) and second (3) copper levels being spaced apart so as to form an electrical isolation.
3. Gallium nitride device according to claim 1 or 2, characterized in that the substrate body (1) is made of aluminum nitride ceramic.
4. The gallium nitride device of claim 3, wherein the device wiring copper layer is provided with a nickel palladium gold layer.
5. Gallium nitride device according to claim 4, characterized in that the substrate body (1) has a thickness in the range of 0.5 to 0.55mm, the device wiring copper layer and the hot-exhaust copper layer (4) having a thickness greater than 30 μm.
6. Gallium nitride device according to claim 5, characterized in that the substrate body 1 is of rectangular configuration, the first (2) and second (3) copper levels being spaced apart by 1 mm.
7. Gallium nitride device according to claim 1, characterized in that said GaN device is selected from GaN HEMT device (5) and said silicon device is selected from Si VDMOS device (6); the Gate, Drain and Source of the gallium nitride device of the cascode structure are sequentially arranged on the same side of the packaging substrate according to the sequence of the Gate, Drain and Source.
CN201810770430.XA 2018-07-13 2018-07-13 Gallium nitride device of cascode cascade structure Active CN109244057B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810770430.XA CN109244057B (en) 2018-07-13 2018-07-13 Gallium nitride device of cascode cascade structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810770430.XA CN109244057B (en) 2018-07-13 2018-07-13 Gallium nitride device of cascode cascade structure

Publications (2)

Publication Number Publication Date
CN109244057A CN109244057A (en) 2019-01-18
CN109244057B true CN109244057B (en) 2020-07-14

Family

ID=65072585

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810770430.XA Active CN109244057B (en) 2018-07-13 2018-07-13 Gallium nitride device of cascode cascade structure

Country Status (1)

Country Link
CN (1) CN109244057B (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013091143A1 (en) * 2011-12-21 2013-06-27 武汉飞恩微电子有限公司 Microchannel direct bonded copper substrate and packaging structure and process of power device thereof
CN102655731A (en) * 2012-05-10 2012-09-05 武汉正维电子技术有限公司 Structure of heat radiation metal substrate for power amplifier
US9818716B2 (en) * 2014-10-20 2017-11-14 Mitsubishi Electric Corporation Power module
CN109314107B (en) * 2016-05-26 2022-12-06 埃克斯甘公司 Integrated circuit comprising a chip formed by high-voltage transistors and comprising a chip formed by low-voltage transistors

Also Published As

Publication number Publication date
CN109244057A (en) 2019-01-18

Similar Documents

Publication Publication Date Title
US9620472B2 (en) Method of manufacturing an electronic component
KR101737149B1 (en) Electronic component, method of forming an electronic component, assembly, half bridge, and bridge circuit for low emi circuits
US9818686B2 (en) Semiconductor modules and methods of forming the same
US9099441B2 (en) Power transistor arrangement and method for manufacturing the same
US9324645B2 (en) Method and system for co-packaging vertical gallium nitride power devices
US9431394B2 (en) Power semiconductor package with gate and field electrode leads
CN103546141A (en) Integrated semiconductor device and a bridge circuit with the integrated semiconductor device
US20210408273A1 (en) Integrated design for iii-nitride devices
US9263440B2 (en) Power transistor arrangement and package having the same
CN105702638A (en) Integrated power assembly with reduced form factor and enhanced thermal dissipation
CN110620138A (en) Transistor device
US10074597B2 (en) Interdigit device on leadframe for evenly distributed current flow
KR20060112691A (en) Complimentary nitride transistors vertical and common drain
CN109244057B (en) Gallium nitride device of cascode cascade structure
JP2013026342A (en) Nitride semiconductor device
US10199347B2 (en) Semiconductor device
CN112420681B (en) Chip packaging structure
JP2008177475A (en) Electronic component
JP2001274406A (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant