CN109244057B - 一种共源共栅级联结构的氮化镓器件 - Google Patents
一种共源共栅级联结构的氮化镓器件 Download PDFInfo
- Publication number
- CN109244057B CN109244057B CN201810770430.XA CN201810770430A CN109244057B CN 109244057 B CN109244057 B CN 109244057B CN 201810770430 A CN201810770430 A CN 201810770430A CN 109244057 B CN109244057 B CN 109244057B
- Authority
- CN
- China
- Prior art keywords
- copper layer
- gallium nitride
- gan
- face
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
本发明公开了一种封装基板及基于该基板形成的共源共栅氮化镓器件,该封装基板包括基板本体,基板本体的一个端面印制器件线路铜层,另一个端面印制热排气铜层,器件线路铜层包括第一铜层面和第二铜层面,第一铜层面和第二铜层面之间电气隔离;热排气铜层上设置有若干条延伸到基板边界的间隙。本发明优化了封装基板的结构和器件线路铜层的相对位置,改变封装基板器件线路铜层和硅器件及GaN器件的连线关系,不仅实现了共源共栅氮化镓器件的同侧Gate、Drain、Source顺序的管脚排布,同时,也把其中起主要的作用的共源寄生电感优化到了最小值。
Description
技术领域
本发明涉及半导体技术领域,具体涉及一种共源共栅级联结构的氮化镓器件。
背景技术
以SiC和GaN为代表的宽禁带半导体器件被誉为第三代半导体器件。GaN器件目前已引起国内外学者的关注。氮化镓高电子迁移率晶体管(GaN HEMT)是氮化镓器件领域最为重要的器件类型,基本等同于MOSFET在Si器件中的地位。GaN HEMT可以分为增强型和耗尽型两种。对于单体增强型HEMT,一方面,目前可实现的最大耐压为250V,低于人们对其预期应用的需求;另一方面,其从开启到完全导通,需要阈值电压1.5V到4.5V的过渡,这对于一般集成电路Vgs为5V或者6V的驱动设计提出了很高的要求。对于单体耗尽型HEMT,虽然耐压可以达到600V以上,但是,驱动电压范围为-30-2V,器件完全导通栅极电压一般为-5V,因此使用时需要负压驱动进行关断,有短路直通的潜在危险。
共源共栅级联(Cascode)型GaN HEMT通过把工艺成熟的增强型Si VDMOS与GaNHEMT共源共栅连接,从而实现通过驱动低压VDMOS来实现高压耗尽型HEMT的通断操作。这种结构,既避免了负压驱动电路的设计,同时也实现了高压HEMT的应用,是当前将HEMT推向应用的最快捷有效的方法。
TO模式是三端功率器件最简单、最成熟的封装工艺,传统基于TO模式的Cascode封装设计会引入较大的共源寄生电感(CSI),造成Cascode系统的开关延迟,并产生较大的损耗,不利于封装模块的应用;另外,大电流、高压HEMTs的设计,使得基于PAD排布的封装管脚与当前IC模块组装规则较难兼容。
发明内容
本申请提供一种共源共栅级联结构的氮化镓器件,实现了封装管脚按照Gate,Drain,Source的顺序排布,而且通过改变传统TO封装模式中封装基板走线方向以及连线之间的相互关系,将共源寄生电感降低到了最小值。
为了达到上述目的,本发明的技术方案如下:
一种封装基板,包括基板本体,基板本体的一个端面印制器件线路铜层,另一个端面印制热排气铜层,器件线路铜层包括第一铜层面和第二铜层面,第一铜层面和第二铜层面之间电气隔离;热排气铜层上设置有若干条延伸到基板边界的间隙。
根据上述基板形成共源共栅级联结构的氮化镓器件,包括硅器件和GaN器件,GaN器件和硅器件分别通过焊料焊接在第一铜层面上,GaN器件和硅器件相邻不相接,GaN器件的Source端与第一铜层面连线进而与硅器件的Drain端相连,形成共源共栅级联结构的氮化镓器件的导通回路;GaN器件的Gate端与硅器件的Source端连线,形成共源共栅级联结构的氮化镓器件的驱动回路;GaN器件的Drain端、硅器件的Gate端直接向封装基板的一侧引出,作为共源共栅级联结构的氮化镓器件的Drain和Gate管脚,硅器件的Source端与第二铜层面连线,第二铜层面向封装基板的同一侧引出,作为共源共栅级联结构的氮化镓器件的Source管脚。
本发明的有益效果为:
本发明优化封装基板的结构和器件线路铜层的相对位置,改变封装基板器件线路铜层和硅器件及GaN器件的连线关系,不仅实现了共源共栅氮化镓器件的同侧Gate、Drain、Source顺序的管脚排布,同时,也把其中起主要的作用的共源寄生电感优化到了最小值。
附图说明
图1为共源共栅氮化镓器件连接原理图;
图2为通过传统TO封装模式形成的共源共栅氮化镓器件的寄生电感示意图;
图3为本发明实施例基板本体的一个端面示意图;
图4为本发明实施例基板本体的另一个端面示意图;
图5为本发明实施例中GaN HEMT器件的PAD形状示意图;
图6为本发明实施例中Si VDMOS器件的PAD形状示意图;
图7为本发明实施例GaN HEMT器件和Si VDMOS器件在基板上安装位置及PAD连线示意图;
图8为本发明实施例共源共栅氮化镓器件的寄生电感的示意图。
图中,1-基板本体,2-第一铜层面,3-第二铜层面,4-热排气铜层,5-GaN HEMT器件,6-Si VDMOS器件。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明作进一步地详细描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
共源共栅氮化镓器件连接原理如图1所示,作为示例,GaN器件和硅器件分别选用GaN HEMT器件5和Si VDMOS器件6,共源共栅氮化镓器件可简写为GaN HEMT Cascode。
GaN HEMT Cascode的制作过程中,一方面,需要将GaN HEMT的Source端与SiVDMOS的Drain端相连,形成整个GaN HEMT Cascode结构的导通回路;另一方面,需要将GaNHEMT的Gate端与Si VDMOS的Source端相连,形成GaN HEMT的驱动回路。最后将GaN HEMT的Drain端,Si VDMOS的Source端和Gate端引出,作为GaN HEMT Cascode结构的Drain,Source和Gate。
图2为通过传统的TO模式封装结构中导线及器件互连间的寄生电感示意图,由图中可见,其中L1,L2,L3被GaN HEMT Cascode的Power Loop以及Si VDMOS和GaN HEMT的DriveLoop所共用,被称为共源寄生电感(CSI),其是影响系统的响应速度和开关损耗最主要的寄生电感,因此,亟待设计开发一种新的封装基板及GaN器件和硅器件在基板上的连线方式,从而应尽可能的减小或消除L1,L2和L3的产生。
下面给出本发明的一个实施例:
一种共源共栅级联结构的氮化镓器件,包括基板本体1,基板本体1的一个端面印制器件线路铜层,另一个端面印制热排气铜层,器件线路铜层包括第一铜层面2和第二铜层面3,第一铜层面2和第二铜层面3之间电气隔离;
参见图3,基板本体1为矩形结构,由氮化铝陶瓷制成,表面可直接镀铜,第一铜层面2和第二铜层面3印制在基板本体1的端面上,第一铜层面2和第二铜层面3之间留有间隙从而形成电气隔离。在其他实施例中,第一铜层面2和第二铜层面3也可以设计为构成电气隔离的其他形状。
参见图4,本实施例中,热排气铜层4包括多组等大的正六边形铜层面,多组正六边形铜层面依次对边小间隔邻接;在其他实施例中,热排气铜层4也可以是其他形状单元的排列或组合,实际上,只需要在热排气铜层4整面均匀的去除铜金属,使得去除间隙能够延伸到基板本体1边界,解决基板本体1背部封装焊接时热排气。
为了使封装基板具有更好的导电性能、耐腐蚀性能和抗摩擦性能,需对封装基板进行表面处理,对器件线路铜层和热排气铜层上通过化学镍钯金设置有镍钯金层。
下面给出基板本体1、器件线路铜层和热排气铜层4的一组具体的形状和尺寸参数,需要说明的是,本领域普通技术人员在没有做出创造性劳动前提下所调整的形状、尺寸参数所获得的基板本体1、器件线路铜层和热排气铜层4设计,也属于本发明的保护范围中。在本实施例中,基板本体1厚度范围0.5~0.55mm,器件线路铜层和热排气铜层厚度大于30μm。基板本体1为矩形,尺寸为7.0*8.5mm2,印制在基板本体1上的第一铜层面2的尺寸为4.0*7.5mm2、第二铜层面3的尺寸为1.0*7.5mm2,第一铜层面2和第二铜层面3的长边正对,第一铜层面2和第二铜层面3之间间隔1mm以形成电气隔离;除了相对的一边,第一铜层面2和第二铜层面3三个其它边距离基板本体1的边沿均为0.5mm。
基于上述封装基板形成共源共栅级联结构的氮化镓器件(GaN HEMT Cascode),包括设置在封装基板上的硅器件和GaN器件,在本实施例中,GaN器件选用GaN HEMT器件5,硅器件选用Si VDMOS器件6,均来源于Founder 6inch Fab的样品,器件厚度为GaN HEMT 1mm,Si VDMOS 250μm,GaN HEMT器件5和Si VDMOS器件6的PAD结构如图5和图6所示;在其他实施例中,硅器件和GaN器件可以选用其他相同功能但布局结构不同的器件。
参见图7,GaN HEMT器件5和Si VDMOS器件6分别通过导电胶焊接在第一铜层面2上,GaN HEMT器件5和Si VDMOS器件6相邻不相接,它们之间相距2mm,GaN HEMT器件5的Source端与第一铜层面2连线进而与Si VDMOS器件6的Drain端相连,形成共源共栅级联结构的氮化镓器件的导通回路;GaN HEMT器件5的Gate端与Si VDMOS器件6的Source端连线,形成共源共栅级联结构的氮化镓器件的驱动回路;GaN HEMT器件5的Drain端、Si VDMOS器件6的Gate端直接向封装基板的一侧引出,作为共源共栅级联结构的氮化镓器件的Drain管脚和Gate管脚,Si VDMOS器件6的Source端与第二铜层面3连线,第二铜层面3向封装基板Drain管脚和Gate管脚的同一侧引出管脚,作为共源共栅级联结构的氮化镓器件的Source管脚。Si VDMOS器件6的Drain端通过大电流通道向封装基板一侧引出Drain管脚,第二铜层面3通过大电流通道向封装基板一侧引出Source管脚。图7中采用双线表示。
通过上述器件排布不仅很容易实现管脚按照Gate,Drain和Source管脚的顺序引出;而且通过把GaN HEMT器件5的Gate端连线终端的位置由原来的基板走线端改到SiVDMOS器件6的Source PAD上,实现将共源寄生电感L2从GaN HEMT器件5的Drive Loop中去除,从而降低了L2对整个GaN HEMT Cascode系统的影响。图8给出了优化后的GaN HEMTCascode寄生电感的示意图,很明显的可以看出L2仅由Si VDMOS器件6的Drive Loop和GaNHEMT Cascode的Power Loop共用,不再存在于GaN HEMT器件5的Drive Loop中,实现了TO模式中GaN HEMT Cascode结构互连线寄生电感的最小化。
选用合适大小并且散热效果好的封装结构对上述GaN HEMT Cascode进行封装,封装对于封装填充材料的热稳定性和绝缘性也有较高的要求,本实施例最终选用TO-3PN的半包封的形式,填充材料选用最新的EMC热稳定性材料。
以上应用了具体个例对本发明进行阐述,只是用于帮助理解本发明,并不用以限制本发明。对于本发明所属技术领域的技术人员,依据本发明的思想,还可以做出若干简单推演、变形或替换。
Claims (7)
1.一种共源共栅级联结构的氮化镓器件,其特征在于,包括:基板本体(1),基板本体(1)的一个端面印制器件线路铜层,另一个端面印制热排气铜层(4),所述器件线路铜层包括第一铜层面(2)和第二铜层面(3),所述第一铜层面(2)和第二铜层面(3)之间电气隔离;所述热排气铜层(4)上设置有若干条延伸到基板边界的间隙;
还包括:硅器件和GaN器件,所述GaN器件和硅器件分别通过焊料焊接在所述第一铜层面(2)上,所述GaN器件和硅器件相邻不相接,所述GaN器件的Source端与第一铜层面(2)连线进而与硅器件的Drain端相连,形成共源共栅级联结构的氮化镓器件的导通回路;所述GaN器件的Gate端与硅器件的Source端连线,形成共源共栅级联结构的氮化镓器件的驱动回路;GaN器件的Drain端、硅器件的Gate端直接向封装基板的一侧引出,作为共源共栅级联结构的氮化镓器件的Drain和Gate管脚,硅器件的Source端与第二铜层面(3)连线,第二铜层面(3)向封装基板的同一侧引出,作为共源共栅级联结构的氮化镓器件的Source管脚。
2.根据权利要求1所述的氮化镓器件,其特征在于,所述第一铜层面(2)和第二铜层面(3)均为矩形结构,第一铜层面(2)和第二铜层面(3)间隔设置从而形成电气隔离。
3.根据权利要求1或2所述的氮化镓器件,其特征在于,所述基板本体(1)由氮化铝陶瓷制成。
4.根据权利要求3所述的氮化镓器件,其特征在于,所述器件线路铜层上设置有镍钯金层。
5.根据权利要求4所述的氮化镓器件,其特征在于,所述基板本体(1)厚度范围0.5~0.55mm,所述器件线路铜层和热排气铜层(4)厚度大于30μm。
6.根据权利要求5所述的氮化镓器件,其特征在于,所述基板本体1为矩形结构,第一铜层面(2)和第二铜层面(3)之间间隔1mm。
7.根据权利要求1所述的氮化镓器件,其特征在于,所述GaN器件选用GaN HEMT器件(5),所述硅器件选用Si VDMOS器件(6);所述共源共栅级联结构的氮化镓器件的Gate、Drain和Source在封装基板的同一侧按Gate、Drain、Source顺序依次排布。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810770430.XA CN109244057B (zh) | 2018-07-13 | 2018-07-13 | 一种共源共栅级联结构的氮化镓器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810770430.XA CN109244057B (zh) | 2018-07-13 | 2018-07-13 | 一种共源共栅级联结构的氮化镓器件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109244057A CN109244057A (zh) | 2019-01-18 |
CN109244057B true CN109244057B (zh) | 2020-07-14 |
Family
ID=65072585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810770430.XA Active CN109244057B (zh) | 2018-07-13 | 2018-07-13 | 一种共源共栅级联结构的氮化镓器件 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN109244057B (zh) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013091143A1 (zh) * | 2011-12-21 | 2013-06-27 | 武汉飞恩微电子有限公司 | 微通道直接敷铜基板及其功率器件的封装结构和工艺 |
CN102655731A (zh) * | 2012-05-10 | 2012-09-05 | 武汉正维电子技术有限公司 | 一种功率放大器的散热金属基板结构 |
US9818716B2 (en) * | 2014-10-20 | 2017-11-14 | Mitsubishi Electric Corporation | Power module |
WO2017203186A1 (fr) * | 2016-05-26 | 2017-11-30 | Exagan | Circuit intégré comprenant une puce formée d'un transistor à haute tension et comprenant une puce formée d'un transistor à basse tension |
-
2018
- 2018-07-13 CN CN201810770430.XA patent/CN109244057B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN109244057A (zh) | 2019-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9620472B2 (en) | Method of manufacturing an electronic component | |
KR101737149B1 (ko) | 낮은 emi 회로를 위한 전자 부품, 전자 부품 형성 방법, 어셈블리, 하프 브리지 및 브리지 회로 | |
US9818686B2 (en) | Semiconductor modules and methods of forming the same | |
US9324645B2 (en) | Method and system for co-packaging vertical gallium nitride power devices | |
US9099441B2 (en) | Power transistor arrangement and method for manufacturing the same | |
US9431394B2 (en) | Power semiconductor package with gate and field electrode leads | |
US9263440B2 (en) | Power transistor arrangement and package having the same | |
CN103546141A (zh) | 集成半导体装置和具有集成半导体装置的桥接电路 | |
US10074597B2 (en) | Interdigit device on leadframe for evenly distributed current flow | |
CN110620138A (zh) | 晶体管器件 | |
US20240014312A1 (en) | Integrated design for iii-nitride devices | |
KR20060112691A (ko) | 컴플리멘터리 질화물 트랜지스터의 수직 및 공통 드레인 | |
CN109244057B (zh) | 一种共源共栅级联结构的氮化镓器件 | |
JP2013026342A (ja) | 窒化物半導体装置 | |
US10199347B2 (en) | Semiconductor device | |
CN112420681B (zh) | 一种芯片封装结构 | |
TWI844645B (zh) | 用於三族氮化物元件的整合設計 | |
JP2008177475A (ja) | 電子部品 | |
JP2001274406A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |