TWI730129B - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention is an arrangement jig, arrangement method and transfer method. It is an arrangement jig (100) provided with a plurality of accommodating parts (101) capable of accommodating sheet-like bodies (CP), and is characterized by the accommodating corners of the accommodating part (101) The part (103) is when each accommodating sheet (CP) is in a plurality of accommodating parts (101) and the sheet-like body (CP) is joined to the wall part (102) of the accommodating part (101), the sheet-like body (CP) The corner portion of the sheet-shaped body is an arrangement jig (100) formed without contacting the receiving corner portion (103).

Description

Manufacturing method of semiconductor device

The invention relates to an arrangement jig, an arrangement method and a reposting method.

In the past, in the semiconductor manufacturing process, semiconductor wafers (hereinafter, sometimes referred to as wafers) were cut into specific shapes and specific sizes, and then sliced into plural semiconductor wafers (hereinafter, It may be simply called a chip), which is mounted on an object to be mounted such as a lead frame or a substrate after increasing the mutual spacing of the individual chips.

In recent years, the miniaturization, weight reduction, and high performance of electronic devices have progressed. For semiconductor devices mounted in electronic equipment, miniaturization, thinning, and high density are also required. The semiconductor chip has a package that is mounted close to the size of the semiconductor chip. Such a package is also called Chip Scale Package (CSP). As one of the processes for manufacturing CSP, wafer level packaging (Wafer Level Package; WLP) can be cited. In WLP, prior to dicing and packaging into individual pieces, external electrodes and the like are formed on the chip circuit formation surface, and finally the packaged wafer including the chip is cut into individual pieces. The WLP system includes a fan-in (Fan-In) type and a fan-out (Fan-Out) type. In fan-out WLP (hereinafter, abbreviated as FO-WLP), the semiconductor chip is made larger than the chip size In the range, the semiconductor wafer enclosure is formed by covering it with the sealing member, and the rewiring layer or external electrode is formed not only on the circuit surface of the semiconductor wafer but also on the surface of the sealing member.

For example, in Document 1 (International Publication No. 2010/058646), it is described that a plurality of semiconductor wafers are sliced from a semiconductor wafer, and the circuit formation surface is left, and a mold member is used to form an expansion around the periphery. The process of wafers, and the process of manufacturing semiconductor packages in which the redistribution pattern extends beyond the semiconductor chip. In the manufacturing method described in Document 1, before forming a plurality of semiconductor chips to be sliced with a model member, the wafer adhesive tape for expansion is pasted, and the wafer adhesive tape is stretched to make the plural semiconductor chips. The distance between semiconductor wafers expands.

As a separation method for increasing the distance between the wafers (sheets), there is known a frame support means (supporting means) that supports the wafer (plate-like member) integrated with the frame by a thin film (adhesive sheet). ), and a person who moves relative to the film surface support mechanism (separation platform) (for example, refer to Document 2 (Japanese Patent Laid-Open No. 2012-204747)). In the method of enlarging the mutual spacing of such wafers, for example, applying tension in four directions of +X axis direction, -X axis direction, +Y axis direction, and -Y axis direction to the adhesive sheet, for example, by detecting means If it is detected that the chip located at the outermost periphery reaches the specified position, the operation of expanding the interval ends.

In the conventional method as described in Document 2, the adhesive sheet is added to the above-mentioned four directions, and for these combined directions, that is, the combined direction of the +X axis direction and the +Y axis direction, the +X axis direction and the − Synthetic square in Y-axis direction Tension is applied to the composite direction of the -X axis direction and the +Y axis direction, and the composite direction of the -X axis direction and the -Y axis direction. As a result, there is a difference between the interval between the wafers on the inner side and the interval between the wafers on the outer side.

However, because the difference in the interval is extremely small, each chip is equally spaced, and the position derived from the calculation (hereinafter referred to as the theoretical position) is used as a reference to pass through the conveying device, and It is conveyed by a conveying means such as a pick-up device, and is mounted on a to-be-loaded object to form a manufactured product. As a result, the relative positional relationship between the chip and the mounted object of the manufactured product is slightly shifted, and the connection position of the wire bonding is shifted, and the position of the chip and the terminal of the mounted object is shifted. It becomes impossible to obtain such conduction, which causes the disadvantage of lowering the yield of the product.

However, such a problem is not only related to the manufacture of semiconductor devices, but may also occur in dense mechanical components and fine decorations.

As in the manufacturing method described in Document 1, when the distance between the plural semiconductor chips is enlarged, after the individual semiconductor wafers are sliced, the expansion process is performed only once, and there is a problem that the distance between the plural semiconductor chips cannot be sufficiently enlarged. The danger of distance. On the other hand, in the first expansion process, when it is used as a thin sheet that stretches and supports a plurality of semiconductor wafers, the thin sheet may break and crack. As a result, the gaps between the semiconductor wafers on the wafer are uneven, and the semiconductor wafers are separated from the wafer, and there is a risk that the semiconductor wafers may degrade in rationality.

However, according to the pick and place method, although a plurality of sheets can be arranged at equal intervals, a pick and place device must be prepared. more Moreover, in the pick-and-place method, it is impossible to arrange the plural pieces of flakes together. Therefore, it is desired to arrange a plurality of sheet-like bodies more quickly by a simpler method.

As other arranging methods, a method of arranging a plurality of semiconductor chips using an arranging jig has also been reviewed. For example, it is possible to use an array jig with a plurality of accommodating parts. The accommodating part is formed so as to accommodate the semiconductor wafer. When using such an arrangement jig to arrange the semiconductor wafers, first, the semiconductor wafers are accommodated in the accommodating part. Then, at least one of the arrangement jig and the semiconductor chip is moved, and the position or tilt of the semiconductor chip is adjusted when the semiconductor chip is brought into close contact with the wall of the accommodating part. During the adjustment, the corners of the semiconductor wafer and the corners of the receiving portion are in contact, and the sheet-shaped body may be inclined.

The object of the present invention is to provide an arrangement jig and an arrangement method that can arrange a plurality of flakes at more even intervals easily and quickly. Another object of the present invention is to provide a transfer method capable of transferring a plurality of sheet-like bodies arranged by the arrangement method to a support.

The arrangement jig according to one aspect of the present invention is an arrangement jig provided with a plurality of accommodating parts capable of accommodating sheet-like bodies, and is characterized in that the accommodating corners of the aforementioned accommodating parts are each arranged so that the aforementioned sheet-like bodies are housed in the plural accommodating When the sheet-like body is brought into contact with the wall of the receiving portion, the sheet-like body corners of the sheet-like body are formed without contacting the receiving corners.

In the arrangement jig related to one aspect of the present invention, the aforementioned plural The accommodating parts are preferably arranged in a lattice shape.

In the arrangement jig according to one aspect of the present invention, the sheet-like system has: a first side surface and a second side surface adjacent to the first side surface; the corner portion of the sheet-shaped body is positioned at an end of the first side surface Part and the end of the second side surface; the wall part of the accommodating part has: a first side wall and a second side wall adjacent to the first side wall; the accommodating corner is located at the end of the first side wall And the end of the second side wall; the accommodating corner has: a surface recessed than the first side wall, and a recessed portion in which the surface of the second side wall is deeper, so that the first side surface of the sheet-like body When abutting against the first side wall of the accommodating portion, and when the second side surface of the sheet-shaped body is brought into contact with the second side wall of the accommodating portion, the corner portion of the sheet-shaped body of the sheet-shaped body is accommodated It is preferable to use the recessed part at the aforementioned accommodating corner part.

In the arrangement jig according to one aspect of the present invention, it is preferable that a plurality of the aforementioned receiving portions are arranged in a square lattice shape.

The arrangement method according to one aspect of the present invention is characterized by using the arrangement jig according to one aspect of the present invention described above to arrange a plurality of the aforementioned sheet-like bodies.

The transfer method according to one aspect of the present invention is characterized in that a plurality of the sheet-like bodies arranged by the one aspect of the arrangement method of the present invention are transferred to the adhesive surface of a rigid support having an adhesive surface.

According to one aspect of the present invention, it is possible to provide an arrangement jig and an arrangement method that can arrange a plurality of sheet-like bodies at more even intervals easily and quickly.

For example, according to the arrangement jig according to one aspect of the present invention, when the sheet-like bodies are brought into close contact with each other and arranged on the wall of the receiving part several times, the corners of the sheet-like bodies (sheet-like body corners) are not in contact with the receiving part. The corners (accommodating corners). That is, according to the arrangement jig, when the sheet-like body is brought into contact with the wall, it is possible to prevent the sheet-like body from being inclined. Moreover, according to this arrangement jig, it can be constructed with a simpler structure than the pick-and-place device, and can arrange a plurality of flakes quickly.

According to the transfer method according to one aspect of the present invention, a plurality of sheet-like bodies arranged by the aforementioned arrangement method according to one aspect of the present invention can be attached to the support.

100，300‧‧‧Arrangement fixture

110‧‧‧Main body

CP‧‧‧Semiconductor chip

101, 301‧‧‧Containment Department

102,302‧‧‧Wall

103,303‧‧‧Containment corner

104‧‧‧Depression

W1‧‧‧Circuit surface

W2‧‧‧Circuit

10‧‧‧First adhesive sheet

12‧‧‧First adhesive layer

20‧‧‧Second Adhesive Sheet

21‧‧‧Second substrate sheet

22‧‧‧Second adhesive layer

200‧‧‧Retaining member

201‧‧‧Keep the surface

40‧‧‧Surface protection sheet

41‧‧‧Fourth substrate film

42‧‧‧The fourth adhesive layer

60‧‧‧Closed component

62‧‧‧Second insulating layer

5A‧‧‧External electrode gasket

3，3A‧‧‧Closed body

W‧‧‧Semiconductor Wafer

30‧‧‧Protection sheet

31‧‧‧Third base film

32‧‧‧Third adhesive layer

400‧‧‧Frame member

401‧‧‧Opening

63‧‧‧Sealing resin

81‧‧‧Support substrate

82‧‧‧Peeling layer

83‧‧‧Insulating resin layer

84‧‧‧Rewiring

84A‧‧‧Internal electrode gasket

80A‧‧‧Layer 1

84B‧‧‧External electrode gasket

85‧‧‧Protruding electrode

86‧‧‧Closed resin film

W4‧‧‧Internal terminal electrode

80B‧‧‧Layer 2

500‧‧‧Hard substrate

500A‧‧‧Hard support

501‧‧‧Adhesive layer

502‧‧‧Adhesive surface

Fig. 1 is a plan view of the arrangement jig according to the first embodiment of the present invention.

Fig. 2A is a plan view illustrating an arrangement method using the arrangement jig according to the first embodiment.

Fig. 2B is a plan view illustrating an arrangement method using the arrangement jig according to the first embodiment.

Fig. 2C is a plan view illustrating the arrangement method using the arrangement jig according to the first embodiment.

Fig. 3A is a plan view illustrating the arrangement method using the arrangement jig of the reference example.

Fig. 3B is a plan view illustrating the arrangement method using the arrangement jig of the reference example.

Figure 3C illustrates the arrangement method of the arrangement jig using the reference example Floor plan.

4A is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first embodiment.

4B is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first embodiment.

4C is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first embodiment.

5A is a cross-sectional view for explaining the manufacturing method of the first embodiment following FIGS. 4A, 4B, and 4C.

Fig. 5B is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 4A, Fig. 4B, and Fig. 4C.

Fig. 6A is a cross-sectional view illustrating the manufacturing method of the first embodiment following Fig. 5A and Fig. 5B.

Fig. 6B is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 5A and Fig. 5B.

Fig. 7A is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 6A and Fig. 6B.

Fig. 7B is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 6A and Fig. 6B.

Fig. 8A is a cross-sectional view illustrating the manufacturing method of the first embodiment following Fig. 7A and Fig. 7B.

Fig. 8B is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 7A and Fig. 7B.

Fig. 8C is a description of the first embodiment following Fig. 7A and Fig. 7B Sectional view of manufacturing method.

Fig. 9A is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 8A, Fig. 8B and Fig. 8C.

Fig. 9B is a cross-sectional view illustrating the manufacturing method related to the first embodiment following Fig. 8A, Fig. 8B and Fig. 8C.

9C is a cross-sectional view for explaining the manufacturing method of the first embodiment following FIGS. 8A, 8B, and 8C.

Fig. 10A is a cross-sectional view illustrating the manufacturing method according to the second embodiment.

Fig. 10B is a cross-sectional view illustrating the manufacturing method according to the second embodiment.

Fig. 10C is a cross-sectional view illustrating the manufacturing method according to the second embodiment.

Fig. 10D is a cross-sectional view illustrating the manufacturing method according to the second embodiment.

11A is a cross-sectional view illustrating the manufacturing method of the second embodiment following FIGS. 10A, 10B, 10C, and 10D.

11B is a cross-sectional view for explaining the manufacturing method of the second embodiment following FIGS. 10A, 10B, 10C, and 10D.

11C is a cross-sectional view for explaining the manufacturing method of the second embodiment following FIGS. 10A, 10B, 10C, and 10D.

Fig. 12A is a cross-sectional view illustrating the manufacturing method of the second embodiment following Fig. 11A, Fig. 11B and Fig. 11C.

Fig. 12B is a cross-sectional view illustrating the manufacturing method of the second embodiment following Fig. 11A, Fig. 11B and Fig. 11C.

Fig. 13A is a cross-sectional view illustrating the manufacturing method according to the third embodiment.

Fig. 13B is a cross-sectional view illustrating the manufacturing method according to the third embodiment.

Fig. 14A is a cross-sectional view illustrating the manufacturing method according to the fourth embodiment.

Fig. 14B is a cross-sectional view illustrating the manufacturing method according to the fourth embodiment.

Fig. 14C is a cross-sectional view illustrating the manufacturing method according to the fourth embodiment.

Fig. 15A is a cross-sectional view illustrating the manufacturing method of the fifth embodiment.

Fig. 15B is a cross-sectional view illustrating the manufacturing method of the fifth embodiment.

Fig. 16A is a cross-sectional view illustrating the manufacturing method of the sixth embodiment.

Fig. 16B is a cross-sectional view illustrating the manufacturing method according to the sixth embodiment.

Fig. 16C is a cross-sectional view illustrating the manufacturing method of the sixth embodiment.

17A is a cross-sectional view for explaining the manufacturing method of the sixth embodiment following FIGS. 16A, 16B, and 16C.

Fig. 17B is a cross-sectional view for explaining the manufacturing method of the sixth embodiment following Fig. 16A, Fig. 16B and Fig. 16C.

18A is a cross-sectional view for explaining the manufacturing method of the sixth embodiment following FIGS. 17A and 17B.

Fig. 18B is a cross-sectional view illustrating the manufacturing method of the sixth embodiment following Fig. 17A and Fig. 17B.

18C is a cross-sectional view for explaining the manufacturing method of the sixth embodiment following FIGS. 17A and 17B.

Fig. 19A is a cross-sectional view illustrating the transfer method according to the seventh embodiment.

Fig. 19B is a cross-sectional view illustrating the transfer method according to the seventh embodiment.

(First Embodiment)

In this embodiment, an example in which an array jig is used in the manufacturing process of a semiconductor device is described. The purpose of the arrangement jig of the present invention is not added Limited to the manufacturing use of semiconductor devices.

In this embodiment, a form in which semiconductor wafers are arranged as a sheet-like body is exemplified. The sheet system that can be arranged by the arrangement jig of the present invention is not limited to a semiconductor chip.

. Arrangement fixture

FIG. 1 is a plan view of the arrangement jig 100 related to this embodiment. Moreover, a plan view showing a part of the enlarged arrangement jig 100 is also shown in FIG. 1.

The arrangement jig 100 is provided with a main body 110 of a frame, and a accommodating part 101 that can accommodate the semiconductor chip CP. The arrangement jig 100 is provided with a plurality of accommodating parts 101.

The arrangement jig 100 of the present embodiment is a plan view, and the receiving portion 101 with a substantially square opening is arranged as a lattice-shaped frame-shaped member. It is better if the plurality of receiving parts 101 are arranged in a square lattice shape.

The outer shape of the main body 110 of this embodiment is formed in a circular shape. The main body 110 has an outer frame 110A and an inner frame 110B formed inside the outer frame 110A. The outer frame 110A is a circular frame. The inner frame 110B is a lattice-shaped frame combined inside the circular outer frame 110A. From the standpoint of increasing the rigidity of the arrangement jig and making it easier to handle the arrangement jig, in the plan view of the arrangement jig 100, the width of the circular outer frame 110A is larger than that of the grid-like inner frame of the plurality of compartments 101 in each division The width of 110B is better if the width is larger. As described later, the outer shape of the main body of the arrangement jig is not limited to a circular shape, and shapes other than the circular shape may be used.

The accommodating parts 101 each have a wall part 102 and a accommodating corner part 103. In this embodiment, the accommodating portion 101 is formed in a substantially square shape in plan view via the wall portion 102 and the accommodating corner portion 103. The opening size of the accommodating portion 101 is formed to a size capable of accommodating a semiconductor chip, and is not particularly limited. Plural accommodating parts 101 are formed at equal intervals.

The accommodating part 101 of this embodiment penetrates the upper and lower sides of the main body 110. That is, the accommodating portion 101 has an opening on the upper surface side and an opening on the lower surface side. Therefore, when the semiconductor chip CP is accommodated in the accommodating part 101, the arrangement jig 100 is placed on the holding surface of the holding member, and the mounting plate-shaped member is equal to one of the upper and lower sides of the main body 110, and the accommodating part 101 is closed. The one who speaks on one side is better. The semiconductor wafer CP is supported by a member closing the opening on one side of the accommodating portion 101 via a member closing the opening.

The main body 110 is composed of an outer frame 110A and an inner frame 110B, and the accommodating portion 101 penetrates the upper and lower sides of the main body 110, which can reduce the weight of the arrangement jig 100 according to this embodiment.

The depth of the accommodating part 101 is not particularly limited. When the semiconductor chip CP is accommodated in the accommodating portion 101, the surface of the semiconductor chip CP can also be positioned above or below the surface of the main body portion 110, and the surface of the main body portion 110 and the surface of the semiconductor chip CP It can be located on the same side. The depth of the receiving portion 101 is equivalent to the height of the wall portion 102.

In the receiving portion 101, the wall portion 102 is composed of a first side wall 102a, a second side wall 102b, a third side wall 102c, and a fourth side wall 102d.

In the receiving portion 101, the first side wall 102a is adjacent to the second side wall 102b, and the second side wall 102b is adjacent to the third side wall 102c, and the third side wall 102a is adjacent to the third side wall 102c. 102c is adjacent to the fourth side wall 102d, and the fourth side wall 102d is adjacent to the first side wall 102a.

In the accommodating part 101, the accommodating corner 103 is located at the end of the wall 102.

In the accommodating portion 101, the accommodating corner 103 is composed of a first accommodating corner 103a, a second accommodating corner 103b, a third accommodating corner 103c, and a fourth accommodating corner 103d.

In the receiving portion 101, the first receiving corner 103a is located at the end of the first side wall 102a and the end of the second side wall 102b, and the second receiving corner 103b is located at the end of the second side wall 102b and the end of the second side wall 102b. The end of the three side walls 102c, the third receiving corner 103c is located at the end of the third side wall 102c and the end of the fourth side wall 102d, and the fourth receiving corner 103d is located at the end of the fourth side wall 102d and the end of the fourth side wall 102d. The end of a side wall 102a.

The four housing corners 103 are each formed in the following shape. When the semiconductor wafer CP is accommodated in the accommodating portion 101 and the semiconductor wafer CP is brought into contact with the wall portion 102, the corners of the semiconductor wafer CP are formed so as not to contact the accommodating corner 103. The corners of the semiconductor chip CP are sometimes called chip corners or chip corners.

In the arrangement jig 100 of this embodiment, for example, the corner portion of the semiconductor chip CP and the receiving corner portion 103 are not in contact with each other, and the four receiving corner portions 103 have a recessed in the relatively wall portion 102. The wall surface is in the form of a recess 104 on the deep side. However, the present invention is not limited to the form having such a recess 104.

The recess 104 of this embodiment is recessed into a semicircular shape, However, if the corner portion of the semiconductor chip CP and the receiving corner portion 103 are in a non-contact shape, there is no particular limitation. As the shape of the recess 104, for example, an elliptical shape or a polygonal shape may also be used. In addition, the recessed portion 104 is not limited to a form formed at four corners as described in this embodiment. For example, the recessed portion 104 may be formed in at least one accommodating corner 103. For example, in the case of an arrangement jig in which one recess 104 is formed, the recess 104 is formed at the same corner of each receiving portion 101 (for example, the first receiving corner 103a), and the recess 104 is preferably formed .

The arrangement jig 100 is preferably formed of a heat-resistant material. The sealing member described later is in the case of thermosetting resin. For example, the curing temperature of thermosetting resin is about 120°C to 180°C. Therefore, it is preferable that the alignment jig 100 has heat resistance that does not cause deformation of the alignment jig even at the curing temperature of the thermosetting resin. Examples of the material system of the alignment jig 100 include metal and heat-resistant resin. Examples of the metal series include copper, 42 alloy, and stainless steel. Examples of heat-resistant resin systems include polyimide resins, glass polyester resins, and the like.

The manufacturing method of the arrangement jig 100 is not particularly limited. For example, the arrangement jig 100 can be manufactured by stamping a plate-shaped member. In addition, the arrangement jig 100 series may also be manufactured by performing etching processing on a plate-shaped member. For the dimensional accuracy required for the receiving portion 101 or the recessed portion 104, it is better to select a suitable processing method.

. Arrangement method

For Fig. 2A, Fig. 2B, and Fig. 2C (there are summarized and referred to as Fig. 2 Situation) is a plan view showing a method for arranging the semiconductor wafer CP as a sheet-like body by using the arrangement jig 100 according to this embodiment.

FIG. 2A is a plan view showing the arrangement jig 100 placed on the holding surface of the holding member and explaining the state in which each semiconductor chip CP is accommodated in the accommodating portion 101. When the arrangement jig 100 is placed on the holding surface of the holding member, the opening on the lower surface side of the accommodating portion 101 is closed.

The semiconductor wafer CP is viewed as a rectangle in a plane. The semiconductor wafer CP has a first side surface cp1 and a second side surface cp2 adjacent to the first side surface cp1.

In FIG. 2A, the plural semiconductor chips CP are not arranged.

2B is a plan view showing a state where the moving arrangement jig 100 is shown in the arrow direction 2B in the figure, and the wall portion 102 of the accommodating portion 101 is abutted against the side surface of the semiconductor chip CP.

When the alignment jig 100 moves in the arrow direction 2B, the first side cp1 of each semiconductor chip CP accommodated in the accommodating portion 101 and the first side wall 102a of the alignment jig 100 abut. As a result, the plural semiconductor wafers CP are arranged at equal intervals in the arrangement in the arrow direction 2B.

2C is a plan view showing a state where the moving arrangement jig 100 is shown in the arrow direction 2C in the figure, and the wall portion 102 of the receiving portion 101 is abutted against the side surface of the semiconductor chip CP.

The arrow direction 2C is preferably orthogonal to the arrow direction 2B. When the arrangement jig 100 is moved in the arrow direction 2C, the first side cp1 of the semiconductor chip CP and the first side wall 102a of the arrangement jig 100 are kept in contact with each other for movement. good.

When the alignment jig 100 moves in the arrow direction 2C, the second side surface cp2 of each semiconductor chip CP accommodated in the accommodating portion 101 and the second side wall 102b of the alignment jig 100 abut against each other. When the second side surface cp2 is in contact with the second side wall 102b, the chip corner cp3 of the semiconductor chip CP is not in contact with the first receiving corner 103a, but is accommodated in the recess 104.

Since the corner portion cp3 of the semiconductor chip CP is not in contact with the first receiving corner portion 103a, the first side surface cp1 of the semiconductor chip CP remains along the first side wall 102a, and the second side surface cp2 abuts on the second side wall 102b. That is, without tilting the semiconductor wafer CP, the mutually adjacent side surfaces of the semiconductor wafer CP can be abutted against the mutually adjacent wall portions of the accommodating portion 101.

As a result, the plural semiconductor wafers CP are arranged at equal intervals in the arrangement of the arrow direction 2B and the arrow direction 2C.

3A, FIG. 3B, and FIG. 3C (there are cases where they are collectively referred to as FIG. 3) are shown to illustrate the use of the arrangement jig 300 of the reference example, and the arrangement of the semiconductor chips CP as a sheet The floor plan of the method.

The arrangement jig 300 is the same as the arrangement jig 100 related to this embodiment, and has a plurality of accommodating parts 301, and has a wall part 302 and an accommodating corner part 303. The wall portion 302 has a first side wall 302a and a second side wall 302b adjacent to the first side wall 302a. However, the shape of the accommodating corner 303 is different from the accommodating corner 103 of the arrangement jig 100 related to this embodiment. The accommodating corner 303 does not have the recess 104, and the wall surface that is curved and protrudes from the wall 102 is inside.

FIG. 3A is a plan view similar to FIG. 2A showing the arrangement jig 300 placed on the holding surface of the holding member and explaining the state in which each semiconductor chip CP is accommodated in the accommodating portion 301. When the alignment jig 300 is placed on the holding surface of the holding member, the opening on the lower surface side of the accommodating portion 301 is closed.

With respect to FIG. 3B, a plan view showing a state where the moving arrangement jig 300 is shown in the arrow direction 3B in the figure, and the wall portion 302 of the receiving portion 301 is abutted against the side surface of the semiconductor chip CP.

When the arrangement jig 300 moves in the arrow direction 3B, the first side surface cp1 of each semiconductor chip CP contained in the accommodating portion 301 and the first side wall 302a of the arrangement jig 300 are in contact with each other. As a result, the plural semiconductor wafers CP are arranged at equal intervals in the arrangement of the arrow direction 3B.

3C is a plan view showing the direction of the arrow 3C of the moving arrangement jig 300 in the figure, as a plan view showing the arrangement state when the wall portion 302 of the housing portion 301 is abutted against the side surface of the semiconductor chip CP.

When the alignment jig 300 moves in the arrow direction 3C, before the second side cp2 of each semiconductor chip CP accommodated in the accommodating portion 301 and the second side wall 302b of the alignment jig 300 come into contact with each other, the chip corner of the semiconductor chip CP cp3 is in contact with the protruding part of the receiving corner 303, and the semiconductor chip CP is inclined.

As described above, according to the arrangement jig 100 and the arrangement method of this embodiment, the semiconductor wafer CP can be arranged evenly without tilting.

. Manufacturing method of semiconductor device

Next, regarding the manufacturing method of the semiconductor device of this embodiment Explain. In this embodiment, in the process of the manufacturing method of the semiconductor device, the process of arranging the aforementioned semiconductor wafers (semiconductor wafer arranging process) is performed.

For FIG. 4A, the semiconductor wafer W attached to the first adhesive sheet 10 is shown. The semiconductor wafer W has a circuit surface W1, and the circuit surface W1 has a circuit W2 formed thereon. The first adhesive sheet 10 is attached to the back surface W3 on the side opposite to the circuit surface W1 of the semiconductor wafer W.

The semiconductor wafer W is, for example, a silicon wafer or gallium. Compound semiconductor wafers such as arsenic. As a method of forming the circuit W2 on the circuit surface W1 of the semiconductor wafer W, a commonly used method may be mentioned, for example, an etching method, a lift-off method, etc. may be mentioned.

The semiconductor wafer W is ground to a predetermined thickness so that the back surface W3 is exposed, and is attached to the first adhesive sheet 10. The method of grinding the semiconductor wafer W is not particularly limited, and, for example, a known method such as a grinder can be cited. When grinding the semiconductor wafer W, in order to protect the circuit W2, a surface protection sheet is attached to the circuit surface W1. The back surface grinding of the wafer is to fix the circuit surface W1 side of the semiconductor wafer W via a chuck or the like, that is, the surface protection sheet side, and to grind the back surface side on which no circuit is formed by a grinder. The thickness of the semiconductor wafer W after grinding is not particularly limited, but is usually 20 μm or more and 500 μm or less.

The first adhesive sheet 10 has a first base film 11 and a first adhesive layer 12. The first adhesive layer 12 is laminated on the first base film 11.

The first adhesive sheet 10 may be attached to the semiconductor wafer W and the first ring frame. In this case, the first adhesive layer 12 of the first adhesive sheet 10 On the upper side, the first ring frame and the semiconductor wafer W are placed, and the first ring frame and the semiconductor wafer W are gently pressed to fix the first ring frame and the semiconductor wafer W to the first adhesive sheet 10.

The material of the first base film 11 is not limited. Examples of the material system of the first base film 11 include polyvinyl chloride resin, polyester resin (polyethylene terephthalate, etc.), acrylic resin, polycarbonate resin, polyethylene resin, and polypropylene resin. , Acrylonitrile. Butadiene. Styrene resin, polyimide resin, polyurethane resin, and polystyrene resin, etc.

The adhesive contained in the first adhesive layer 12 is not particularly limited, and various types of adhesives can be applied to the first adhesive layer 12. Examples of the adhesive contained in the first adhesive layer 12 include rubber-based, acrylic-based, silicone-based, polyester-based, and urethane-based adhesives. However, the type of adhesive is selected in consideration of the use or the type of the object to be attached.

When an energy-ray polymerizable compound is blended into the first adhesive layer 12, the first adhesive layer 12 is irradiated with energy rays from the side of the first base film 11 to harden the energy-ray polymerizable compound. When the energy ray polymerizable compound is hardened, the cohesive force of the first adhesive layer 12 is increased, and the adhesive force between the first adhesive layer 12 and the semiconductor wafer W can be reduced or disappeared. Examples of the energy line system include ultraviolet (UV) and electron beams (EB), and ultraviolet rays are preferred.

The method of reducing or disappearing the adhesive force between the first adhesive layer 12 and the semiconductor wafer W is not limited to energy ray irradiation. As a method of reducing or disappearing this adhesive force, for example, a method of heating can be cited. The method by heating and energy ray irradiation, and the method by cooling.

As a method of cooling, there is a method of changing the crystal structure of the polymer used in the first adhesive layer 12 when cooling the first adhesive sheet 10, and then changing the adhesive force.

[Cutting Engineering]

For FIG. 4B, a plurality of semiconductor chips CP held on the first adhesive sheet 10 are shown.

The semiconductor wafer W held on the first adhesive sheet 10 is sliced by dicing to form a plurality of semiconductor chips CP. For the cutting system, use cutting means such as a cutting machine. The cutting depth during dicing is set to the total thickness of the semiconductor wafer W and the thickness of the first adhesive layer 12, and the depth of the wear component added to the dicing machine. Through the dicing, the first adhesive layer 12 is also cut to the same size as the semiconductor chip CP. Furthermore, the first base film 11 is also cut through cutting.

In addition, the method of dicing the semiconductor wafer W is not limited to the method using a dicing machine. For example, the semiconductor wafer W may be diced by a laser irradiation method.

The irradiation of the energy rays to the first adhesive layer 12 may be performed at any stage from after the semiconductor wafer W is attached to the first adhesive sheet 10 to before the first adhesive sheet 10 is peeled off. The energy ray irradiation system may be performed after cutting, for example, or may be performed after the expansion process described later. It is also possible to irradiate energy rays multiple times.

[First expansion project]

4C is a diagram illustrating the process of stretching and holding the first adhesive sheet 10 of the plural semiconductor chips CP (there is a case called the first expansion process).

After dicing and dicing into a plurality of semiconductor chips CP, the first adhesive sheet 10 is stretched to expand the space between the plurality of semiconductor chips CP. The method of stretching the first adhesive sheet 10 in the first expansion process is not particularly limited. As a method of stretching the first adhesive sheet 10, for example, a method of stretching the first adhesive sheet 10 by pressing an annular expander or a circular expander on the first adhesive sheet 10, and The method of grasping the outer periphery of the first adhesive sheet 10 and stretching the first adhesive sheet 10 by using a holding member or the like.

In this embodiment, as shown in FIG. 4C, the distance between the semiconductor wafers CP after the first expansion step is referred to as D1. As the distance D1 system, for example, it may be 15 μm or more and 110 μm or less.

[First Transfer Project]

5A is a diagram illustrating the process of transferring a plurality of semiconductor chips CP to the second adhesive sheet 20 after the first expansion process (there is a case called the first transfer process). After the first adhesive sheet 10 is stretched to enlarge the distance between the plurality of semiconductor chips CP to the distance D1, the second adhesive sheet 20 is pasted on the circuit surface W1 of the semiconductor chip CP.

The second adhesive sheet 20 has a second substrate film 21 and a second adhesive 剂层22。 Agent layer 22. The second adhesive sheet 20 is preferably attached so as to cover the circuit surface W1 with the second adhesive layer 22.

The material of the second base film 21 is not particularly limited. As the material of the second base film 21, for example, the same material as the material exemplified for the first base film 11 can be cited.

The second adhesive layer 22 is laminated on the second base film 21. The adhesive contained in the second adhesive layer 22 is not particularly limited, and various types of adhesives can be applied to the second adhesive layer 22. As the adhesive contained in the second adhesive layer 22, for example, the same adhesive as the adhesive described for the first adhesive layer 12 can be cited. However, the type of adhesive is selected in consideration of the use or the type of the object to be attached. For the second adhesive layer 22, an energy ray polymerizable compound is also formulated.

The second adhesive sheet 20 has a better tensile elastic modulus than the first adhesive sheet 10. The tensile elastic modulus of the second adhesive sheet 20 is preferably greater than or equal to 10 MPa and less than or equal to 2000 MPa. It is also ideal that the breaking elongation of the second adhesive sheet 20 is 50% or more. However, the tensile modulus and elongation at break in this specification are measured using a tensile testing device in accordance with JIS K7161 and JIS K7127.

The adhesive force of the second adhesive layer 22 is better than the adhesive force of the first adhesive layer 12. For example, when the adhesive force of the second adhesive layer 22 is large, it becomes easy to peel off the first adhesive sheet 10 after the plural semiconductor chips CP are transferred to the second adhesive sheet 20.

It is preferable that the second adhesive sheet 20 has heat resistance. When the sealing member described later is a thermosetting resin, for example, the curing temperature of the thermosetting resin The temperature ranges from 120°C to 180°C, and the heating time ranges from 30 minutes to 2 hours. The second adhesive sheet 20 preferably has heat resistance such as no wrinkles when the sealing member is thermally cured. In addition, the second adhesive sheet 20 is preferably made of a material that can be peeled from the semiconductor chip CP after the thermal hardening treatment.

The second adhesive sheet 20 may be attached to the second ring frame. In this case, a second ring frame is placed above the second adhesive layer 22 of the second adhesive sheet 20, and then the second ring frame is lightly pressed to fix the second ring frame to the second adhesive sheet 20 . After that, the second adhesive layer 22 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor chip CP, and a plurality of semiconductor chips CP are fixed on the second adhesive sheet 20.

When attaching the second adhesive sheet 20 to the circuit surface W1, it is preferable that the MD direction of the first base film 11 is orthogonal to the MD direction of the second base film 21. With such pasting, the direction in which the substrate film is easily stretched is orthogonal to the second expansion process of stretching the second adhesive sheet 20 described later. Therefore, by implementing the second expansion process, the interval between the plurality of semiconductor chips CP is expanded more uniformly. In this specification, the "MD direction" is used as a vocabulary indicating the length direction parallel to the original structure of the substrate film (the conveying direction during the manufacture of the original structure). In this manual, MD is the abbreviation for Machine Direction.

For example, for the amount of extension along the direction that is easy to stretch in the first expansion project (sometimes referred to as the first direction), and along the direction orthogonal to the first direction (which is less stretchable than the first direction) Direction, there is a case called the second direction) and the extension of the extension is different, by the first If the direction in which the substrate film 21 is easy to extend, if it matches the second direction, the extension in the second direction can be made larger than the first direction in the second expansion process, and the plurality of semiconductor chips CP can be adjusted uniformly The interval between. For example, in the case of a plurality of semiconductor chips CP that are sliced along a grid-shaped dividing line, according to this aspect, the space between the plurality of semiconductor chips CP is more uniformly expanded in the up-down direction and the left-right direction .

After the second adhesive sheet 20 is attached to the plurality of semiconductor chips CP, when the first adhesive sheet 10 is peeled off, the back surface W3 of the plurality of semiconductor chips CP is exposed. After peeling off the first adhesive sheet 10, it is preferable to maintain the distance D1 between the plurality of semiconductor chips CP expanded in the first expansion process. In the case where an energy-ray polymerizable compound is formulated for the first adhesive layer 12, for the first adhesive layer 12, energy rays are irradiated from the side of the first base film 11 to harden the energy-ray polymerizable compound, and then the first adhesive layer is peeled off 10 thin slices are preferred.

[Second Expansion Project]

5B is a diagram showing a process of stretching and holding the second adhesive sheet 20 of a plurality of semiconductor chips CP (there is a case called a second expansion process).

In the second expansion process, the interval between the plural semiconductor chips CP is further expanded. The method of stretching the second adhesive sheet 20 in the second expansion process is not particularly limited. As a method of stretching the second adhesive sheet 20, for example, a method of stretching the second adhesive sheet 20 by pressing an annular expander or a circular expander on the second adhesive sheet 20, and Use control The member or the like grasps the method of stretching the second adhesive sheet 20 at the outer periphery of the second adhesive sheet 20, and the like.

In this embodiment, as shown in FIG. 5B, the interval between the semiconductor wafers CP after the second expansion step is referred to as D2. The distance D2 is greater than the distance D1. As the distance D2 system, for example, it is preferably 200 μm or more and 5000 μm or less.

[Second Transfer Project]

6A is a diagram showing the process of transferring a plurality of semiconductor wafers CP to the holding surface of the holding member after the second expansion process (sometimes referred to as the second transfer process).

6A shows a plurality of semiconductor wafers CP transferred to the holding member 200. As shown in FIG. The holding member 200 has a holding surface 201 capable of sucking and holding the semiconductor wafer CP. The semiconductor wafer CP is sucked and held on the holding surface 201 by a pressure reducing means (not shown). It is preferable that the holding surface 201 is a flat surface, and it is preferable that the holding surface 201 has a plurality of suction holes so as to adsorb and hold the semiconductor wafer CP. As the decompression means, for example, a decompression pump, a vacuum exhauster, and the like can be cited. In the second transfer process, the back surface W3 of the plurality of semiconductor wafers CP held by the second adhesive sheet 20 is arranged toward the holding surface 201. The plurality of semiconductor wafers CP placed on the holding surface 201 are bonded to the holding surface 201 on the back surface W3 of the semiconductor wafer CP. Driven by the pressure reducing means, the plural semiconductor wafers CP are sucked and held on the holding surface 201. After the plurality of semiconductor wafers CP are adsorbed and held on the holding surface 201, it is preferable to peel off the second adhesive sheet 20.

[Fixture Placement Project]

6B is a diagram showing the process of placing the array jig 100 on the holding surface 201 of the holding member 200 (there is a case called jig placing process).

The semiconductor wafer CP held on the holding surface 201 is accommodated in the accommodating portion 101, and the alignment jig 100 is placed on the holding surface 201. When the arrangement jig 100 is placed on the holding surface 201 of the holding member 200, it is in a state of closing the opening on the lower surface side of the accommodating portion 101.

In the jig placement process, it is preferable to adsorb and hold the plurality of semiconductor wafers CP on the holding surface 201.

In the case of arranging the diced semiconductor wafers CP in a grid pattern, from the viewpoint of easily accommodating the semiconductor chips CP in the housing portion 101, it is preferable to use the arrangement jig 100 in which the arrangement and housing portion 101 is grid-like.

[Semiconductor wafer arrangement project]

After the jig placement process, the semiconductor chip arrangement process of arranging the plurality of semiconductor chips CP using the arrangement jig 100 is implemented. The semiconductor chip arrangement process can be implemented in the same way as the aforementioned semiconductor chip arrangement method.

In this embodiment, a method of moving the alignment jig 100 so that the wall portion 102 of the accommodating portion 101 abuts against the side surface of the semiconductor chip CP will be described as an example.

First, use the holding means to hold the main body 110 of the arrangement jig 100 的外架110A. The holding means is connected with a driving device not shown in the figure. The arrangement jig 100 is moved by this driving device, and the wall 102 of the arrangement jig 100 is abutted on the side surface of the semiconductor chip CP. The sequence and direction of moving the arrangement jig 100 are not limited to the sequence and direction of the arrow direction 2B in FIG. 2B and the arrow direction 2C in FIG. 2C. The driving device is preferably configured such that the arrangement jig 100 can be moved in any direction along the holding surface 201. When the arrangement jig 100 is moved, it is preferable that the arrangement jig 100 is separated from the holding surface 201 and moved along the holding surface 201. In addition, the alignment jig 100 may be moved while keeping contact with the holding surface 201.

The semiconductor wafer arranging process is performed based on releasing the suction and holding by the pressure reducing means of the holding member 200, and when the suction and holding force is reduced, the semiconductor wafer CP can be easily moved. However, the driving device may have detection means not shown in the figure. The position of the semiconductor wafer CP placed on the holding surface 201 may be detected by the detecting means. The driving device may have a control means for controlling the movement amount or the movement direction of the semiconductor chip CP according to the detection result of the detection means. In the driving device, the gripping means, the detecting means, and the control means may be linked together.

The method of arranging the plural semiconductor wafers CP is not limited to the above-mentioned method. For example, instead of moving the alignment jig 100, in order to move the holding member 200, a method of bringing the alignment jig 100 and the semiconductor chip CP into close contact may also be used. In the case of this method, it is preferable to release the adsorption holding by the pressure reducing means of the holding member 200 and to reduce the adsorption holding force.

In addition, as a method of arranging the plural semiconductor chips CP, both the arrangement jig 100 and the holding member 200 are moved to make the arrangement jig The method of 100 and the semiconductor chip CP is also available. In the case of this method, it is preferable to release the adsorption holding by the pressure reducing means of the holding member 200 and to reduce the adsorption holding force.

[Third Transfer Project]

7A is a diagram showing a process of transferring the semiconductor wafers CP arranged in the semiconductor wafer aligning process to the surface protection sheet 40 as the fourth adhesive sheet (it may be referred to as the third transfer process).

A surface protection sheet 40 is pasted on the circuit surface W1 of the arranged plural semiconductor chips CP. In this embodiment, the semiconductor wafer CP is attached to the surface protection sheet 40, but the arrangement jig 100 is not attached to the surface protection sheet 40.

The surface protection sheet 40 has a fourth base film 41 and a fourth adhesive layer 42. The surface protection sheet 40 is preferably attached so as to cover the circuit surface W1 with the fourth adhesive layer 42.

The material of the surface protection sheet 40 is not particularly limited. As the material of the fourth base film 41, for example, the same material as the material exemplified for the first base film 11 can be cited.

The fourth adhesive layer 42 is laminated on the fourth base film 41. The adhesive contained in the fourth adhesive layer 42 is not particularly limited, and various types of adhesives can be applied to the fourth adhesive layer 42. As the adhesive contained in the fourth adhesive layer 42, for example, the same adhesive as the adhesive described for the first adhesive layer 12 can be mentioned. However, the type of adhesive is selected in consideration of the use or the type of the object to be attached. For the fourth The adhesive layer 42 is also formulated with an energy ray polymerizable compound.

The surface protection sheet 40 is preferably one having heat resistance. When the sealing member described later is a thermosetting resin, for example, the curing temperature of the thermosetting resin is about 120°C to 180°C, and the heating time is about 30 minutes to 2 hours. The surface protection sheet 40 preferably has heat resistance such as no wrinkles when the sealing member is thermally cured. In addition, the surface protection sheet 40 is preferably made of a material that can be peeled from the semiconductor wafer CP after the thermal hardening treatment.

[Closed Project]

7B is a diagram showing a process of sealing a plurality of semiconductor chips CP held by the surface protection sheet 40 (a case known as a sealing process).

When a plurality of semiconductor chips CP are covered via the sealing member 60 via the remaining circuit surface W1, the enclosed body 3 is formed. A sealing member 60 is also filled between the plurality of semiconductor chips CP. In this embodiment, since the circuit surface W1 and the circuit W2 are covered by the surface protection sheet 40, it is possible to prevent the circuit surface W1 from being covered by the sealing member 60.

Through the sealing process, a sealing body 3 can be obtained in which a plurality of semiconductor chips CP, which are separated by each specific distance, are embedded in the sealing member. In the sealing process, the plurality of semiconductor chips CP are maintained at a distance D2, and it is preferable that they are covered by the sealing member 60.

There is no method for covering a plurality of semiconductor chips CP with the sealing member 60 Specially limited. For example, a method of holding a plurality of semiconductor chips CP covered with the surface protection sheet 40 and covering the circuit surface W1 in a metal mold and injecting a fluid resin material into the metal mold may be adopted to harden the resin material. In addition, it is also possible to use a method in which a sheet-like sealing resin is placed to cover the back surface W3 of a plurality of semiconductor chips CP, and the sealing resin is heated to bury the plurality of semiconductor chips CP in the sealing resin. As a material of the sealing member 60, epoxy resin etc. are mentioned, for example. Regarding the epoxy resin used as the sealing member 60, for example, phenol resin, synthetic rubber, inorganic filler, hardening accelerator, and the like may also be contained.

After the sealing process, when the surface protection sheet 40 is peeled off, the surface 3S contacting the circuit surface W1 of the semiconductor chip CP and the surface protection sheet 40 of the enclosure 3 is exposed.

[Manufacturing Engineering of Semiconductor Packaging]

8A, 8B, and 8C (the case where these are aggregated and referred to as FIG. 8), and Figures 9A, 9B, and 9C (the case where these are aggregated and referred to as FIG. 9) are displayed and explained A diagram of the process of manufacturing a semiconductor package using plural semiconductor chips CP. This embodiment is preferable to include the manufacturing process of such a semiconductor package.

[Rewiring layer formation project]

8A is a cross-sectional view showing the enclosure 3 after the surface protection sheet 40 is peeled off. In this embodiment, it further includes: after peeling off the surface protection sheet 40, the enclosure 3 is formed to form a rewiring layer forming a rewiring layer Engineers are better. In the redistribution layer forming process, redistributions connected to the circuits W2 of the plurality of exposed semiconductor chips CP are formed on the circuit surface W1 and the surface 3S of the enclosure 3. For the formation of rewiring, first, an insulating layer is formed on the enclosure 3.

8B is a cross-sectional view showing the process of forming the first insulating layer 61 on the circuit surface W1 of the semiconductor chip CP and the surface 3S of the enclosure 3. The first insulating layer 61 containing an insulating resin is formed on the circuit surface W1 and the surface 3S so as to expose the circuit W2 or the internal terminal electrode W4 of the circuit W2. Examples of insulating resins include polyimide resins, polybenzoxazole resins, and silicone resins. The material of the internal terminal electrode W4 is not limited as long as it is a conductive material. For example, metals such as gold, silver, copper, and aluminum, and alloys can be mentioned.

8C is a cross-sectional view showing the process of forming the rewiring 5 electrically connected to the semiconductor chip CP enclosed by the enclosed body 3. In this embodiment, the rewiring 5 is formed following the formation of the first insulating layer 61. The material of the rewiring 5 is not limited as long as it is a conductive material. For example, metals such as gold, silver, copper, and aluminum, alloys, etc. can be mentioned. The rewiring 5 system can be formed by a well-known method.

9A is a cross-sectional view showing the process of forming the second insulating layer 62 covering the redistribution 5. The rewiring 5 has an external electrode pad 5A for external terminal electrodes. An opening or the like is provided to the second insulating layer 62 to expose the external electrode pad 5A for the external terminal electrode. In this embodiment, the external electrode pad 5A is within and outside the range (corresponding to the circuit surface W1) of the semiconductor chip CP of the enclosure 3 (corresponding to the enclosure member 60). The range of the upper surface 3S) is exposed. In addition, the rewiring 5 is formed on the surface 3S of the enclosure 3 in an array with the external electrode pads 5A arranged. In this embodiment, the enclosure 3 has a structure in which the external electrode pad 5A is exposed outside the range of the semiconductor chip CP, so that a fan-out type WLP can be obtained.

[Connection with external terminal electrode]

9B is a cross-sectional view showing the process of connecting the external terminal electrode to the external electrode pad 5A of the enclosure 3. The external terminal electrode 7 such as a solder ball is placed on the external electrode pad 5A exposed from the second insulating layer 62, and the external terminal electrode 7 and the external electrode pad 5A are electrically connected through solder bonding or the like. The material of the solder balls is not particularly limited. For example, lead-containing solder, lead-free solder, and the like can be cited.

[Second Cutting Project]

For FIG. 9C, a cross-sectional view illustrating the process (a case known as the second cutting process) of the enclosure 3 to which the external terminal electrode 7 is connected to the individual pieces is shown. In this second dicing process, the enclosure 3 is divided into pieces in units of semiconductor wafers CP. There is no particular limitation on the method of forming the closed body 3 into individual pieces. For example, the same method as the method of cutting the aforementioned semiconductor wafer W can be used, and the enclosed body 3 can be made into individual pieces. The process of making the closure body 3 into individual pieces may be implemented by attaching the closure body 3 to an adhesive sheet such as a cutting sheet.

The semiconductor chip CP is manufactured by using the enclosed body 3 as individual pieces Unit of semiconductor package 1. As described above, the semiconductor package 1 connecting the external terminal electrode 7 to the external electrode pad 5A outside the range of the semiconductor chip CP is manufactured as a fan-out wafer level package (FO-WLP).

[Installation work]

In this embodiment, it is also preferable to include the process of mounting and individualizing the semiconductor package 1 on a printed wiring board.

. Effect of implementation form

According to the arrangement jig 100 and the arrangement method of the present embodiment, a plurality of semiconductor chips CP can be arranged easily and quickly at more even intervals.

According to the arrangement jig 100 and the arrangement method of the present embodiment, the chip corner cp3 of the semiconductor chip CP is not easily contacted with the receiving corner 103 of the arrangement jig 100. Therefore, it is possible to prevent damage to the apex part such as the corner part of the semiconductor wafer CP. For the case where the thickness of the semiconductor wafer CP is thin, or the case where the semiconductor wafer CP is brittle, the arrangement jig 100 and the arrangement method of this embodiment are more suitable from the viewpoint of preventing damage to the semiconductor wafer CP.

For example, according to the semiconductor device manufacturing method of the present embodiment, in the semiconductor chip arrangement process, the arrangement method using the arrangement jig 100 is implemented. After arranging a plurality of semiconductor chips CP at equal intervals, the sealing process can be implemented Or semiconductor packaging engineering. Therefore, in the closed body In 3, a plurality of semiconductor chips CP are closed at more even intervals. Furthermore, since the plurality of semiconductor chips CP are closed at equal intervals, the positional deviation of the connection position of the circuit W2 of the plurality of semiconductor chips CP and the redistribution 5 can be suppressed in the rewiring layer forming process.

The manufacturing method of the semiconductor device of this embodiment is superior in suitability for the process of manufacturing the semiconductor package 1 of the FO-WLP format. Specifically, according to this embodiment, it is possible to improve the uniformity and accuracy of the chip spacing in the FO-WLP type semiconductor package 1.

(Second Embodiment)

Next, the second embodiment of the present invention will be described. However, in the following description, the description of the same parts as those already described will be omitted.

The manufacturing method of the semiconductor device related to this embodiment is mainly related to the first embodiment from the process of using semiconductor wafers W to separate them into semiconductor chips CP to the process of expanding the distance between the plural semiconductor chips CP. The manufacturing method of the semiconductor device is different. The other points are that the second embodiment is the same as the first embodiment, and the description is omitted or simplified. However, the arrangement jig or arrangement method described in the first embodiment is also applied to this embodiment.

. Manufacturing method of semiconductor device

Hereinafter, the manufacturing method of the semiconductor device of this embodiment will be described.

[Gully Formation Project]

10A is a diagram illustrating a process of forming a trench of a certain depth from the side of the circuit surface W1 of the semiconductor wafer W (it is called a trench forming process).

The semiconductor wafer W has a circuit surface W1 as the first surface. A circuit W2 is formed on the circuit surface W1.

In the trench formation process, a dicing sheet of a dicing device or the like is used from the side of the circuit surface W1 to cut the semiconductor wafer. At this time, from the circuit surface W1 of the semiconductor wafer W, an incision having a shallower depth than the thickness of the semiconductor wafer W is cut to form a groove W5. The trench W5 is formed by dividing a plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W. The depth of the groove W5 is slightly deeper than the thickness of the target semiconductor wafer, and is not particularly limited.

For FIG. 10B, it is shown that after the formation of the groove W5, the semiconductor wafer W, which is the protective sheet 30 as the third adhesive sheet, is pasted on the circuit surface W1.

In this embodiment, in the subsequent grinding process, the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W before the semiconductor wafer W is ground. The protective sheet 30 protects the circuit surface W1 and the circuit W2.

The protective sheet 30 has a third base film 31 and a third adhesive layer 32. The third adhesive layer 32 is laminated on the third base film 31.

The material of the third base film 31 is not particularly limited. As the material system of the third base film 31, for example, polyvinyl chloride resin, polyester resin (polyethylene terephthalate, etc.), acrylic resin, polycarbonate resin Grease, polyethylene resin, polypropylene resin, acrylonitrile. Butadiene. Styrene resin, polyimide resin, polyurethane resin, and polystyrene resin, etc.

The adhesive contained in the third adhesive layer 32 is not particularly limited, and various types of adhesives can be applied to the third adhesive layer 32. As the adhesive contained in the third adhesive layer 32, for example, rubber-based adhesives, acrylic-based adhesives, silicone-based adhesives, polyester-based adhesives, and urethane-based adhesives can be cited Wait. However, the type of adhesive is selected in consideration of the use and the type of the object to be attached.

When an energy-ray polymerizable compound is blended into the third adhesive layer 32, the third adhesive layer 32 is irradiated with energy rays from the third base film 31 side to harden the energy-ray polymerizable compound. When the energy ray polymerizable compound is hardened, the cohesive force of the third adhesive layer 32 increases, and the adhesive force between the third adhesive layer 32 and the semiconductor wafer W decreases or disappears. Examples of the energy line system include ultraviolet (UV) and electron beams (EB), and ultraviolet rays are preferred. In this embodiment, as a method of reducing or disappearing the adhesive force, the method described in the first embodiment can be adopted.

[Research Engineering]

10C is a diagram illustrating the process of forming the groove W5, attaching the protective sheet 30, and grinding the back surface W6 which is the second surface of the semiconductor wafer W (there is a case called a grinding process).

After the protective sheet 30 is attached, the semiconductor wafer W is ground from the back surface W6 side using the grinder 50. Through grinding, the thickness of the semiconductor wafer W becomes thinner, and finally the semiconductor wafer W is divided into a plurality of semiconductor chips CP. Until the bottom of the groove W5 is removed, grinding is performed from the side of the back surface W6, and the semiconductor wafer W is sliced into individual circuits W2. After that, back grinding is performed as necessary to obtain a semiconductor wafer CP with a specific thickness. In this embodiment, grinding is performed until the back surface W3 as the third surface is exposed.

FIG. 10D shows the state in which the plurality of divided semiconductor wafers CP are held on the protective sheet 30. The semiconductor chip CP with the back surface W3 exposed is held by the protective sheet 30.

[Attaching Process (Second Adhesive Sheet)]

11A is a diagram showing the process of attaching the second adhesive sheet 20 to a plurality of semiconductor chips CP after the grinding process (there is a case called an attaching process).

The second adhesive sheet 20 is attached to the back surface W3 of the semiconductor chip CP. The second adhesive sheet 20 has a second base film 21 and a second adhesive layer 22. The second adhesive sheet 20 is the same as in the first embodiment.

In this embodiment, the adhesive force for the semiconductor wafer W of the second adhesive layer 22 is better than the adhesive force for the semiconductor wafer W of the third adhesive layer 32. For example, when the adhesive force of the second adhesive layer 22 is large, the protective sheet 30 is easily peeled off.

The second adhesive sheet 20 may be attached to the first ring frame. In the case of using the first ring frame, place the first ring frame on the second adhesive layer 22 of the second adhesive sheet 20, and lightly press the first ring frame to fix the second adhesive sheet 20 and the first Ring frame. After that, the second adhesive layer 22 exposed inside the ring shape of the first ring frame is pressed against the semiconductor chip CP. On the back side W3, a plurality of semiconductor chips CP are fixed on the second adhesive sheet 20.

[Stripping Project]

11B is a diagram showing a process of peeling off the protective sheet 30 after attaching the second adhesive sheet 20 to a plurality of semiconductor chips CP (there is a case called a peeling process). When the protective sheet 30 is peeled off, the circuit surfaces W1 of the plural semiconductor chips CP are exposed. In this embodiment, as shown in FIG. 11B, the distance between the semiconductor wafers CP divided by the pre-dicing method is D3. The distance D3 is, for example, 15 μm or more and 110 μm or less.

[Extension Project]

11C is a diagram showing the process of stretching and holding the second adhesive sheet 20 of the plurality of semiconductor chips CP.

In the expansion process, the interval between the plural semiconductor chips CP is further expanded. The method of stretching the second adhesive sheet 20 in the expansion process is not particularly limited. As a method of stretching the second adhesive sheet 20, for example, a method of stretching the second adhesive sheet 20 by pressing an annular expander or a circular expander on the second adhesive sheet 20, and Using a gripping member or the like, a method of grasping the outer peripheral portion of the second adhesive sheet 20 and stretching the second adhesive sheet 20 and the like.

In this embodiment, as shown in FIG. 11C, the distance between the semiconductor wafers CP after the expansion process is D4. The distance D4 is greater than the distance D3. The distance D4 is, for example, 200 μm or more and 5000 μm or less.

[Transfer Engineering]

FIG. 12A is a diagram showing the process of transferring the semiconductor wafer CP to the surface protection sheet 40 as the fourth adhesive sheet after the expansion process (it may be referred to as the fourth transfer process). The surface protection sheet 40 is the same as in the first embodiment.

In the fourth transfer process, the surface protection sheet 40 is pasted on the circuit surface W1 of the plurality of semiconductor chips CP.

[Stripping Project]

12B is a diagram showing the process of peeling the second adhesive sheet 20 from the plurality of semiconductor chips CP. When the second adhesive sheet 20 is peeled off, the back surface W3 of the semiconductor chip CP is exposed.

[Transfer Engineering]

After peeling off the second adhesive sheet 20 and exposing the back surface W3 of the semiconductor wafer CP, in the same way as the second transfer process of the first embodiment, transfer a plurality of semiconductor wafers CP to the holding surface 201 of the holding member 200. engineering.

After the plural semiconductor wafers CP are transferred to the holding surface 201, the semiconductor wafer arrangement process can be carried out in the same manner as in the first embodiment.

. Effect of implementation form

According to this embodiment, the same effect as the first embodiment can be obtained.

Furthermore, according to the present embodiment, since the semiconductor wafer W is divided into a plurality of semiconductor chips CP by the so-called dicing method, it is possible to prevent the disorder of the arrangement state of the semiconductor chips CP when the semiconductor chips CP are divided into pieces.

Furthermore, according to this embodiment, a plurality of semiconductor chips CP sliced by a first dicing method can be attached to the second adhesive sheet 20, and the second adhesive sheet 20 can be stretched to enlarge the plurality of semiconductor chips CP Those who are separated from each other. In the expansion process, it is also possible to prevent the disorder of the arrangement state of the plural semiconductor chips CP.

(Third Embodiment)

Next, the third embodiment of the present invention will be described. However, in the following description, the description of the same parts as those already described will be omitted.

The manufacturing method of the semiconductor device of the present embodiment is after arranging a plurality of semiconductor wafers CP, and after the sealing process of sealing the plurality of semiconductor wafers CP transferred on the surface protection sheet 40, it is mainly related to the semiconductor of the first embodiment. The manufacturing method of the device is different. The other points are that the third embodiment is the same as the first embodiment, and the description is omitted or simplified. However, the arrangement jig or arrangement method described in the first embodiment is also applied to this embodiment.

[Frame component paste project]

13A is a diagram showing the process of attaching the frame member 400 to the fourth adhesive layer 42 of the surface protection sheet 40 (there is a case called the frame member attaching process).

The frame member attaching process is preferably implemented after the third transfer process shown in FIG. 7A of the first embodiment is implemented. In the frame member attaching process, the frame member 400 is attached to the surface protection sheet 40 to which the semiconductor wafer CP is transferred. The surface protection sheet 40 is the same as in the first embodiment.

The frame member 400 according to this embodiment is formed in a lattice shape and has a plurality of openings 401. The frame member 400 is preferably formed of a material having heat resistance. The material of the frame member 400 includes, for example, metal and heat-resistant resin. Examples of the metal system include copper, stainless steel, and the like. Examples of heat-resistant resin systems include polyimide resins, glass polyester resins, and the like.

The opening 401 is a hole that penetrates the front and back of the frame member 400. The shape of the opening 401 is such that it can accommodate the semiconductor chip CP in the frame, and is not particularly limited. The depth of the hole of the opening 401 is also such that it can accommodate the semiconductor chip CP, and is not particularly limited.

When attaching the frame member 400 to the surface protection sheet 40, the frame member 400 is attached to the fourth adhesive layer 42 so as to accommodate the semiconductor chip CP in each opening 401.

[Closed Project]

13B is a diagram showing the process of sealing the semiconductor chip CP and the frame member 400 pasted on the surface protection sheet 40.

The material of the sealing member 63 is a thermosetting resin, for example, epoxy resin etc. are mentioned. Regarding the epoxy resin used as the sealing member 63, for example, phenol resin, synthetic rubber, inorganic filler, hardening accelerator, and the like may also be contained.

When the semiconductor wafer CP and the frame member 400 are covered by using the sealing member 63, a sealing body 3D is formed.

The method of sealing the semiconductor wafer CP and the frame member 400 by the sealing member 63 is not particularly limited. For example, a method of using a sheet-like sealing resin can be cited. A sheet-like sealing resin is placed so as to cover the semiconductor wafer CP and the frame member 400, and the sealing resin is heated and cured to form a sealing resin layer.

In the case of using a sheet-like sealing resin, it is preferable to seal the semiconductor wafer CP and the frame member 400 by a vacuum lamination method. Through this vacuum lamination method, the generation of voids between the semiconductor wafer CP and the frame member 400 can be prevented. The temperature condition range of heat curing by the vacuum lamination method is, for example, 80°C or more and 120°C or less.

After the plurality of semiconductor chips CP are sealed to form the sealed body 3D, the manufacturing process of the semiconductor package can be carried out in the same manner as in the first embodiment.

. Effect of implementation form

According to this embodiment, the same effect as the first embodiment can be obtained.

Moreover, as in this embodiment, inside the enclosure 3D, not only Since the semiconductor chip CP can also be enclosed by the frame member 400, the rigidity of the enclosed body 3D is improved. As a result, when a large number of semiconductor chips CP are enclosed with a relatively wide area, as in this embodiment, it is also possible to suppress warpage of the semiconductor package.

(Fourth Embodiment)

Next, the fourth embodiment of the present invention will be described. However, in the following description, the description of the same parts as those already described will be omitted.

The manufacturing method of the semiconductor device of this embodiment is based on the point where the alignment jig 100 is placed on the holding surface 201 of the holding member 200 before the plural semiconductor wafers CP are transferred to the holding member 200. This is mainly related to the first embodiment. The manufacturing method of the semiconductor device of the form is different. The other points are the same as the present embodiment and the first embodiment, so the description will be omitted or simplified. However, the arrangement jig or arrangement method described in the first embodiment is also applied to this embodiment.

[Fixture Placement Project]

14A is a diagram showing and explaining the process of placing the array jig 100 on the holding surface 201 of the holding member 200. The jig placing process of this embodiment is different from the jig placing process of the first embodiment at a point where a plurality of semiconductor wafers CP are not transferred to the holding surface 201 in advance. In this embodiment, it is preferable to adsorb and hold the array jig 100 on the holding surface 201.

The fixture placement engineering system of this embodiment is the same as the first Since the embodiment is the same, the description is omitted.

[Transfer Engineering]

14B is a diagram showing a process of transferring a plurality of semiconductor wafers CP to the holding surface 201 of the holding member 200 after the second expansion process (refer to FIG. 5B) explained in the first embodiment.

The transfer process in this embodiment is different from the second transfer process in the first embodiment at the point where the alignment jig 100 is placed on the holding surface 201 in advance. In the transfer process of this embodiment, the back surface W3 of the plurality of semiconductor wafers CP held by the second adhesive sheet 20 is placed toward the holding surface 201. The semiconductor chip CP is placed in the accommodating part 101 of the arrangement jig 100. In this embodiment, by sucking and holding the alignment jig 100 on the holding surface 201, it is possible to prevent the alignment jig 100 from moving above the holding surface 201 during the transfer process. In the transfer process of this embodiment, by preventing the movement of the alignment jig, contact between the semiconductor chip CP and the alignment jig 100 can be prevented.

[Stripping Project]

14C is a diagram illustrating the process of peeling the second adhesive sheet 20 from the semiconductor chip CP after placing the semiconductor chip CP on the holding surface.

When peeling off the second adhesive sheet 20, it is preferable to drive the pressure reducing means to adsorb and hold the plurality of semiconductor wafers CP on the holding surface 201. Furthermore, when the second adhesive sheet 20 is peeled off, it is better to also adsorb and hold the arrangement jig 100 on the holding surface 201.

After the plural semiconductor wafers CP are transferred to the holding surface 201 of the holding member 200, the process of arranging the semiconductor wafers CP can be implemented as the semiconductor wafer arranging process of the first embodiment. After the semiconductor wafer arrangement process, it can also be implemented as in the first embodiment.

. Effect of implementation form

According to this embodiment, the same effect as the first embodiment can be obtained.

(Fifth Embodiment)

Next, the fifth embodiment of the present invention will be described. However, in the following description, the description of the same parts as those already described will be omitted.

The manufacturing method of the semiconductor device of this embodiment is that after arranging a plurality of semiconductor wafers CP, not only the semiconductor wafers CP but also the alignment jig 100 is also transferred to the points on the surface protection sheet 40. This is mainly related to the first embodiment. The manufacturing method of the semiconductor device of the form is different. The other points are the same as the present embodiment and the first embodiment, so the description will be omitted or simplified. However, the arrangement jig or arrangement method described in the first embodiment is also applied to this embodiment.

[Transfer Engineering]

15A is shown to illustrate that the semiconductor chip CP and the alignment jig 100 arranged in the semiconductor chip alignment process are transferred to the surface for protection Diagram of the process of sheet 40.

The transfer process of this embodiment is preferably implemented after the semiconductor wafer arrangement process of the first embodiment or the third embodiment is performed.

In the transfer process of this embodiment, the surface protection sheet 40 is pasted on the circuit surface W1 of the arranged plural semiconductor chips CP and the arrangement jig 100. When attaching the surface protection sheet 40, it is preferable to adsorb and hold the plurality of semiconductor chips CP and the arrangement jig 100 on the holding surface 201.

After being pasted, the holding surface 201 of the holding member 200 separates the semiconductor chip CP and the arrangement jig 100. When the semiconductor wafer CP and the arrangement jig 100 are separated from the holding surface 201, it is preferable to release the suction holding via the holding surface 201 and to reduce the suction holding force.

[Closed Project]

15B is a diagram illustrating the process of sealing the plurality of semiconductor chips CP held by the surface protection sheet 40 and the arrangement jig 100.

When the semiconductor chip CP and the arrangement jig 100 are covered by the sealing member 60, the sealing body 3E is formed. The semiconductor chip CP accommodated in the accommodating portion 101 of the array jig 100 is also filled with a sealing member 60. The closing method is the same as described above.

After the plurality of semiconductor chips CP are sealed to form the sealed body 3E, the manufacturing process of the semiconductor package can be carried out in the same manner as in the first embodiment.

. Effect of implementation form

According to this embodiment, the same effect as the first embodiment can be obtained.

Furthermore, according to the present embodiment, not only the semiconductor chip CP but also the closed arrangement jig 100 can be placed inside the enclosed body 3E, so the rigidity of the enclosed body 3E is improved. As a result, when a large number of semiconductor chips CP are enclosed with a relatively wide area, as in this embodiment, it is also possible to suppress warpage of the semiconductor package.

(Sixth Embodiment)

Next, the sixth embodiment of the present invention will be described. However, in the following description, the description of the same parts as those already described will be omitted.

The manufacturing method of the semiconductor device of this embodiment is that after arranging a plurality of semiconductor chips CP and sealing the plurality of semiconductor chips CP transferred on the surface protection sheet 40, the process of manufacturing a semiconductor package is mainly the same as that of the first embodiment. The manufacturing method of the semiconductor device is different. The other points are the same as the present embodiment and the first embodiment, so the description will be omitted or simplified. However, the arrangement jig or arrangement method described in the first embodiment is also applied to this embodiment.

For FIGS. 16A, 16B, and 16C (collectively these are referred to as Figure 16), Figure 17A, and Figure 17B (collectively referred to as Figure 17), and Figures 18A, 18B and Fig. 18C (these are collectively referred to as Fig. 18), it is shown that it is manufactured using plural semiconductor chips CP The diagram of the semiconductor packaging project.

In this embodiment, a process of forming a rewiring layer on the support, electrically connecting the rewiring layer, and a semiconductor wafer enclosed in the enclosed body is included. The manufacturing process of the semiconductor package described in this embodiment is called RDL-First. RDL is an abbreviation for Redistribution Layer.

16A shows a support 80 having a support substrate 81 and a peeling layer 82 formed on the surface of the support substrate 81.

Examples of the material system of the support substrate 81 include glass and silicon wafers. The surface of the support substrate 81 is preferably smooth.

The peeling layer 82 is formed of a material having peelability. For example, the release layer 82 can be formed by laminating a release tape on the support substrate 81. The release tape is preferably one having a release base material and a release agent layer, for example. In the case of using the release tape constructed in this way, the release agent layer is exposed on the surface and is laminated on the surface of the support substrate 81. The method of attaching the release base material and the supporting substrate 81 is not particularly limited. For example, when an adhesive layer is interposed between the release base material and the supporting substrate 81, the release tape and the supporting substrate 81 may be attached.

In addition, a metal film may be formed on the peeling layer 82 as necessary. The metal film system can be formed by, for example, a sputtering method. Examples of the metal system constituting the metal film include metals selected from the group consisting of titanium and aluminum. When a metal film is formed on the peeling layer 82, a rewiring layer described later is formed on the metal film.

[Rewiring layer formation project]

16B is a diagram illustrating the process of forming the rewiring layer RDL on the peeling layer 82 of the support 80.

The rewiring layer RDL has an insulating resin layer 83 and a rewiring 84 covered by the insulating resin layer 83.

In the process of forming the rewiring layer, the rewiring 84 and the insulating resin layer 83 covering the rewiring 84 are formed. The rewiring layer RDL can also be formed by using a known rewiring layer forming method. In addition, the redistribution layer RDL can also be formed by the formation method of the redistribution layer in the manufacturing process of RDL-First. In addition, the rewiring layer RDL can also be formed by using the same method as the method for forming the rewiring layer described in the first embodiment.

The rewiring 84 has an internal electrode pad 84A electrically connected to the internal terminal electrode W4 of the semiconductor chip CP, and an external electrode pad 84B electrically connected to the external terminal electrode.

The internal electrode pad 84A is located on the surface side of the first laminated body 80A in which the rewiring layer RDL is formed on the support 80. In the first laminated body 80A, the internal electrode pad 84A is exposed.

The external electrode pad 84B is in the first laminated body 80A, and is located inside the first laminated body 80A. The external electrode pad 84B is located in the inside of the first laminate 80A and faces the release layer 82. In the first laminate 80A, the external electrode pad 84B is exposed.

[Protrusion electrode formation project]

16C is illustrated in the internal electrical circuit of the first laminated body 80A. The electrode spacer 84A is a drawing of the process of forming the protruding electrode 85.

In the process of forming the bump electrode, a solder ball or the like is placed on the internal electrode pad 84A, and the bump electrode 85 and the internal electrode pad 84A are electrically connected via solder bonding or the like. The material of the solder balls is not particularly limited. For example, lead-containing solder, lead-free solder, and the like can be cited.

After forming a plurality of protruding electrodes 85 on the first laminated body 80A, a sealing resin film 86 is attached to the surface of the first laminated body 80A so as to cover the plurality of protruding electrodes 85. Examples of the sealing resin film 86 system include NCF (Non Conductivity Film).

[Enclosure Formation Project]

FIG. 17A shows an enclosure 3A that encloses a plurality of semiconductor wafers CP arranged by the semiconductor wafer arrangement method according to the first embodiment.

The closing body 3A can be formed in the same manner as in the first embodiment. However, in the enclosed body 3A shown in FIG. 17A and the enclosed body 3 shown in FIG. 7B, the number of the enclosed semiconductor chips CP is different in the description. The enclosure 3A can also be formed in the same manner as the enclosure 3 when the enclosure process is performed after the semiconductor wafer arrangement process is performed.

After the semiconductor wafer CP is sealed, when the surface protection sheet 40 is peeled off, a sealing body 3A in which the circuit surface W1 and the internal terminal electrode W4 of the semiconductor wafer CP are exposed can be obtained.

In addition, in the closed system of this embodiment, like the closed body 3D of the third embodiment, not only the semiconductor chip CP, but also the sealing of the frame member 400 is closed. Body can also be.

In addition, in the closed system of the present embodiment, such as the closed body 3E of the fifth embodiment, not only the semiconductor chip CP but also the closed body of the array jig 100 may be closed.

[Semiconductor wafer connection project]

17B is a diagram illustrating the process of electrically connecting the semiconductor chip CP of the enclosure 3A and the internal electrode pad 84A of the first laminate 80A. However, this connection engineering system can be implemented through a flip-chip connection method.

In the connection process of this embodiment, the exposed surface of the internal terminal electrode W4 of the sealing body 3A faces the surface of the sealing resin film 86 on which the protruding electrode 85 covering the first laminate 80A is formed. Next, the positions of the plurality of internal terminal electrodes W4 of the enclosure 3A and the positions of the plurality of protruding electrodes 85 of the first laminated body 80A are aligned with each other, and the positions are controlled.

After the position control, the sealing body 3A is pressed against the first laminated body 80A, the internal terminal electrode W4 of the semiconductor wafer CP is inserted into the sealing resin film 86, and the internal terminal electrode W4 is brought into contact with the protruding electrode 85. When the internal terminal electrode W4 is brought into contact with the protruding electrode 85, a second laminated body 80B is formed to bond the sealing body 3A and the first laminated body 80A.

The second laminated body 80B is sandwiched from the closed body 3A side and the first laminated body 80A side using pressing members, and the second laminated body 80B is heated and pressed for a specific time. As the pressing member system, a pressing plate can be cited. As the material of the pressing plate, metal or resin can be mentioned.

When the second laminated body 80B is pressed by heating, the internal terminal electrode W4 and the internal electrode pad 84A are electrically connected by the protruding electrode 85, and the sealing resin film 86 is cured.

Through this connection process, since the sealing resin film 86 is filled between the sealing body 3A and the first laminated body 80A, the electrical connection between the internal terminal electrode W4 and the protruding electrode 85 is reinforced.

[Support stripping project]

18A is a diagram showing the process of peeling the support 80 from the second laminate 80B.

When the support 80 is peeled from the second laminate 80B, the external electrode pad 84B of the rewiring 84 is exposed. When the support 80 is peeled off from the second laminated body 80B, a third laminated body 80C in which the rewiring layer RDL and the sealing body 3A are laminated can be obtained.

[Connection with external terminal electrode]

FIG. 18B is a diagram showing and explaining the process of connecting the external terminal electrode to the third laminate 80C.

On the external electrode pad 84B of the third laminate 80C, an external terminal electrode 87 such as a solder ball is placed, and the external terminal electrode 87 and the external electrode pad 84 are electrically connected through solder bonding or the like. The material of the solder balls is not particularly limited. For example, lead-containing solder, lead-free solder, and the like can be cited.

[Cutting Engineering]

18C is a diagram illustrating the process of the third laminated body 80C to which the external terminal electrodes 87 are connected to individual pieces.

In this dicing process, the third layered body 80C is sliced in units of semiconductor wafer CP. The method of forming the third laminate 80C into individual pieces is not particularly limited. For example, the same method as the method of dicing the aforementioned semiconductor wafer W can be used to form the third layered body 80C into individual pieces. The process of making the third layered body 80C into individual pieces may be implemented by attaching the third layered body 80C to an adhesive sheet such as a dicing sheet.

The semiconductor package 1A of the semiconductor chip CP unit is manufactured by using the third layered body 80C as individual pieces.

. Effect of implementation form

According to this embodiment, the same effect as the first embodiment can be obtained.

In this embodiment, similar to the first embodiment, the semiconductor chip arrangement process is performed, and the arrangement method using the arrangement jig 100 is implemented. After arranging a plurality of semiconductor chips CP at equal intervals, the sealing process can be implemented. Or semiconductor packaging engineering.

Therefore, in the enclosed body 3A, a plurality of semiconductor wafers CP are enclosed at more even intervals. Furthermore, since the plurality of semiconductor chips CP are enclosed at equal intervals, it is easy to align the positions of the plurality of internal terminal electrodes W4 of the enclosed body 3A and the positions of the plurality of protruding electrodes 85 of the first laminated body 80A. Furthermore, the positional deviation of the connection position can also be suppressed.

(The seventh embodiment)

Next, the seventh embodiment of the present invention will be described. However, in the following description, the description of the same parts as those already described will be omitted.

This embodiment relates to a method of transferring a plurality of sheet-like bodies arranged through the arrangement method of the aforementioned embodiment to a support. In this embodiment, a form in which semiconductor wafers are arranged as a sheet-like body and then transferred to a support is explained as an example. The sheet system that can be transferred by the transfer method of the present invention is not limited to semiconductor wafers.

In the first embodiment, regarding the process (third transfer process) of transferring the aligned semiconductor wafers CP to the surface protection sheet 40 after the semiconductor wafer aligning process is performed, the transfer method related to this embodiment is The point where the arranged semiconductor chip CP is transferred to a hard support having an adhesive surface instead of the surface protection sheet 40 is mainly different from the first embodiment and the present embodiment.

[Repost Project]

For FIGS. 19A and 19B, a diagram illustrating a method of transferring a semiconductor chip CP to a rigid support having an adhesive surface is shown.

19A shows a rigid support 500A having a rigid substrate 500 and an adhesive layer 501 formed on the surface of the rigid substrate 500. The outer surface of the adhesive layer 501 is equivalent to the adhesive surface 502.

As the hard substrate 500, for example, a substrate made of glass or the like can be used. The hard substrate 500 is preferably one having heat resistance. For example, via The temperature at which the hard substrate 500 deforms when heated is higher than the temperature at which the adhesive sheet deforms through heating, and it is better.

The adhesive layer 501 contains an adhesive. The adhesive contained in the adhesive layer 501 is not particularly limited, and various types of adhesives can be applied to the adhesive layer 501. As the adhesive contained in the adhesive layer 501, for example, rubber-based, acrylic-based, silicone-based, polyester-based, and urethane-based adhesives can be cited. However, the type of adhesive is selected in consideration of the use and the type of the object to be attached. In the case of disposing an energy ray polymerizable compound in the adhesive layer 501, the adhesive layer 501 is irradiated with energy rays from the side of the hard substrate 500 to harden the energy ray polymerizable compound. When the energy-ray polymerizable compound is hardened, the cohesive force of the adhesive layer 501 is increased, and the adhesive force between the adhesive layer 501 and the semiconductor chip CP may decrease or disappear. Examples of the energy line system include ultraviolet (UV) and electron beams (EB), and ultraviolet rays are preferred. As a method of reducing or disappearing the adhesive force between the adhesive layer 501 and the semiconductor wafer CP, for example, as in the first embodiment, a method of irradiation with energy rays, a method of heating, a method of heating and energy Any of the method of beam irradiation and the method of cooling.

19B shows a hard support 500B having a hard base 500 and a surface protection sheet 40 formed on the surface of the hard base 500. The surface protection sheet 40 has a fourth base film 41 and a fourth adhesive layer 42. In the hard support 500B, the fourth adhesive layer 42 is exposed on the surface, and the outer surface of the fourth adhesive layer 42 is equivalent to the adhesive surface 43.

In this embodiment, the semiconductor chip CP arranged in the semiconductor chip arrangement process is transferred to the adhesive surface 502 of the rigid support 500A. Or the adhesive surface 43 of the rigid support 500B.

19A and 19B illustrate the configuration where the alignment jig 100 is not attached. However, at the same time as the semiconductor chip CP after the alignment, the alignment jig 100 may be transferred to a hard support.

After the semiconductor chip CP is transferred to the hard support, the manufacturing method of the semiconductor device can be implemented in the same manner as in the foregoing embodiment. For example, instead of the third transfer process of the first embodiment, the transfer process of this embodiment is implemented, and other engineering systems can be performed in the same manner as in the first embodiment.

. Effect of implementation form

According to this embodiment, the same effect as the first embodiment can be obtained.

Furthermore, the heat resistance of the hard substrate 500 is higher than that of adhesive sheets such as surface protection sheets. According to this embodiment, a hard support with a semiconductor chip CP can be used for high-temperature heating. Engineer. In addition, the hard base 500 is formed of a hard material compared to a surface protection sheet, etc., so according to this embodiment, the semiconductor chip CP can be more stably supported and transported in the manufacturing process of semiconductor packaging, etc. .

[Transformation of Implementation Mode]

The present invention is not limited to the above-mentioned embodiment in any way. The present invention is within the scope of achieving the object of the present invention, and includes modifications to the above-mentioned embodiments.

For example, semiconductor wafers and circuits of semiconductor wafers are not limited to the arrangement or shape shown in the figure. The connection structure with the external terminal electrode of the semiconductor package, etc. are not limited to the form described in the foregoing embodiment. In the foregoing embodiment, the form of manufacturing FO-WLP type semiconductor packages has been described as an example, but the present invention is also applicable to the form of manufacturing fan-in type WLP and other semiconductor packages.

For example, the number of accommodating parts included in the array jig is not limited to the example of the array jig described in the first embodiment. It is possible to use an arrangement jig with accommodating parts corresponding to the number of lamellae such as semiconductor chips.

In addition, for example, the outer shape of the main body of the array jig is not limited to the circular shape as described in the first embodiment, and examples of shapes other than the circular shape include a rectangle, a square, or an ellipse.

For example, in the description of the arrangement method of the first embodiment, the method of arranging semiconductor wafers by moving the arrangement jig in the 2B direction and 2C direction in the figure in two stages was explained as an example, but the present invention is not Limited to such a form. For example, by moving the arrangement jig and the holding surface of the holding member through the direction (for example, the oblique direction) in which the recessed portion of the accommodating corner of the array jig is accommodated in the corner of the semiconductor wafer, the semiconductor wafer can be made Arranger.

In addition, the direction of moving the holding surface is not limited to the horizontal direction. For example, when the holding surface is inclined, the semiconductor wafer CP may be moved and bonded to the wall of the array jig.

For example, in the first embodiment, a mode in which the expansion process is performed twice has been described as an example, but the present invention is not limited to such a mode. For example, if Insert the frame of the arranging jig between the semiconductor wafers, and the expansion process can also be done once.

For example, in the second embodiment, a mode in which the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W and the trench formation process is performed has been exemplified, but the present invention is not limited to such a mode. For example, as another form, the protection sheet 30 is not attached to the circuit surface W1, and the circuit surface W1 is kept exposed, and the groove formation process is performed. After the groove is formed, the first adhesive sheet is attached to the circuit surface W1. 10. Implementation of the form of grinding engineering. In addition, before the trench formation process, a protective film covering the circuit surface W1 may be formed. The protective film preferably has a shape that exposes the internal terminal electrode W4 of the circuit W2. For example, the protective film is preferably formed by using silicon nitride, silicon oxide, or polyimide.

For example, in the second embodiment, an example is described in which the second adhesive sheet 20 is stretched to expand the interval between the plurality of semiconductor chips CP. However, it may be implemented by adding an expansion process. In the case of performing multiple expansion processes, the plurality of semiconductor chips CP held on the second adhesive sheet 20 are maintained at a distance between the expansions, transferred to another expansion sheet, and the expansion sheet is stretched to expand the plurality of semiconductors. The distance between the chips CP. For example, in the second embodiment, after the surface protection sheet 40 is attached, the surface protection sheet 40 may be stretched to increase the distance between the plurality of semiconductor wafers CP.

For example, in the second embodiment, the method of manufacturing a semiconductor device including a process of forming a trench having a cut depth shallower than the thickness of a semiconductor wafer has been exemplified, but a semiconductor wafer with the trench formed in advance may be used.

In the second embodiment, after forming the trench W5 on the semiconductor wafer W, the form of attaching the protective sheet 30 as the third adhesive sheet to the circuit surface W1 has been exemplified, but the present invention is not limited to such a form.

For example, when the circuit surface W1 is protected by the circuit surface protection sheet, such as the formation of the groove W5, contamination or damage of the circuit surface W1 or the circuit W2 through cutting chips can be prevented. In this case, a cut is made from the side of the circuit surface protection sheet to completely cut the circuit surface protection sheet, and then a cut shallower than the thickness of the semiconductor wafer W is made from the circuit surface W1 of the semiconductor wafer W to form a groove W5. Furthermore, in this form, the first adhesive sheet 10 may be pasted on the side of the protective sheet 30 before grinding. After the first adhesive sheet 10 is attached, a grinder 50 is used to grind the semiconductor wafer W from the back side W6 side. The first adhesive sheet 10 has a first base film 11 and a first adhesive layer 12. The first adhesive layer 12 is laminated on the first base film 11. The first adhesive sheet 10 has the same shape as the semiconductor wafer W, and it may be cut in advance. In addition, prepare the first adhesive sheet 10 larger than the semiconductor wafer W and attach it to the semiconductor wafer W. It may be cut into the same shape as the semiconductor wafer W. In addition, in this form, the first adhesive layer 12 includes: in the subsequent process, the cut protective sheet 30 is also peelable together. In comparison, an adhesive with a strong adhesive force is better. The first base film 11 has a structure that is not stretched during peeling, such as polyethylene terephthalate, and relatively high rigidity is preferred.

In addition, as a method of forming a sheet-like body such as a semiconductor wafer CP, for example, the arrangement method of the form of the following [1] and [2] can also be mentioned.

[1] An arrangement method that uses an arrangement jig to make plural pieces The arrangement method of the body arrangement, wherein the sheet-like system has: a first side surface, a second side surface adjacent to the first side surface, and a sheet positioned at the end of the first side surface and the end of the second side surface Shaped body corners; the aforementioned array fixture system is provided with: a plurality of receiving portions that can accommodate sheet-shaped bodies, and the aforementioned receiving portion has: a wall portion, and a receiving corner; the aforementioned wall portion has: a first side wall, and and The second side wall adjacent to the first side wall; the accommodating corner is located at the end of the first side wall and the end of the second side wall; the accommodating corner has: a surface recessed in the first side wall, The surface of the second side wall and the second side wall are deep-side recessed portions; including: the process of joining the first side surface of the sheet-shaped body and the first side wall of the receiving portion, and the process of joining the second side surface of the sheet-shaped body and The process of arranging the second side wall of the accommodating part and the process of accommodating the corner of the sheet-shaped body in the recessed part of the accommodating corner.

According to this arranging method, it is possible to arrange a plurality of flakes at more even intervals easily and quickly.

[2] In the arranging method of the form of [1], it is preferable that the plurality of the receiving parts are arranged in a lattice shape, and it is more preferable to arrange them in a square lattice shape.

[Example]

Hereinafter, the present invention will be explained in more detail with examples. The present invention is not limited to these embodiments.

In Example 1, the arrangement method using the arrangement jig of the aforementioned first embodiment was implemented. That is, in the first embodiment, a copper arrangement jig having a plurality of storage portions in the shape shown in FIG. 2A is used. A copper plate with a thickness of 3mm was installed on the side of the array jig to close the opening on one side, and the semiconductor chip was placed on the copper plate from the opening side of the other side, and then the semiconductor chip was joined to the wall of the receiving portion (refer to Figure 2C).

As reference example 1, in the foregoing embodiment, the arrangement method using the arrangement jig of the reference example described in FIG. 3A is implemented. In Reference Example 1, the same operation as Example 1 was performed except that the array jig was changed. The inner dimension (the distance between the opposing side walls) of the accommodating part of the arrangement jig used in this embodiment (Example 1 and Reference Example 1) and the width of the grid frame of the arrangement jig, as well as the width of the grid frame used in this embodiment The dimensions of the semiconductor wafer are as follows. However, the shape of the recess of the arrangement jig used in Example 1 is a semicircle with a diameter of about 0.4 mm.

After implementing each arrangement method of Example 1 and Reference Example 1, compare the degree to which the semiconductor wafers are arranged at equal intervals.

. The inner size of the accommodating part of the arrangement jig: 4.6mm×4.6mm

. Width of grid frame for arranging fixtures: 0.4mm

. The size of semiconductor wafer: 3mm×3mm, thickness 350μm

However, in this embodiment, the shape of the accommodating portion is the same shape as the accommodating portion described in the first embodiment and the reference example, but Use a jig that has more accommodating parts than those shown in the previous embodiment and the reference example. In the arrangement jig, 3 storage areas with a total of 16 storage areas (4 vertical x 4 horizontal) are defined, and semiconductor chips are accommodated in the storage areas of 3 storage areas (48 positions in total), and the arrangement method is implemented.

After the arrangement method is implemented, a measuring instrument with an XY stage is used to digitize the center coordinates of each semiconductor chip with a common coordinate system. The measuring device used a CNC image measuring device manufactured by Mitutoyo Co., Ltd. (product name: QV ACCEL HYBRID TYPE1).

Among the three storage areas, one storage area (the first area) is selected, the first area is used as a reference, and the other two areas are used as the second area and the third area.

The X-axis direction and Y-axis direction of the first area as a reference, and the X-axis direction and Y-axis direction of the second area are minimized. The angle (tilt) of the storage area is not changed and overlaps the data. on. The first area and the third area are also superimposed on the data in the same manner as described above.

After overlapping, the 16 accommodating portions in the first area and the 16 accommodating portions in the second or third area are compared with the coordinates of the semiconductor wafers accommodated in the accommodating portions corresponding to each area. Here, the coordinates of the semiconductor wafer in the first area are used as a reference, and how much the coordinates of the semiconductor wafer in the second area deviate from the reference coordinates are calculated. Similarly, using the first area as a reference, calculate how much the coordinates of the semiconductor wafer in the third area are shifted.

Table 1 shows the calculated X-axis direction, Y-axis direction, and the amount of unevenness of the inclination after the arrangement method of Example 1 and Reference Example 1 are implemented. Calculation results.

However, the inclination means that the diagonal line connecting the semiconductor wafer in the first region is used as a reference, and the diagonal line connecting the semiconductor wafer in the second region or the third region is compared to show the degree of inclination.

As shown in Table 1, according to the arrangement method using the arrangement jig of Example 1, compared with Reference Example 1, it is understood that the semiconductor wafers are displaced in the X-axis direction, Y-axis direction, and the tilted position of each other. The amount is small. That is, according to the arrangement method using the arrangement jig of the first embodiment, it is possible to arrange a plurality of semiconductor wafers at more equal intervals.

The arrangement jig and the arrangement method described in embodiments other than the first embodiment or the modification of the embodiment are also the same as the first embodiment. Compared with Reference Example 1, it is possible to make plural numbers at more equal intervals. Array of semiconductor chips.

100: Arrangement fixture

110: main body

110A: Outer frame

110B: inner frame

CP: Semiconductor chip

101: Containment Department

102: Wall

102a: first side wall

102b: second side wall

102c: third side wall

102d: Fourth side wall

103: Containment Corner

103a: First Containment Corner

103b: second containment corner

130c: Third Containment Corner

103d: Fourth Containment Corner

104: Depressed part

Claims (4)

A method of manufacturing a semiconductor device, including the process of arranging a plurality of sheet-like bodies using an arrangement jig, the process of transferring the arranged plurality of the sheet-like bodies to a surface protection sheet, and the process of sealing and holding on the surface protection sheet The process of plural pieces of the aforementioned sheet-like bodies; the aforementioned arrangement jig is equipped with plural accommodating parts capable of accommodating the aforementioned piece-like bodies, and the accommodating corners of the aforementioned accommodating parts are arranged to accommodate each of the aforementioned sheet-like bodies in the plural accommodating parts to join the aforementioned When the sheet-like body is on the wall of the receiving portion, the sheet-like body corners of the sheet-like body are formed without contacting the receiving corners. For example, in the method of manufacturing a semiconductor device described in item 1 of the scope of the patent application, the plurality of the aforementioned receiving portions are arranged in a lattice shape. According to the method of manufacturing a semiconductor device described in claim 1, wherein the sheet system has: a first side surface and a second side surface adjacent to the first side surface; and the corner portions of the sheet body are positioned at the first side surface. The end of one side and the aforementioned The end of the second side surface; the wall of the accommodating portion has: a first side wall and a second side wall adjacent to the first side wall; the accommodating corner is located at the end of the first side wall and the first side wall The end of the two side walls; the receiving corner has: a surface recessed in the first side wall, and the surface of the second side wall is a deep side recessed part; where the first side surface of the sheet-shaped body is joined with the When the first side wall of the accommodating portion joins the second side surface of the sheet-shaped body and the second side wall of the accommodating portion, the sheet-shaped body corner of the sheet-shaped body is received in one of the accommodating corners The aforementioned depression. For example, the semiconductor device manufacturing method described in the first item of the scope of the patent application, wherein the plurality of the aforementioned receiving parts are arranged in a square grid.

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