TWI713857B - 半導體裝置封裝及其製造方法 - Google Patents

半導體裝置封裝及其製造方法 Download PDF

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TWI713857B
TWI713857B TW107121787A TW107121787A TWI713857B TW I713857 B TWI713857 B TW I713857B TW 107121787 A TW107121787 A TW 107121787A TW 107121787 A TW107121787 A TW 107121787A TW I713857 B TWI713857 B TW I713857B
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semiconductor device
conductive
conductive pillar
substrate
pillar
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TW107121787A
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TW201946243A (zh
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胡逸群
王銘漢
謝村隆
黃志億
洪志斌
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日月光半導體製造股份有限公司
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Abstract

本發明之至少一些實施例係關於一種半導體裝置封裝。該半導體裝置封裝包括一基板、安置於該基板上之一插入件、安置於該基板上之一導電柱、安置於該插入件上並電連接至該導電柱之一第一半導體裝置、安置於該插入件上之一第二半導體裝置，及環繞該導電柱之一囊封物。該第一半導體裝置包括電連接至該插入件之一第一導電襯墊。該第二半導體裝置包括電連接至該插入件之一第二導電襯墊。

Description

半導體裝置封裝及其製造方法
本發明係關於一種半導體裝置封裝。
在可比的三維半導體封裝中，插入件(例如矽穿孔(TSV)插入件)提供電互連。然而，精細間距(例如小於1微米(µm))互連可佔據插入件之小部分。換言之，具有相對較大間距(例如大於1 µm)之互連可佔據插入件之其他區域。在TSV之直徑增加的情況下，插入件之面積相應地增加。在此類情形下，半導體封裝之面積增加。在TSV之直徑減少的情況下，半導體裝置與插入件之間的未對準可出現。另外，TSV之製造操作係複雜的且插入件之成本因此顯著增加。
此外，一些半導體裝置可具有接地襯墊或電力襯墊以用於大電流。因此，具有小直徑之TSV可遇到短路問題。
在一些實施例中，根據一個態樣，一半導體裝置封裝包括一基板、安置於該基板上之一插入件、安置於該基板上之一導電柱、安置於該插入件上並電連接至該導電柱之一第一半導體裝置、安置於該插入件上之一第二半導體裝置，及環繞該導電柱之一囊封物。該第一半導體裝置包括電連接至該插入件之一導電襯墊。該第二半導體裝置包括電連接至該插入件之一導電襯墊。
在一些實施例中，根據另一態樣，揭示一種用於製造一半導體裝置封裝的方法。該方法包括：提供一基板、一第一半導體裝置及一第二半導體裝置；提供用於電連接該第一半導體裝置及該第二半導體裝置至該基板之一插入件；提供電連接至該基板及該第一半導體裝置之一第一導電柱；及提供一囊封物以環繞該第一導電柱及該插入件。
貫穿圖式及實施方式使用共同參考編號以指示相同或相似組件。自結合附圖的以下詳細描述將更容易理解本發明之實施例。
對於如相關聯圖中所展示之組件之定向，關於某一組件或某一組組件，或一組件或一組組件之某一平面而指定空間描述，諸如「在…之上」、「在…之下」、「上」、「左」、「右」、「下」、「頂部」、「底部」、「垂直」、「水平」、「側」、「較高」、「下部」、「上部」、「在…上方」、「在…下方」等等。應理解，本文中所使用之空間描述僅出於說明之目的，且本文中所描述之結構之實際實施可以任何定向或方式在空間上配置，其限制條件為本發明之實施例之優點不因此配置而有偏差。
圖1A為根據本發明之一些實施例之半導體裝置封裝1的截面圖。半導體裝置封裝1包括基板10、插入件11、底填充料12、導電柱13、半導體裝置14、半導體裝置15、囊封物16、焊球17及環結構19。
基板10具有上表面10u及與上表面10u相對的下表面10b。插入件11安置於基板10之上表面10u上。環結構19安置於基板10之上表面10u上。環結構19鄰近於基板10之周邊而安置。環結構19環繞囊封物16及插入件11。焊球17安置於基板10之下表面10b上。環結構19提供防止彎曲問題之功能。在一些實施例中，環結構19可省略。
插入件11 (例如矽穿孔(TSV)插入件)包括導電通孔111及電端子112。插入件11經由電端子112電連接至基板10。底填充料12安置於基板10與插入件11之間。電端子112由底填充料12環繞。插入件11之導電通孔111的大小(例如高度、寬度或直徑)小於導電柱13之大小。
導電柱13安置於基板10之上表面10u上。導電柱13安置於插入件11之間。導電柱13由插入件11環繞。導電柱13可用作接地路徑或電力路徑。導電柱13之寬度不同於導電通孔111之寬度。導電柱13之寬度大於導電通孔111之寬度。導電柱13之高度大於導電通孔111之高度。導電柱13之寬度足夠大以防止由大電流引起的短路問題。導電柱13之縱橫比大於7。導電柱13之大小可基於所要設計而調整。導電柱13可包括焊接點131。
半導體裝置14安置於插入件11上。半導體裝置14安置於導電柱13上。半導體裝置14包括導電襯墊141及導電襯墊142。導電襯墊141經由導電結構143電連接至插入件11之導電通孔111。該導電結構143可包括接觸插入件11之導電通孔111的焊接點1431。導電襯墊142電連接至導電柱13之焊接點131。半導體裝置14經由插入件11電連接至基板10。半導體裝置14經由導電柱13電連接至基板10。導電襯墊142可為接地襯墊。在一些實施例中，半導體裝置14可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，導電結構143可為焊料凸塊或銅柱凸塊。
半導體裝置15安置於插入件11上。半導體裝置15安置於導電柱13上。半導體裝置15包括導電襯墊151。底填充料12安置於插入件11與半導體裝置15之間。半導體裝置15經由導電襯墊151電連接至插入件11。導電襯墊151電連接至導電結構153。導電結構153可包括接觸插入件11之導電通孔111的焊接點1531。半導體裝置15經由插入件11電連接至基板10。半導體裝置14及半導體裝置15可經由插入件11彼此連通。在一些實施例中，半導體裝置15可為高頻寬記憶體(HBM)。在一些實施例中，導電結構153可為焊料凸塊或銅柱凸塊。
囊封物16安置於基板10之上表面10u上。囊封物16環繞插入件11。囊封物16環繞導電柱13。囊封物16囊封插入件11、導電柱13、半導體裝置14及半導體裝置15。半導體裝置14之上表面由囊封物16曝露。囊封物16具有樹脂材料。囊封物16具有填料。
在一些實施例中，囊封物16中存在一些空隙。空隙位於插入件11與半導體裝置14之間。空隙位於插入件11、導電柱13及半導體裝置14之間。
圖1B為根據本發明之一些實施例之半導體裝置封裝1的俯視圖。插入件11、半導體裝置14、半導體裝置15及環結構19安置於基板10上。環結構19環繞插入件11。四個插入件11環繞導電柱13 (圖1B中未展示)。半導體裝置14安置於插入件11上。半導體裝置15安置於插入件11上。由於插入件11之導電通孔111的大小(例如寬度或直徑)可足夠小，所以插入件11之面積可降低。因此，半導體裝置封裝1之成本可降低。
半導體裝置14可安置於四個插入件11上。在一些實施例中，半導體裝置14可安置於兩個插入件11上。半導體裝置14可安置於六個插入件11上。半導體裝置14可安置於八個插入件11上。
圖2A為根據本發明之一些實施例之半導體裝置封裝1'的截面圖。半導體裝置封裝1'包括基板10、插入件11'、導電柱13'a、導電柱13'b、半導體裝置14、半導體裝置15、囊封物16、焊球17及環結構19。
基板10具有上表面10u及與上表面10u相對的下表面10b。插入件11'可不具有導電通孔。插入件11'經由黏著劑113'安置於基板10之上表面10u上。黏著劑113'安置於基板10與插入件11'之間。環結構19安置於基板10之上表面10u上。環結構19鄰近於基板10之周邊而安置。環結構19環繞囊封物16及插入件11'。焊球17安置於基板10之下表面10b上。環結構19提供防止彎曲問題之功能。在一些實施例中，環結構19可省略。
導電柱13'a安置於基板10之上表面10u上。導電柱13'b安置於基板10之上表面10u上。導電柱13'a安置於插入件11'之間。導電柱13'a由插入件11'環繞。導電柱13'b鄰近於囊封物16之周邊而安置。導電柱13'a或13'b可用作接地路徑或電力路徑。導電柱13'a之大小(例如寬度、直徑或高度)可不同於導電柱13'b之大小。導電柱13'a之大小可與導電柱13'b之大小相同。導電柱13'a或13'b之寬度足夠大以防止由大電流引起的短路問題。導電柱13'a或13'b之縱橫比大於7。導電柱13'a或13'b之大小可基於所要設計而調整。在一些實施例中，導電柱13'b可由導電柱13'a替換。導電柱13'a可包括焊接點13'a1。導電柱13'b可包括焊接點13'b1。
半導體裝置14安置於插入件11'上。半導體裝置14安置於導電柱13'a上。半導體裝置14包括導電襯墊141及導電襯墊142。導電襯墊141經由導電結構143電連接至插入件11'。導電結構143可包括接觸插入件11'之焊接點1431。導電襯墊142電連接至導電柱13'a。導電襯墊142可接觸導電柱13'a之焊接點13'a1。半導體裝置14經由導電柱13'a電連接至基板10。導電襯墊142可為接地襯墊。在一些實施例中，半導體裝置14可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。
半導體裝置15安置於插入件11'上。半導體裝置15安置於導電柱13'b上。半導體裝置15包括導電襯墊151及導電襯墊152。半導體裝置15經由導電襯墊151電連接至插入件11'。導電襯墊151電連接至導電結構153。導電結構153可包括接觸插入件11'之焊接點1531。半導體裝置15經由導電襯墊152電連接至導電柱13'b。導電襯墊152可接觸導電柱13'b之焊接點13'b1。半導體裝置15經由導電柱13'b電連接至基板10。導電襯墊152可為接地襯墊。半導體裝置14及半導體裝置15可經由插入件11'彼此連通。在一些實施例中，半導體裝置15可為高頻寬記憶體(HBM)。在一些實施例中，導電結構153可為焊料凸塊或銅柱凸塊。
囊封物16安置於基板10之上表面10u上。囊封物16環繞插入件11'。囊封物16環繞導電柱13'a。囊封物16環繞導電柱13'b。囊封物16囊封插入件11'、導電柱13'a、導電柱13'b、半導體裝置14及半導體裝置15。半導體裝置14之上表面由囊封物16曝露。囊封物16具有樹脂材料。囊封物16具有填料。
在一些實施例中，囊封物16中存在一些空隙。空隙位於插入件11與半導體裝置14之間。空隙位於插入件11、導電柱13'a及半導體裝置14之間。
圖2B為根據本發明之一些實施例之半導體裝置封裝1'的俯視圖。插入件11'、半導體裝置14、半導體裝置15及環結構19安置於基板10上。四個插入件11'環繞導電柱13'a(圖1B中未展示)。環結構19環繞插入件11'。半導體裝置14安置於插入件11'上。半導體裝置15安置於插入件11'上。由於插入件11'可不具有導電通孔，所以插入件11'之面積可儘可能小地降低。因此，半導體裝置封裝1'之成本可降低。
半導體裝置14可安置於四個插入件11'上。在一些實施例中，半導體裝置14可安置於兩個插入件11'上。半導體裝置14可安置於六個插入件11'上。半導體裝置14可安置於八個插入件11'上。
圖3A為根據本發明之一些實施例之半導體裝置封裝2的截面圖。半導體裝置封裝2包括基板20、插入件21、底填充料22、導電柱23、半導體裝置24、半導體裝置25、囊封物26、焊球27、電連接28及環結構29。
基板20具有上表面20u及與上表面20u相對的下表面20b。插入件21安置於基板20之上表面20u上。電連接28安置於基板20之上表面20u上。電連接28將插入件21電連接至基板20。電連接28可為凸塊。環結構29安置於基板20之上表面20u上。環結構29鄰近於基板20之周邊而安置。環結構29環繞囊封物26及插入件21。焊球27安置於基板20之下表面20b上。環結構29提供防止彎曲問題之功能。在一些實施例中，環結構29可省略。
插入件21 (例如矽穿孔(TSV)插入件)包括導電通孔211及電端子212。插入件21經由電端子212電連接至基板20。插入件21之導電通孔211的大小(例如高度、寬度或直徑)小於導電柱23之大小。
導電柱23安置於基板20之上表面20u上。導電柱23安置於插入件21之間。導電柱23由插入件21環繞。導電柱23可用作接地路徑或電力路徑。導電柱23之寬度不同於導電通孔211之寬度。導電柱23之寬度大於導電通孔211之寬度。導電柱23之高度大於導電通孔211之高度。導電柱23之寬度足夠大以防止由大電流引起的短路問題。導電柱23之縱橫比大於7。導電柱23之大小可基於所要設計而調整。導電柱23可包括焊接點231。
半導體裝置24安置於插入件21上。半導體裝置24安置於導電柱23上。半導體裝置24包括導電襯墊241及導電襯墊242。導電襯墊241經由導電結構243電連接至插入件21之導電通孔211。導電結構243可包括接觸插入件21之導電通孔211的焊接點2431。導電襯墊242電連接至導電柱23。導電襯墊242可接觸導電柱231之焊接點231。半導體裝置24經由插入件21電連接至基板20。半導體裝置24經由導電柱23電連接至基板20。導電襯墊242可為接地襯墊。在一些實施例中，半導體裝置24可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，導電結構243可為焊料凸塊或銅柱凸塊。
半導體裝置25安置於插入件21上。半導體裝置25安置於導電柱23上。半導體裝置25包括導電襯墊251。半導體裝置25經由導電襯墊251電連接至插入件21。導電襯墊251電連接至導電結構253。導電結構253可包括接觸插入件21之導電通孔211的焊接點2531。半導體裝置25經由插入件21電連接至基板20。半導體裝置24及半導體裝置25可經由插入件21彼此連通。在一些實施例中，半導體裝置25可為高頻寬記憶體(HBM)。在一些實施例中，導電結構253可為焊料凸塊或銅柱凸塊。
囊封物26安置於基板20之上表面20u上。囊封物26安置於基板20之上表面20u上方。囊封物26藉由電連接28與基板20隔開。囊封物26環繞插入件21。囊封物26環繞導電柱23。囊封物26囊封插入件21、導電柱23、半導體裝置24及半導體裝置25。半導體裝置24之上表面由囊封物26曝露。囊封物26具有樹脂材料。囊封物26具有填料。囊封物26中不存在空隙。
底填充料22安置於基板20與囊封物26之間。電連接28由底填充料22環繞。底填充料22環繞囊封物26。
圖3B為根據本發明之一些實施例之半導體裝置封裝2的俯視圖。插入件21、半導體裝置24、半導體裝置25及環結構29安置於基板20上。四個插入件21環繞導電柱23(圖3B中未展示)。環結構29環繞插入件21。半導體裝置24安置於插入件21上。半導體裝置25安置於插入件21上。由於插入件21之導電通孔211的大小(例如寬度或直徑)可足夠小，所以插入件21之面積可降低。因此，半導體裝置封裝2之成本可降低。
半導體裝置24可安置於四個插入件21上。在一些實施例中，半導體裝置24可安置於兩個插入件21上。半導體裝置24可安置於六個插入件21上。半導體裝置24可安置於八個插入件21上。
圖4A為根據本發明之一些實施例之半導體裝置封裝2'的截面圖。半導體裝置封裝2'包括基板20、插入件21'、底填充料22、導電柱23'a、導電柱23'b、半導體裝置24、半導體裝置25、囊封物26、焊球27及環結構29。
基板20具有上表面20u及與上表面20u相對的下表面20b。插入件21'可不具有導電通孔。插入件21'安置於基板20之上表面20u上。電連接28安置於基板20之上表面20u上。電連接28將導電柱23'a或23'b電連接至基板20。電連接28可為凸塊。環結構29安置於基板20之上表面20u上。環結構29鄰近於基板20之周邊而安置。環結構29環繞囊封物26及插入件21'。焊球27安置於基板20之下表面20b上。環結構29提供防止彎曲問題之功能。在一些實施例中，環結構29可省略。
導電柱23'a安置於基板20之上表面20u上。導電柱23'b安置於基板20之上表面20u上。導電柱23'a安置於插入件21'之間。導電柱23'a由插入件21'環繞。導電柱23'b鄰近於囊封物26之周邊而安置。導電柱23'a或23'b可用作接地路徑或電力路徑。導電柱23'a之大小(例如寬度、直徑或高度)可不同於導電柱23'b之大小。導電柱23'a之大小可與導電柱23'b之大小相同。導電柱23'a或23'b之寬度足夠大以防止由大電流引起的短路問題。導電柱23'a或23'b之縱橫比大於7。導電柱23'a或23'b之大小可基於所要設計而調整。在一些實施例中，導電柱23'b可由導電柱23'a替換。導電柱23'a可包括焊接點23'a1。導電柱23'b可包括焊接點23'b1。
半導體裝置24安置於插入件21'上。半導體裝置24安置於導電柱23'a上。半導體裝置24包括導電襯墊241及導電襯墊242。導電襯墊241經由導電結構243電連接至插入件21'。導電結構243可包括接觸插入件21'之焊接點2431。導電襯墊242電連接至導電柱23'a。導電襯墊242可接觸導電柱23'a之焊接點23'a1。半導體裝置24經由導電柱23'a電連接至基板20。導電襯墊242可為接地襯墊。在一些實施例中，半導體裝置24可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。
半導體裝置25安置於插入件21'上。半導體裝置25安置於導電柱23'b上。半導體裝置25包括導電襯墊251及導電襯墊252。半導體裝置25經由導電襯墊251電連接至插入件21'。導電襯墊251電連接至導電結構253。導電結構253可包括接觸插入件21'之焊接點2531。半導體裝置25經由導電襯墊252電連接至導電柱23'b。導電襯墊252可接觸導電柱23'b之焊接點23'b1。半導體裝置25經由導電柱23'b電連接至基板20。導電襯墊252可為接地襯墊。半導體裝置24及半導體裝置25可經由插入件21'彼此連通。在一些實施例中，半導體裝置25可為高頻寬記憶體(HBM)。在一些實施例中，導電結構253可為焊料凸塊或銅柱凸塊。
囊封物26安置於基板20之上表面20u上。囊封物26環繞插入件21'。囊封物26環繞導電柱23'a。囊封物26環繞導電柱23'b。囊封物26囊封插入件21'、導電柱23'a、導電柱23'b、半導體裝置24及半導體裝置25。插入件21'嵌入於囊封物26中。半導體裝置24之上表面係由囊封物26曝露。囊封物26具有樹脂材料。囊封物26具有填料。囊封物26中不存在空隙。
圖4B為根據本發明之一些實施例之半導體裝置封裝2'的俯視圖。插入件21'、半導體裝置24、半導體裝置25及環結構29安置於基板20上。四個插入件21'環繞導電柱23(圖4B中未展示)。環結構29環繞插入件21'。半導體裝置24安置於插入件21'上。半導體裝置25安置於插入件21'上。由於插入件21'可不具有導電通孔，所以插入件21'之面積可儘可能小地降低。因此，半導體裝置封裝2'之成本可降低。
半導體裝置24可安置於四個插入件21'上。在一些實施例中，半導體裝置24可安置於兩個插入件21'上。半導體裝置24可安置於六個插入件21'上。半導體裝置24可安置於八個插入件21'上。
圖5A為根據本發明之一些實施例之半導體裝置封裝3的截面圖。半導體裝置封裝3包括基板30、插入件31、底填充料32、導電柱33、半導體裝置34、半導體裝置35、囊封物36、焊球37、互連381、互連382及環結構39。
基板30具有上表面30u及與上表面30u相對的下表面30b。插入件31安置於基板30之上表面30u上。環結構39安置於基板30之上表面30u上。環結構39鄰近於基板30之周邊而安置。環結構39環繞囊封物36及插入件31。焊球37安置於基板30之下表面30b上。環結構39提供防止彎曲問題之功能。在一些實施例中，環結構39可省略。
插入件31 (例如矽穿孔(TSV)插入件)包括導電通孔311及電端子312。插入件31經由電端子312電連接至基板30。插入件31之導電通孔311的大小(例如高度、寬度或直徑)小於導電柱33之大小。
導電柱33安置於基板30之上表面30u上。導電柱33安置於插入件31之間。導電柱33係由插入件31環繞。導電柱33可用作接地路徑或電力路徑。導電柱33之寬度不同於導電通孔311之寬度。導電柱33之寬度大於導電通孔311之寬度。導電柱33之高度大於導電通孔311之高度。導電柱33之寬度足夠大以防止由大電流引起的短路問題。導電柱33之縱橫比大於7。導電柱33之大小可基於所要設計而調整。
囊封物36安置於基板30之上表面30u上。囊封物36環繞插入件31。囊封物36環繞導電柱33。囊封物36囊封插入件31及導電柱33。囊封物36具有樹脂材料。囊封物36具有填料。囊封物36中不存在空隙。
互連381安置於囊封物36中。互連382安置於囊封物36中。互連381將插入件31電連接至半導體裝置34。互連382將插入件31電連接至半導體裝置35。互連381之寬度可不同於互連382之寬度。互連381之寬度可大於互連382之寬度。互連381之寬度可小於互連382之寬度。互連381之寬度可與互連382之寬度相同。互連382環繞互連381。
半導體裝置34安置於插入件31上。半導體裝置34安置於導電柱33上。半導體裝置34包括導電襯墊341及導電襯墊342。導電襯墊341經由互連381電連接至插入件31之導電通孔311。導電結構332安置於導電襯墊341與互連381之間。導電結構332電連接導電襯墊341及互連381。導電襯墊342電連接至導電柱33。導電結構331安置於導電襯墊342與導電柱33之間。導電結構331電連接導電襯墊342及導電柱33。半導體裝置34經由插入件31電連接至基板30。半導體裝置34經由導電柱33電連接至基板30。導電襯墊342可為接地襯墊。在一些實施例中，半導體裝置34可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，該導電結構331及該導電結構332可為焊料凸塊或銅柱凸塊。
半導體裝置35安置於插入件31上。半導體裝置35安置於導電柱33上。半導體裝置35包括導電襯墊351。導電襯墊351經由互連382電連接至插入件31之導電通孔311。半導體裝置35經由插入件31電連接至基板30。導電結構333安置於導電襯墊351與互連382之間。導電結構333電連接導電襯墊351及互連382。半導體裝置34及半導體裝置35可經由插入件31彼此連通。在一些實施例中，半導體裝置35可為高頻寬記憶體(HBM)。在一些實施例中，導電結構333及導電可為焊料凸塊或銅柱凸塊。
底填充料32安置於囊封物36上。底填充料32可安置於半導體裝置34與囊封物36之間。底填充料32可安置於半導體裝置35與囊封物36之間。底填充料32可環繞導電襯墊341及導電襯墊342。底填充料32可環繞導電襯墊351。
圖5B為根據本發明之一些實施例之半導體裝置封裝3的俯視圖。插入件31、半導體裝置34、半導體裝置35及環結構39安置於基板30上。四個插入件31環繞導電柱33(圖5B中未展示)。環結構39環繞插入件31。半導體裝置34安置於插入件31上。半導體裝置35安置於插入件31上。由於插入件31之導電通孔311的大小(例如寬度或直徑)可足夠小，所以插入件31之面積可降低。因此，半導體裝置封裝3之成本可降低。
半導體裝置34可安置於四個插入件31上。在一些實施例中，半導體裝置34可安置於兩個插入件31上。半導體裝置34可安置於六個插入件31上。半導體裝置34可安置於八個插入件31上。
圖6A為根據本發明之一些實施例之半導體裝置封裝3'的截面圖。半導體裝置封裝3'包括基板30、插入件31'、底填充料32、導電柱33'a、導電柱33'b、半導體裝置34、半導體裝置35、囊封物36、焊球37、互連381、互連382及環結構39。
基板30具有上表面30u及與上表面30u相對的下表面30b。插入件31'可不具有導電通孔。插入件31'經由黏著劑313'安置於基板30之上表面30u上。環結構39安置於基板30之上表面30u上。環結構39鄰近於基板30之周邊而安置。環結構39環繞囊封物36及插入件31'。焊球37安置於基板30之下表面30b上。環結構39提供防止彎曲問題之功能。在一些實施例中，環結構39可省略。
導電柱33'a安置於基板30之上表面30u上。導電柱33'b安置於基板30之上表面30u上。導電柱33'a安置於插入件31'之間。導電柱33'a由插入件31'環繞。導電柱33'b鄰近於囊封物36之周邊而安置。導電柱33'a或33'b可用作接地路徑或電力路徑。導電柱33'a之大小(例如寬度、直徑或高度)可不同於導電柱33'b之大小。導電柱33'a之大小可與導電柱33'b之大小相同。導電柱33'a或33'b之寬度足夠大以防止由大電流引起的短路問題。導電柱33'a或33'b之縱橫比大於7。導電柱33'a或33'b之大小可基於所要設計而調整。在一些實施例中，導電柱33'b可由導電柱33'a替換。
囊封物36安置於基板30之上表面30u上。囊封物36環繞插入件31'。囊封物36環繞導電柱33'a。囊封物36環繞導電柱33'b。囊封物36囊封插入件31'、導電柱33'a及導電柱33'b。囊封物36具有樹脂材料。囊封物36具有填料。囊封物36中不存在空隙。
互連381安置於囊封物36中。互連382安置於囊封物36中。互連381將插入件31'電連接至半導體裝置34。互連382將插入件31'電連接至半導體裝置35。互連381之寬度可不同於互連382之寬度。互連381之寬度可大於互連382之寬度。互連381之寬度可小於互連382之寬度。互連381之寬度可與互連382之寬度相同。互連382環繞互連381。
半導體裝置34安置於囊封物36上。半導體裝置34安置於插入件31'上。半導體裝置34安置於導電柱33'a上。半導體裝置34包括導電襯墊341及導電襯墊342。導電襯墊341經由互連381電連接至插入件31之導電通孔311。導電結構332安置於導電襯墊341與互連381之間。導電結構332電連接導電襯墊341及互連381。導電襯墊342電連接至導電柱33'a。導電結構331安置於導電襯墊342與導電柱33'a之間。導電結構331電連接導電襯墊342及導電柱33'a。半導體裝置34經由導電柱33'a電連接至基板30。導電襯墊342可為接地襯墊。在一些實施例中，半導體裝置34可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，該導電結構331及該導電結構332可為焊料凸塊或銅柱凸塊。
半導體裝置35安置於囊封物36上。半導體裝置35安置於插入件31'上。半導體裝置35安置於導電柱33'b上。半導體裝置35包括導電襯墊351及導電襯墊352。導電襯墊351經由互連382電連接至插入件31之導電通孔311。導電結構333安置於導電襯墊351與互連382之間。導電結構333電連接導電襯墊351及互連382。半導體裝置35經由導電襯墊352電連接至導電柱33'b。導電結構333安置於導電襯墊352與導電柱33'b之間。導電結構333電連接導電襯墊351及導電柱33'b。半導體裝置35經由導電柱33'b電連接至基板30。導電襯墊352可為接地襯墊。半導體裝置34及半導體裝置35可經由插入件31'彼此連通。在一些實施例中，半導體裝置35可為高頻寬記憶體(HBM)。
底填充料32安置於囊封物36上。底填充料32可安置於半導體裝置34與囊封物36之間。底填充料32可安置於半導體裝置35與囊封物36之間。底填充料32可環繞導電襯墊341及導電襯墊342。底填充料32可環繞導電襯墊351。
圖6B為根據本發明之一些實施例之半導體裝置封裝3'的俯視圖。插入件31'、半導體裝置34、半導體裝置35及環結構39安置於基板30上。四個插入件31'環繞導電柱33'a (圖6B中未展示)。環結構39環繞插入件31'。半導體裝置34安置於插入件31'上。半導體裝置35安置於插入件31'上。由於插入件31'可不具有導電通孔，所以插入件31'之面積可儘可能小地降低。因此，半導體裝置封裝3'之成本可降低。
半導體裝置34可安置於四個插入件31'上。在一些實施例中，半導體裝置34可安置於兩個插入件31'上。半導體裝置34可安置於六個插入件31'上。半導體裝置34可安置於八個插入件31'上。
圖7A至圖7F說明根據本發明之一些實施例之製造半導體裝置封裝1的方法之一些實施例。
參看圖7A，用於製造半導體裝置封裝1之方法包括提供具有上表面10u及下表面10b之基板10。導電柱13安置於基板10之上表面10u上。導電柱13電連接至基板10。導電柱13可為預先形成之固體柱/柱子。導電柱13之大小(例如寬度、直徑或高度)可經調整。導電柱13之縱橫比大於7。導電柱13可用作接地路徑或電力路徑。導電柱13之寬度足夠大以防止由大電流引起的短路問題。
參看圖7B，具有導電通孔111及電端子112之插入件11 (例如矽穿孔(TSV)插入件)安置於基板10之上表面10u上。底填充料12安置於基板10與插入件11之間。傳導柱13係由插入件11環繞。
導電柱13之大小大於導電通孔111之大小。導電柱13之寬度大於導電通孔111之寬度。導電柱13之高度大於導電通孔111之高度。插入件11中不存在接地導電通孔(其具有相對較大寬度)。由於插入件11之導電通孔111的大小(例如寬度或直徑)可足夠小，所以插入件11之面積可降低。導電柱13可包括焊接點131。
參看圖7C，半導體裝置14安置於插入件11上。半導體裝置14安置於導電柱13上。半導體裝置14包括導電襯墊141及導電襯墊142。導電襯墊141經由導電結構143電連接至插入件11之導電通孔111。導電結構143可包括接觸插入件11之導電通孔111的焊接點1431。導電襯墊142電連接至導電柱13之焊接點131。半導體裝置14經由插入件11電連接至基板10。在一些實施例中，半導體裝置14可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，導電結構143可為焊料凸塊或銅柱凸塊。
半導體裝置15安置於插入件11上。半導體裝置15包括導電襯墊151。半導體裝置15經由導電襯墊151電連接至插入件11。導電襯墊151經電連接至導電結構153。導電結構153可包括接觸插入件11之導電通孔111的焊接點1531。半導體裝置15經由插入件11電連接至基板10。半導體裝置14及半導體裝置15可經由插入件11彼此連通。在一些實施例中，半導體裝置15可為高頻寬記憶體(HBM)。在一些實施例中，導電結構153可為焊料凸塊或銅柱凸塊。
參看圖7D，底填充料12安置於插入件11與半導體裝置15之間以保護半導體裝置15的導電襯墊151。
參看圖7E，囊封物16安置於基板10之上表面10u上以囊封插入件11、導電柱13、半導體裝置14及半導體裝置15。囊封物16環繞導電柱13及插入件11。半導體裝置14之上表面係由囊封物16曝露。囊封物16具有樹脂材料。囊封物16具有填料。
在一些實施例中，由於插入件11與半導體裝置14之間的距離較小且導電襯墊141密集，所以囊封物16可不能夠完全進入基板10、插入件11及半導體裝置14之間的空間，此導致囊封物16中存在一些空隙。空隙位於插入件11與半導體裝置14之間。空隙位於插入件11、導電柱13及半導體裝置14之間。
參看圖7F，環結構19安置於基板10之上表面10u上。隨後，焊球17安置於基板10之下表面10b上。環結構19提供防止彎曲問題之功能。在一些實施例中，環結構19可省略。隨後，可執行單粒化操作。
圖8A至圖8E說明根據本發明之一些實施例之製造半導體裝置封裝1'的方法之一些實施例。
參看圖8A，用於製造半導體裝置封裝1'之方法包括提供具有上表面10u及下表面10b之基板10。導電柱13'a安置於基板10之上表面10u上。導電柱13'a電連接至基板10。導電柱13'b安置於基板10之上表面10u上。導電柱13'b電連接至基板10。導電柱13'a鄰近於基板10之中心部分而安置。導電柱13'b鄰近於基板10之周邊部分而安置。導電柱13'a或13'b可為預先形成之固體柱/柱子。
導電柱13'a或13'b之大小(例如高度、寬度或直徑)可經調整。導電柱13'a之大小可與導電柱13'b之大小相同。導電柱13'a之大小可不同於導電柱13'b之大小。導電柱13'a或13'b之縱橫比大於7。導電柱13'a或13'b可用作接地路徑或電力路徑。導電柱13'a或13'b之寬度足夠大以防止由大電流引起的短路問題。導電柱13'a可包括焊接點13'a1。導電柱13'b可包括焊接點13'b1。
參看圖8B，插入件11'安置於基板10之上表面10u上。插入件11'經由黏著劑113'附接至基板10。插入件11'安置於導電柱13'a與導電柱13'b之間。插入件11'可不具有導電通孔。由於插入件11'可不具有導電通孔，所以插入件11'之面積可儘可能小地降低。因此，半導體裝置封裝1'之成本可降低。
參看圖8C，半導體裝置14安置於插入件11'上。半導體裝置14安置於導電柱13'a上。半導體裝置14包括導電襯墊141及導電襯墊142。導電襯墊141經由導電結構143電連接至插入件11'。導電結構143可包括接觸插入件11'之焊接點1431。導電襯墊142電連接至導電柱13'a。導電襯墊142可接觸導電柱13'a之焊接點13'a1。半導體裝置14經由導電柱13'a電連接至基板10。導電襯墊142可為接地襯墊。在一些實施例中，半導體裝置14可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。
半導體裝置15安置於插入件11'上。半導體裝置15安置於導電柱13'b上。半導體裝置15包括導電襯墊151及導電襯墊152。半導體裝置15經由導電襯墊151電連接至插入件11'。導電襯墊151電連接至導電結構153。導電結構153可包括接觸插入件11'之焊接點1531。半導體裝置15經由導電襯墊152電連接至導電柱13'b。導電襯墊152可接觸導電柱13'b之焊接點13'b1。半導體裝置15經由導電柱13'b電連接至基板10。導電襯墊152可為接地襯墊。半導體裝置14及半導體裝置15可經由插入件11'彼此連通。在一些實施例中，半導體裝置15可為高頻寬記憶體(HBM)。在一些實施例中，導電結構153可為焊料凸塊或銅柱凸塊。
參看圖8D，囊封物16安置於基板10之上表面10u上以囊封插入件11'、導電柱13'a、導電柱13'b、半導體裝置14及半導體裝置15。囊封物16環繞導電柱13'a、導電柱13'b及插入件11'。半導體裝置14之上表面由囊封物16曝露。囊封物16具有樹脂材料。囊封物16具有填料。
在一些實施例中，由於插入件11'與半導體裝置14之間的距離較小且導電襯墊141密集，所以囊封物16可不能夠完全進入基板10、插入件11'及半導體裝置14之間的空間，此導致囊封物16中存在一些空隙。空隙位於插入件11'與半導體裝置14之間。空隙位於插入件11'、導電柱13'a及半導體裝置14之間。
參看圖8E，環結構19安置於基板10之上表面10u上。隨後，焊球17安置於基板10之下表面10b上。環結構19提供防止彎曲問題之功能。在一些實施例中，環結構19可省略。隨後，可執行單粒化操作。
圖9A至圖9I說明根據本發明之一些實施例之製造半導體裝置封裝2的方法之一些實施例。
參看圖9A，用於製造半導體裝置封裝2之方法包括提供具有黏著劑91之載體90。半導體裝置24經由黏著劑91安置於載體90上。半導體裝置24包括導電襯墊241及導電襯墊242。導電襯墊242可為接地襯墊。導電結構243安置於導電襯墊241上。導電結構243可包括焊接點2431。在一些實施例中，半導體裝置24可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。
導電柱23安置於半導體裝置24之主動區域上。導電柱23可用作接地路徑或電力路徑。導電柱23之縱橫比大於7。導電柱23之大小(例如高度、寬度或直徑)可基於所要設計而調整。導電柱23可為預先形成之固體柱/柱子。導電柱23可包括焊接點231。
半導體裝置25經由黏著劑91安置於載體90上。半導體裝置25包括導電襯墊251。導電結構253安置於導電襯墊251上。導電結構253可包括焊接點2531。在一些實施例中，半導體裝置25可為高頻寬記憶體(HBM)。
參看圖9B，插入件21 (例如矽穿孔(TSV)插入件)安置於半導體裝置24之主動區域上。插入件21經由導電襯墊241電連接至半導體裝置24。插入件21安置於半導體裝置25之主動區域上。插入件21經由導電襯墊251電連接至半導體裝置25。半導體裝置24及半導體裝置25通過插入件21彼此連通。插入件21環繞導電柱23。插入件21包括導電通孔211及電端子212。導電通孔211之大小(例如高度、寬度或直徑)小於導電柱23之大小。
參看圖9C，囊封物26提供在載體90及黏著劑91上以囊封插入件21、導電柱23、半導體裝置24及半導體裝置25。囊封物26環繞插入件21及導電柱23。
由於插入件21、導電柱23、半導體裝置24及半導體裝置25以反轉形式模製，所以囊封物26中不存在空隙。
參看圖9D，囊封物26藉由研磨操作研磨以曝露插入件21之電端子212及導電柱23。插入件21之電端子212及導電柱23可在研磨操作期間被研磨。插入件21之電端子212及導電柱23係由囊封物26曝露。
參看圖9E，電連接28安置於囊封物26上。電連接28電連接至插入件21之電端子212。電連接28電連接至導電柱23。電連接28可為凸塊。
參看圖9F，載體90及黏著劑91被移除。半導體裝置24之上表面係由囊封物26曝露。
參看圖9G，單粒化操作經執行以形成子模組92。子模組92包括插入件21、導電柱23、半導體裝置24、半導體裝置25、囊封物26及電連接28。
參看圖9H，子模組92安置於基板20之上表面20u上。子模組92電連接至基板20。半導體裝置24經由插入件21電連接至基板20。半導體裝置24經由導電柱23電連接至基板20。半導體裝置25經由插入件21電連接至基板20。
參看圖9I，底填充料22安置於基板20與囊封物26之間。電連接28係由底填充料22環繞。底填充料22環繞囊封物26。接著，環結構29安置於基板20之上表面20u上。環結構29環繞囊封物26及插入件21。隨後，焊球27安置於基板20之下表面20b上。環結構29提供防止彎曲問題之功能。在一些實施例中，環結構29可省略。
在一些實施例中，在製造半導體裝置封裝2中存在晶粒丟失之風險。由於插入件21、半導體裝置24及半導體裝置25係在提供基板20之前經模製，所以若插入件21與經模製半導體裝置24及25之間的電連接不良，則經模製半導體裝置24及25將被廢棄。
圖10A至圖10H說明根據本發明之一些實施例之製造半導體裝置封裝2'的方法之一些實施例。
參看圖10A，用於製造半導體裝置封裝2'之方法包括提供具有黏著劑91之載體90。半導體裝置24經由黏著劑91安置於載體90上。半導體裝置24包括導電襯墊241及導電襯墊242。導電結構243安置於導電襯墊241上。導電結構243可包括焊接點2431。導電襯墊242可為接地襯墊。在一些實施例中，半導體裝置24可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。
導電柱23'a安置於半導體裝置24之主動區域上。導電柱23'a鄰近於載體90之中心區域。導電柱23'a可用作接地路徑或電力路徑。導電柱23'a之縱橫比大於7。導電柱23'a之大小(例如高度、寬度或直徑)可基於所要設計而調整。導電柱23'a可為預先形成之固體柱/柱子。導電柱23'a可包括焊接點23'a1。導電柱23'b可包括焊接點23'b1。
半導體裝置25經由黏著劑91安置於載體90上。半導體裝置25包括導電襯墊251及導電襯墊252。導電結構253安置於導電襯墊251上。導電結構253可包括焊接點2531。導電襯墊252可為接地襯墊。在一些實施例中，半導體裝置25可為高頻寬記憶體(HBM)。
導電柱23'b安置於半導體裝置25之主動區域上。導電柱23'b鄰近於載體90之周邊區域。導電柱23'b可用作接地路徑或電力路徑。導電柱23'b之縱橫比大於7。導電柱23'b之大小(例如，高度、寬度或直徑)可基於所要設計而調整。導電柱23'a之大小可與導電柱23'b之大小相同。導電柱23'a之大小可不同於導電柱23'b之大小。導電柱23'b可為預先形成之固體柱/柱子。
參看圖10B，插入件21'安置於半導體裝置24之主動區域上。插入件21'經由導電襯墊241電連接至半導體裝置24。插入件21'安置於半導體裝置25之主動區域上。插入件21'經由導電襯墊251電連接至半導體裝置25。半導體裝置24及半導體裝置25通過插入件21'彼此連通。插入件21'環繞導電柱23'a。插入件21'可不具有導電通孔。由於插入件21'可不具有導電通孔，所以插入件21'之面積可儘可能小地降低。因此，半導體裝置封裝2'之成本可降低。
參看圖10C，囊封物26經提供於載體90及黏著劑91上以囊封插入件21'、導電柱23'a、導電柱23'b、半導體裝置24及半導體裝置25。囊封物26環繞插入件21'、導電柱23'a及導電柱23b。
由於插入件21、導電柱23'a、導電柱23'b、半導體裝置24及半導體裝置25係以反轉形式模製，所以囊封物26中不存在空隙。
參看圖10D，囊封物26係藉由研磨操作研磨以曝露導電柱23'a及導電柱23'b。導電柱23'a及導電柱23'b可在研磨操作期間被研磨。導電柱23'a及導電柱23'b係由囊封物26曝露。
在研磨操作之後，導電柱23'b之大小(例如高度、寬度或直徑)可與導電柱23'a之大小相同。導電柱23'b之大小(例如高度、寬度或直徑)可不同於導電柱23'a之大小。
參看圖10E，電連接28安置於囊封物26上。電連接28電連接至導電柱23'a。電連接28電連接至導電柱23'b。電連接28可為凸塊。
隨後，載體90及黏著劑91被移除。半導體裝置24之上表面係由囊封物26曝露。
參看圖10F，單粒化操作經執行以形成子模組92'。子模組92'包括插入件21'、導電柱23'a、導電柱23'b、半導體裝置24、半導體裝置25、囊封物26及電連接28。
參看圖10G，子模組92'安置於基板20之上表面20u上。子模組92'電連接至基板20。半導體裝置24經由導電柱23'a電連接至基板20。半導體裝置25經由導電柱23'b電連接至基板20。
參看圖10H，底填充料22安置於基板20與囊封物26之間。電連接28係由底填充料22環繞。底填充料22環繞囊封物26。環結構29安置於基板20之上表面20u上。接著，環結構29環繞囊封物26及插入件21' 隨後，焊球27安置於基板20之下表面20b上。環結構29提供防止彎曲問題之功能。在一些實施例中，環結構29可省略。
在一些實施例中，在製造半導體裝置封裝2'中存在晶粒丟失之風險。由於插入件21'、半導體裝置24及半導體裝置25係在提供基板20之前被模製，所以若插入件21'與經模製半導體裝置24及25之間的電連接不良，則經模製半導體裝置24及25將被廢棄。
圖11A至圖11H說明根據本發明之一些實施例之製造半導體裝置封裝3的方法之一些實施例。
參看圖11A，用於製造半導體裝置封裝3之方法包括提供具有上表面30u及下表面30b之基板30。導電柱33安置於基板30之上表面30u上。導電柱33電連接至基板30。導電柱33可為預先形成之固體柱/柱子。導電柱33之大小(例如高度、寬度或直徑)可經調整。導電柱33之縱橫比大於7。導電柱33可用作接地路徑或電力路徑。導電柱33之寬度足夠大以防止由大電流引起的短路問題。
參看圖11B，具有導電通孔311及電端子312之插入件31 (例如矽穿孔(TSV)插入件)安置於基板30之上表面30u上。傳導柱33係由插入件31環繞。
導電柱33之大小大於導電通孔311之大小。導電柱33之寬度大於導電通孔311之寬度。導電柱33之高度大於導電通孔311之高度。插入件31中不存在接地導電通孔(其具有相對較大寬度)。由於插入件31之導電通孔311之大小(例如，寬度或直徑)可足夠小，所以插入件31之面積可降低。
參看圖11C，囊封物36安置於基板30之上表面30u上。囊封物36環繞插入件31及導電柱33。囊封物36囊封插入件31及導電柱33。囊封物36具有樹脂材料。囊封物36具有填料。囊封物36中不存在空隙。
參看圖11D，通孔36a及通孔36b藉由雷射鑽孔操作形成於囊封物36中。通孔36a之大小(例如，深度、寬度或直徑)可與通孔36b之大小相同。通孔36a之大小可不同於通孔36b之大小。
參看圖11E，互連381係藉由金屬電鍍操作形成於通孔36a中。互連382係藉由金屬電鍍操作形成於通孔36b中。
參看圖11F，囊封物36係藉由研磨操作而研磨。互連381及互連382係藉由研磨操作而研磨。
參看圖11G，半導體裝置34安置於插入件31上。半導體裝置34安置於導電柱33上。半導體裝置34安置於囊封物36上。底填充料32安置於半導體裝置34與囊封物36之間。半導體裝置34包括導電襯墊341及導電襯墊342。導電襯墊341經由導電襯墊341及互連381電連接至插入件31之導電通孔311。導電結構332安置於導電襯墊341與互連381之間。導電結構332電連接導電襯墊341及互連381。導電襯墊342電連接至導電柱33。導電結構331安置於導電襯墊342與導電柱33之間。導電結構331電連接導電襯墊342及導電柱33。導電襯墊342可為接地襯墊。半導體裝置34經由導電柱33電連接至基板30。半導體裝置34經由插入件31電連接至基板30。在一些實施例中，半導體裝置34可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，該導電結構331及該導電結構332可為焊料凸塊或銅柱凸塊。
半導體裝置35安置於插入件31上。半導體裝置35安置於囊封物36上。底填充料32安置於半導體裝置35與囊封物36之間。半導體裝置35包括導電襯墊351。導電襯墊351經由互連382電連接至插入件31。導電結構333安置於導電襯墊351與互連382之間。導電結構333電連接導電襯墊351及互連382。半導體裝置35經由插入件31電連接至基板30。半導體裝置34及半導體裝置35可經由插入件31彼此連通。在一些實施例中，半導體裝置35可為高頻寬記憶體(HBM)。在一些實施例中，導電結構333及導電可為焊料凸塊或銅柱凸塊。
參看圖11H，環結構39安置於基板30之上表面10u上。隨後，焊球37安置於基板30之下表面30b上。環結構39提供防止彎曲問題之功能。在一些實施例中，環結構39可省略。隨後，可執行單粒化操作。
圖12A至圖12H說明根據本發明之一些實施例之製造半導體裝置封裝3'的方法之一些實施例。
參看圖12A，用於製造半導體裝置封裝3'之方法包括提供具有上表面30u及下表面30b之基板30。導電柱33'a安置於基板30之上表面30u上。導電柱33'a電連接至基板30。導電柱33'b安置於基板30之上表面30u上。導電柱33'b電連接至基板30。導電柱33'a鄰近於基板30之中心部分而安置。導電柱33'b鄰近於基板30之周邊部分而安置。導電柱33'a或33'b可為預先形成之固體柱/柱子。
導電柱33'a或33'b之大小(例如，高度、寬度或直徑)可經調整。導電柱33'a之大小可與導電柱33'b之大小相同。導電柱33'a之大小可不同於導電柱33'b之大小。導電柱33'a或33'b之縱橫比大於7。導電柱33'a或33'b可用作接地路徑或電力路徑。導電柱33'a或33'b之寬度足夠大以防止由大電流引起的短路問題。
參看圖12B，插入件31'安置於基板30之上表面30u上。插入件31'經由黏著劑313'附接至基板30。插入件31'安置於導電柱33'a與導電柱33'b之間。插入件31'可不具有導電通孔。由於插入件31'可不具有導電通孔，所以插入件31'之面積可儘可能小地降低。因此，半導體裝置封裝3'之成本可降低。
參看圖12C，囊封物36安置於基板30之上表面30u上。囊封物36環繞插入件31'、導電柱33'a及導電柱33'b。囊封物36囊封插入件31'、導電柱33'a及導電柱33'b。囊封物36具有樹脂材料。囊封物36具有填料。囊封物36中不存在空隙。
參看圖12D，通孔36a及通孔36b藉由雷射鑽孔操作形成於囊封物36中。通孔36a之大小(例如，深度、寬度或直徑)可與通孔36b之大小相同。通孔36a之大小可不同於通孔36b之大小。
參看圖12E，互連381係藉由金屬電鍍操作形成於通孔36a中。互連382係藉由金屬電鍍操作形成於通孔36b中。
參看圖12F，囊封物36係藉由研磨操作而研磨。互連381及互連382係藉由研磨操作而研磨。
參看圖12G，半導體裝置34安置於插入件31上。半導體裝置34安置於導電柱33'a上。半導體裝置34安置於囊封物36上。底填充料32安置於半導體裝置34與囊封物36之間。半導體裝置34包括導電襯墊341及導電襯墊342。導電襯墊341經由互連381電連接至插入件31'。導電結構332安置於導電襯墊341與互連381之間。導電結構332電連接導電襯墊341及互連381。導電襯墊342電連接至導電柱33'a。導電結構331安置於導電襯墊342與導電柱33'a之間。導電結構331電連接導電襯墊342及導電柱33'a。導電襯墊342可為接地襯墊。半導體裝置34經由導電柱33'a電連接至基板30。在一些實施例中，半導體裝置34可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。在一些實施例中，該導電結構331及該導電結構332可為焊料凸塊或銅柱凸塊。
半導體裝置35安置於插入件31'上。半導體裝置35安置於囊封物36上。底填充料32安置於半導體裝置35與囊封物36之間。半導體裝置35包括導電襯墊351及導電襯墊352。導電襯墊351經由互連382電連接至插入件31'。導電結構333安置於導電襯墊351與互連382之間。導電結構333電連接導電襯墊351及互連382。半導體裝置35經由導電柱33'b電連接至基板30。導電結構333安置於導電襯墊352與導電柱33'b之間。導電結構333電連接導電襯墊351及導電柱33'b。半導體裝置34及半導體裝置35可經由插入件31'彼此連通。在一些實施例中，半導體裝置35可為高頻寬記憶體(HBM)。
參看圖12H，環結構39安置於基板30之上表面10u上。隨後，焊球37安置於基板30之下表面30b上。環結構39提供防止彎曲問題之功能。在一些實施例中，環結構39可省略。隨後，可執行單粒化操作。
圖13A為對比半導體裝置封裝4之截面圖。半導體裝置封裝4包括基板40、插入件41、底填充料42、半導體裝置44、半導體裝置45、焊球47及環結構49。
基板40具有上表面40u及與上表面40u相對的下表面40b。插入件41安置於基板40之上表面40u上。環結構49安置於基板40之上表面40u上。環結構49環繞插入件41。焊球47安置於基板40之下表面40b上。環結構49提供防止彎曲問題之功能。在一些實施例中，環結構49可省略。
插入件41 (例如矽穿孔(TSV)插入件)包括導電通孔411、電端子412及導電通孔413。插入件41經由電端子412電連接至基板40。底填充料42安置於基板40與插入件41之間。電端子412係由底填充料42環繞。
導電通孔413為接地通孔。導電通孔413之寬度大於導電通孔411之寬度。由於導電通孔411及導電通孔413之寬度彼此不同，所以難以均一地形成導電通孔411及導電通孔413，此致使較差良率。另外，插入件41之面積由於導電通孔413具有較大大小而難以降低。
半導體裝置44安置於插入件41上。底填充料42安置於插入件41與半導體裝置44之間。半導體裝置14包括導電襯墊441。導電襯墊441可電連接至導電通孔411。導電襯墊441可電連接至導電通孔413。半導體裝置44經由插入件41電連接至基板40。半導體裝置44可包括特殊應用積體電路(ASIC)、控制器、處理器或其他電子組件或半導體裝置。
半導體裝置45安置於插入件41上。底填充料42安置於插入件41與半導體裝置45之間。半導體裝置45包括導電襯墊451。導電襯墊451可電連接至導電通孔411。導電襯墊451可電連接至導電通孔413。半導體裝置45經由插入件41電連接至基板40。半導體裝置44及半導體裝置45可經由插入件41彼此連通。半導體裝置15可為高頻寬記憶體(HBM)。
圖13B為根據本發明之一些實施例之半導體裝置封裝4的俯視圖。插入件41、半導體裝置44、半導體裝置45及環結構49安置於基板40上。環結構49環繞插入件41。半導體裝置44及半導體裝置15兩者均安置於插入件41上。由於半導體裝置44及半導體裝置15兩者均安置於一個插入件上，所以插入件41之面積必須足夠大以容納半導體裝置44及半導體裝置45。因此，半導體裝置封裝4之成本難以降低。
圖14為對比半導體裝置封裝5之截面圖。半導體裝置封裝5包括基板50、插入件52、半導體裝置54及半導體裝置56。
插入件52安置於基板50上。插入件52包括導電襯墊521及導電柱522。導電柱522電連接至基板50之導電襯墊501。
半導體裝置54安置於基板50及插入件52上。半導體裝置54包括導電柱541及導電柱542。導電柱541電連接至導電襯墊501。導電柱542電連接至導電襯墊521。導電柱541之高度大於導電柱542之高度。
半導體裝置56安置於插入件52上。半導體裝置56包括導電柱561。導電柱561電連接至導電襯墊521。導電柱561之高度與導電柱542之高度相同。
由於導電柱522、導電柱541、導電柱542及導電柱561未由囊封物囊封，所以此等導電柱可在半導體裝置封裝5之製造期間坍塌或破裂。此類坍塌或破裂將引起隨後操作中之未對準及電斷開。
如本文中所使用且不另外定義，術語「實質上」、「實質性」、「大致」及「約」用以描述及解釋小變化。當與事件或情形結合使用時，術語可涵蓋事件或情形精確發生之情況以及事件或情形極近似於發生之情況。舉例而言，當結合數值使用時，術語可涵蓋小於或等於彼數值之±10%的變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%。術語「實質上共面」可指沿著同一平面處於微米內之兩個表面，諸如沿著同一平面處於40 μm內、30 μm內、20 μm內、10 μm內或1 μm內。
除非上下文另外明確規定，否則如本文所用，單數術語「一(a/an)」及「該」可包括複數個指示物。在對一些實施例之描述中，提供「在」另一組件「上」之組件可涵蓋前一組件直接在後一組件上(例如，與後一組件實體接觸)的狀況以及一或多個介入組件位於前一組件與後一組件之間的狀況。
儘管本發明已參看其特定實施例進行描述及說明，但此等描述及說明並不為限制性的。熟習此項技術者應理解，在不脫離如由所附申請專利範圍界定的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效物。說明可不必按比例繪製。歸因於製造程序及容限，本發明中之藝術再現與實際設備之間可存在區別。可存在並未特定說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可做出修改，以使特定情形、材料、物質組成、方法或程序適應於本發明之目標、精神及範疇。所有此類修改意欲在此處附加之申請專利範圍之範疇內。雖然已參考按特定次序執行之特定操作描述本文中所揭示的方法，但應理解，在不脫離本發明之教示的情況下，可組合、再細分，或重新定序此等操作以形成等效方法。因此，除非本文中特定指示，否則操作之次序及分組並非限制。
1‧‧‧半導體裝置封裝1'‧‧‧半導體裝置封裝2‧‧‧半導體裝置封裝2'‧‧‧半導體裝置封裝3‧‧‧半導體裝置封裝3'‧‧‧半導體裝置封裝4‧‧‧半導體裝置封裝5‧‧‧半導體裝置封裝10‧‧‧基板10b‧‧‧下表面10u‧‧‧上表面11‧‧‧插入件11'‧‧‧插入件12‧‧‧底填充料13‧‧‧導電柱13'a‧‧‧導電柱13'a1‧‧‧焊接點13'b‧‧‧導電柱13'b1‧‧‧焊接點14‧‧‧半導體裝置15‧‧‧半導體裝置16‧‧‧囊封物17‧‧‧焊球19‧‧‧環結構20‧‧‧基板20b‧‧‧下表面20u‧‧‧上表面21‧‧‧插入件21'‧‧‧插入件22‧‧‧底填充料23‧‧‧導電柱23'a‧‧‧導電柱23'a1‧‧‧焊接點23'b‧‧‧導電柱23'b1‧‧‧焊接點24‧‧‧半導體裝置25‧‧‧半導體裝置26‧‧‧囊封物27‧‧‧焊球28‧‧‧電連接29‧‧‧環結構30‧‧‧基板30b‧‧‧下表面30u‧‧‧上表面31‧‧‧插入件31'‧‧‧插入件32‧‧‧底填充料33‧‧‧導電柱33'a‧‧‧導電柱33'b‧‧‧導電柱34‧‧‧半導體裝置35‧‧‧半導體裝置36‧‧‧囊封物36a‧‧‧通孔36b‧‧‧通孔37‧‧‧焊球39‧‧‧環結構40‧‧‧基板40b‧‧‧下表面40u‧‧‧上表面41‧‧‧插入件42‧‧‧底填充料44‧‧‧半導體裝置45‧‧‧半導體裝置47‧‧‧焊球49‧‧‧環結構50‧‧‧基板52‧‧‧插入件54‧‧‧半導體裝置56‧‧‧半導體裝置90‧‧‧載體91‧‧‧黏著劑92‧‧‧子模組92'‧‧‧子模組111‧‧‧導電通孔112‧‧‧電端子113'‧‧‧黏著劑131‧‧‧焊接點141‧‧‧導電襯墊142‧‧‧導電襯墊143‧‧‧導電結構151‧‧‧導電襯墊152‧‧‧導電襯墊153‧‧‧導電結構211‧‧‧導電通孔212‧‧‧電端子231‧‧‧焊接點241‧‧‧導電襯墊242‧‧‧導電襯墊243‧‧‧導電結構251‧‧‧導電襯墊252‧‧‧導電襯墊253‧‧‧導電結構311‧‧‧導電通孔312‧‧‧電端子313'‧‧‧黏著劑331‧‧‧導電結構332‧‧‧導電結構333‧‧‧導電結構341‧‧‧導電襯墊342‧‧‧導電襯墊351‧‧‧導電襯墊352‧‧‧導電襯墊381‧‧‧互連382‧‧‧互連411‧‧‧導電通孔412‧‧‧電端子441‧‧‧導電襯墊451‧‧‧導電襯墊501‧‧‧導電襯墊521‧‧‧導電襯墊522‧‧‧導電柱541‧‧‧導電柱542‧‧‧導電柱561‧‧‧導電柱1431‧‧‧焊接點1531‧‧‧焊接點2431‧‧‧焊接點2531‧‧‧焊接點
圖1A說明根據本發明之一些實施例之半導體裝置封裝的截面圖。 圖1B說明根據本發明之一些實施例之半導體裝置封裝的俯視圖。 圖2A說明根據本發明之一些實施例之半導體裝置封裝的截面圖。 圖2B說明根據本發明之一些實施例之半導體裝置封裝的俯視圖。 圖3A說明根據本發明之一些實施例之半導體裝置封裝的截面圖。 圖3B說明根據本發明之一些實施例之半導體裝置封裝的俯視圖。 圖4A說明根據本發明之一些實施例之半導體裝置封裝的截面圖。 圖4B說明根據本發明之一些實施例之半導體裝置封裝的俯視圖。 圖5A說明根據本發明之一些實施例之半導體裝置封裝的截面圖。 圖5B說明根據本發明之一些實施例之半導體裝置封裝的俯視圖。 圖6A說明根據本發明之一些實施例之半導體裝置封裝的截面圖。 圖6B說明根據本發明之一些實施例之半導體裝置封裝的俯視圖。 圖7A說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖7B說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖7C說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖7D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖7E說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖7F說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖8A說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖8B說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖8C說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖8D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖8E說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9A說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9B說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9C說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9E說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9F說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9G說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9H說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖9I說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10A說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10B說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10C說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10E說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10F說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10G說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖10H說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11A說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11B說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11C說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11E說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11F說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11G說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖11H說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12A說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12B說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12C說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12D說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12E說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12F說明根據本發明之一些實施例的製造半導體裝置封裝之方法。 圖12G說明根據本發明之一些實施例之製造半導體裝置封裝的方法。 圖12H說明根據本發明之一些實施例之製造半導體裝置封裝的方法。 圖13A說明對比半導體裝置封裝的截面圖。 圖13B說明對比半導體裝置封裝的俯視圖。 圖14說明對比半導體裝置封裝的截面圖。
1‧‧‧半導體裝置封裝
10‧‧‧基板
10b‧‧‧下表面
10u‧‧‧上表面
11‧‧‧插入件
12‧‧‧底填充料
13‧‧‧導電柱
14‧‧‧半導體裝置
15‧‧‧半導體裝置
16‧‧‧囊封物
17‧‧‧焊球
19‧‧‧環結構
111‧‧‧導電通孔
112‧‧‧電端子
131‧‧‧焊接點
141‧‧‧導電襯墊
142‧‧‧導電襯墊
143‧‧‧導電結構
151‧‧‧導電襯墊
153‧‧‧導電結構
1431‧‧‧焊接點
1531‧‧‧焊接點

Claims (15)

  1. 一種半導體裝置封裝，其包含：一基板；一插入件，其安置於該基板上；一導電柱，其安置於該基板上；一第一半導體裝置，其安置於該插入件上並電連接至該導電柱，該第一半導體裝置包括電連接至該插入件之一導電襯墊；一第二半導體裝置，其安置於該插入件上，該第二半導體裝置包括電連接至該插入件之一導電襯墊；及一囊封物，其環繞該導電柱其中該導電柱係直接接觸該基板及該第一半導體裝置，且其中該插入件包括一導電通孔並電連接至該基板，且其中該導電通孔之一寬度小於該導電柱之一寬度。
  2. 如請求項1之半導體裝置封裝，其中該囊封物環繞該插入件、該第一半導體裝置及該第二半導體裝置。
  3. 如請求項1之半導體裝置封裝，其中該囊封物囊封該插入件並曝露該第一半導體裝置及該第二半導體裝置。
  4. 如請求項1之半導體裝置封裝，其中該導電柱之一縱橫比大於7。
  5. 如請求項1之半導體裝置封裝，其中該第一半導體裝置包括一接地導電襯墊，且其中該第一半導體裝置之該接地導電襯墊電連接至該導電柱。
  6. 如請求項5之半導體裝置封裝，其進一步包含一第二導電柱，其中該第二導電柱電連接至該第二半導體裝置之一接地襯墊。
  7. 如請求項5之半導體裝置封裝，其進一步包含安置於該插入件與該基板之間的一黏著劑。
  8. 如請求項7之半導體裝置封裝，其中該囊封物環繞該黏著劑。
  9. 如請求項5之半導體裝置封裝，其進一步包含安置於該導電柱與該基板之間的一連接元件。
  10. 如請求項1之半導體裝置封裝，其進一步包含安置於該基板上之一環結構，其中該環結構環繞該囊封物及該插入件。
  11. 一種用於製造一半導體裝置封裝之方法，其包含：提供一基板、一第一半導體裝置及一第二半導體裝置；提供一插入件以用於將該第一半導體裝置及該第二半導體裝置電連接至該基板；提供電連接至該基板及該第一半導體裝置之一第一導電柱，該第一導電柱係直接接觸該基板及該第一半導體裝置；及 提供一囊封物以環繞該第一導電柱及該插入件，其中提供電連接至該基板及該第一半導體裝置的該第一導電柱進一步包含：將該第一導電柱安置於該基板上；及將該第一半導體裝置安置於該第一導電柱上，其中該第一半導體裝置電連接至該第一導電柱，且其中提供該囊封物以環繞該第一導電柱及該插入件係在將該第一半導體裝置安置於該第一導電柱上之前。
  12. 如請求項11之方法，其進一步包含：安置電連接至該基板及該第二半導體裝置的一第二導電柱。
  13. 如請求項11之方法，其進一步包含：在該囊封物中形成一第一互連及一第二互連，該第一互連及該第二互連電連接至該插入件；研磨該囊封物以曝露該第一導電柱；將該第一半導體裝置電連接至該第一互連；及將該第二半導體裝置電連接至該第二互連。
  14. 如請求項11之方法，其中提供電連接至該基板及該第一半導體裝置的該第一導電柱進一步包含：將該第一半導體裝置及該第二半導體裝置安置於一載體上，該第一導電柱安置於該第一半導體裝置上；將該插入件安置於該第一半導體裝置及該第二半導體裝置上；提供該囊封物以環繞該第一半導體裝置及該第二半導體裝置； 研磨該囊封物以曝露該第一導電柱以形成一子模組；自該子模組移除該載體；及將該子模組安置於該基板上，該第一導電柱電連接至該基板。
  15. 如請求項14之方法，其進一步包含：安置電連接至該基板及該第二半導體裝置的一第二導電柱。
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