TWI713086B - 積體電路結構的形成方法和半導體結構 - Google Patents
積體電路結構的形成方法和半導體結構 Download PDFInfo
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- TWI713086B TWI713086B TW108124820A TW108124820A TWI713086B TW I713086 B TWI713086 B TW I713086B TW 108124820 A TW108124820 A TW 108124820A TW 108124820 A TW108124820 A TW 108124820A TW I713086 B TWI713086 B TW I713086B
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Abstract
本發明實施例提供製造半導體結構的方法。此方法包含在半導體基底上形成複合應力層,其中複合應力層的形成包含形成具有第一壓縮應力的介電材料之第一應力層和形成具有第二壓縮應力的介電材料之第二應力層在第一應力層上,第二壓縮應力大於第一壓縮應力,以及使用複合應力層作為蝕刻遮罩,圖案化半導體基底以形成鰭片主動區。
Description
本發明實施例係有關於半導體製造技術,且特別有關於鰭式場效電晶體的形成方法及其結構。
積體電路(integrated circuit,IC)已經發展到具有更小部件尺寸,例如16nm、9nm和7nm的先進技術。在這些先進技術中,裝置(例如電晶體)縮小並因此而引起各種問題,例如閘極接點的橋接(bridging concern)問題。此外,提高裝置效能通常需要具有鰭片主動區的三維電晶體,形成在鰭片主動區上的那些三維場效電晶體(field effect transistors,FETs)也稱為鰭式場效電晶體(FinFET)。為了短的通道控制,希望FinFET具有窄的鰭片寬度,這導致鰭片主動區具有高的深寬比(aspect ratio)。因此,鰭片主動區變得較薄且機械強度較小,這在後續製程期間會引起鰭片彎曲問題並降低裝置效能。因此,需要一種用於鰭式電晶體的裝置結構和形成方法來解決這些問題,以提高電路效能。
根據本發明的一些實施例,提供積體電路結構的形成方法。此方法包含在半導體基底上形成複合應力層,其中複合應力層的形成包含形成具有第一壓縮應力的介電材料之第一應力層,以及形成具有第二壓縮應力的介電材料之第二應力層於第一應力層上,第二壓縮應力大於第一壓縮應力。此方法還包含使用複合應力層作為蝕刻遮罩,圖案化半導體基底以形成多個鰭片主動區。
根據本發明的一些實施例,提供積體電路結構的形成方法。此方
法包含在半導體基底上形成第一壓縮應力的第一應力層。此方法也包含在第一應力層之上形成第二壓縮應力的第二應力層。此方法還包含在第一應力層和第二應力層之間形成拉伸應力的第三應力層。此方法更包含使用第一應力層、第二應力層和第三應力層作為蝕刻遮罩,圖案化半導體基底以形成多個鰭片主動區。
根據本發明的一些實施例,提供半導體結構。此半導體結構包含鰭片主動區突出於半導體基底上方。此半導體結構也包含閘極堆疊設置在鰭片主動區的頂表面和側壁上,其中閘極堆疊包含閘極介電層和閘極電極。此半導體結構還包含複合應力層介於鰭片主動區的頂表面與閘極介電層之間,其中複合應力層包含第一氮化矽層和在第一氮化矽層上的第二氮化矽層,第一氮化矽層具有第一壓縮應力,且第二氮化矽層具有大於第一壓縮應力的第二壓縮應力。
100:半導體結構
102:半導體基底
102A:第一區
102B:第二區
104:隔離部件
104A:內襯材料層
106:鰭片主動區
107:矽鍺(SiGe)層
108:源極和汲極
110:閘極堆疊
110A:閘極介電層
110B:閘極電極
110B-1:覆蓋層
110B-2、110B-4:阻擋層
110B-3:功函數金屬層
110B-5:填充金屬層
112:間隔物
114、114-1、114-2、114-3:複合應力層
114A:第一應力層
114B:第二應力層
114C:第三應力層
114D:第四應力層
116:層間介電(ILD)層
118:溝槽
119:通道
120:虛置閘極
122:閘極硬遮罩
200:方法
202、204、206、208、210、212、214、216、218:操作
252:光阻層
H:高度
W:寬度
為了讓本發明實施例能更容易理解,以下配合所附圖式作詳細說明。應注意的是,根據工業上的標準範例,各個部件未必按照比例繪製。實際上,為了讓討論清晰易懂,各個部件的尺寸可以被任意放大或縮小。
第1A圖為根據一些實施例,半導體結構的透視圖。
第1B圖為根據一些實施例,第1A圖的半導體結構的剖面圖。
第2圖為根據一些實施例,製造半導體結構的方法之流程圖。
第3圖為根據一些實施例,在一製造階段的半導體結構的透視圖。
第3A、3B和3C圖為根據一些實施例,在一製造階段的半導體結構的各種透視圖。
第4和5圖為根據一些實施例,在各個製造階段的半導體結構的透視圖。
第6、7和8圖為根據一些實施例,在各個製造階段的半導體結構的剖面圖。
第9、10和11圖為根據一些實施例,在各個製造階段的半導體結構的透視圖。
第12和13圖為根據一些實施例,半導體結構的閘極堆疊的剖面圖。
以下內容提供了許多不同實施例或範例,以實現本發明實施例的不同部件(feature)。以下描述組件和配置方式的具體範例,以簡化本發明實施例。當然,這些僅僅是範例,而非意圖限制本發明實施例。舉例而言,在以下描述中提及於第二部件上方形成第一部件,其可以包含第一部件和第二部件以直接接觸的方式形成的實施例,並且也可以包含在第一部件和第二部件之間形成額外的部件,使得第一部件和第二部件可以不直接接觸的實施例。
此外,本發明實施例可在各個範例中重複參考標號及/或字母。此重複是為了簡化和清楚之目的,其本身並非用於指定所討論的各個實施例及/或配置之間的關係。另外,在後續本發明實施例中,形成一部件在另一部件上、連接到另一部件和/或耦接到另一部件,可以包含其中的部件直接接觸形成的實施例,並且還可以包含形成額外部件於這些部件之間的實施例,使得這些部件可以不直接接觸。此外,為了容易描述本發明實施例中的一個部件與另一部件之間的關係,在此可以使用空間相關用語,例如「下」、「上」、「水平」、「垂直」、「上方」、「之上」、「下方」、「底下」、「向上」、「向下」、「頂」、「底」等類似的空間相關用語及其衍生用語。這些空間相關用語意欲涵蓋包含這些部件的裝置之不同方向。另外,當用「約」、「近似」等類似用語描述數字或數字範圍時,該用語意欲涵蓋的數值是在合理範圍內包含所描述的數字,例如在所描述的數字之+/-10%之內或本發明所屬技術領域中具有通常知識者理解的其他數值。例如,用語「約5nm」涵蓋從4.5nm至5.5nm的尺寸範圍。
本發明實施例提供了解決鰭片彎曲(buckling)問題的結構及其製造方法。第1A圖是根據一些實施例之半導體結構100的透視圖,第1B圖是根據一些實施例,沿著第1A圖的虛線AA'之半導體結構100的剖面圖。半導體結構100
包含形成有各種場效電晶體(FETs)於其上的半導體基底102,具體地,半導體結構100包含形成有p型場效電晶體(PFETs)於其上的第一區102A和形成有n型場效電晶體(NFETs)於其上的第二區102B。第2圖是根據一些實施例之製造半導體結構例如半導體結構100的方法200的流程圖。第3至11圖是根據一些實施例,在各個製造階段之半導體結構100的透視圖或剖面圖。第12和13圖是根據各種實施例,半導體結構100中的閘極堆疊的剖面圖。以下參照第1至13圖共同描述半導體結構100及製造半導體結構的方法200。
參照第1A和1B圖,半導體結構100包含半導體基底102,半導體基底102具有用於PFETs的第一區102A和用於NFETs的第二區102B。半導體結構100包含各種隔離部件104,例如淺溝槽隔離(shallow trench isolation,STI)部件。半導體結構100還包含形成在半導體基底102上的各種鰭片主動區106,鰭片主動區106突出於隔離部件104之上,並且被隔離部件104包圍和互相隔離。各種鰭式場效電晶體形成在鰭片主動區106上,在本實施例中,PFETs設置在第一區102A的鰭片主動區106上,NFETs設置在第二區102B的鰭片主動區106上。在一些實施例中,在第一區102A的半導體基底102上磊晶成長矽鍺(SiGe)層107,以提高載子遷移率和裝置速度。源極和汲極108形成在鰭片主動區106上,閘極堆疊110形成在鰭片主動區106上,並且設置在相應的源極和汲極108之間。每個閘極堆疊110包含閘極介電層110A和閘極電極110B,此外,還可以在閘極電極110B的側壁和鰭片主動區106的側壁上形成間隔物112。通道119是位於相應的閘極堆疊110底下的鰭片主動區106的一部分。相應的源極和汲極108、閘極堆疊110以及通道119耦接到場效電晶體。在第1A和1B圖所示的範例中,第一區102A包含兩個PFETs,第二區102B包含兩個NFETs。
半導體結構100還包含設置在鰭片主動區106上並且圍繞閘極堆疊110的層間介電(interlayer dielectric,ILD)層116。第1A圖中的ILD層116以虛線繪
製並且被繪示為透明的,以讓各種部件例如閘極堆疊110和鰭片主動區106有更好的觀察效果。由於鰭片主動區106突出於隔離部件104之上,所以閘極堆疊110通過鰭片主動區106的側壁和頂表面更有效地耦接到相應的通道119,因此提高了裝置效能。
特別地,如第1B圖所示,複合應力層114設置在鰭片主動區106的頂表面上,並位於閘極堆疊110下面。複合應力層114是具有工程應力的介電材料層,以保持鰭片沒有彎曲。複合應力層114可以用於其他目的,例如作為圖案化鰭片主動區106的硬遮罩層。複合應力層114是介電質,並且包含本實施例的氮化矽。在形成鰭片主動區106的各種蝕刻製程之後,複合應力層114具有保留在鰭片主動區106的頂表面上的部分。
通過方法200使用複合應力層114來形成半導體結構100,以固定鰭片主動區106並防止其彎曲。以下將進一步詳細描述方法200和半導體結構100,特別是複合應力層114。通過實施半導體結構100及其製造的方法200,消除或減少了鰭片彎曲問題。此外,線端粗糙度(line-end roughness,LER)也得到改善,並降低至小於2.5nm。
參考第3圖,方法200開始於操作202,以提供半導體基底102。半導體基底102包含矽。在一些其他實施例中,半導體基底102包含鍺、矽鍺或其他合適的半導體材料。另外,半導體基底102可以由一些其他合適的元素半導體製成,例如金剛石或鍺;還可以由合適的化合物半導體製成,例如碳化矽、砷化銦或磷化銦;或由合適的合金半導體製成,例如碳化矽鍺、磷化鎵砷或磷化鎵銦。
在本實施例中,半導體基底102包含矽,並且在第一區102A的半導體基底102上磊晶成長矽鍺(SiGe)層107,以增強PFETs的載子遷移率。可以通過任何合適的製程形成SiGe層107,例如,可以沉積並圖案化硬遮罩層,以覆蓋
第二區102B並露出第一區102A;使用圖案化的硬遮罩作為蝕刻遮罩,並使用蝕刻製程蝕刻第一區102A的半導體基底102;使用選擇性磊晶成長以在第一區102A形成SiGe層107;以及使用化學機械研磨(chemical mechanical polishing,CMP)製程來平坦化頂表面。
半導體基底102還可以包含各種摻雜區,例如n型井和p型井。在一些實施例中,半導體基底102可以包含用於隔離的埋藏介電材料層,其通過適當的技術形成,例如稱為植入氧分離(separation by implanted oxygen,SIMOX)的技術。
仍然參考第3圖,方法200進行到操作204,在用於PFETs的第一區102A和用於NFETs的第二區102B內,於半導體基底102上形成複合應力層114。複合應力層114包含具有工程應力的多個膜,以提供組合的物理特性來減少鰭片彎曲,並進一步在隨後的圖案化製程期間用作硬遮罩,以形成鰭片主動區106。
在如第3A圖所示的一些實施例中,複合應力層114(第3A圖中的複合應力層114標示為114-1)包含第一應力層114A和第一應力層114A上的第二應力層114B,這兩層都是介電材料層。第一應力層114A具有較高的密度(體積質量密度),並且相對於第二應力層114B具有較小的應力。在本實施例中,兩個應力層都具有壓縮應力。具體地,第一應力層114A具有第一壓縮應力和第一密度,第二應力層114B具有第二壓縮應力和第二密度。第一密度大於第二密度,並且第一壓縮應力小於第二壓縮應力。此外,第一應力層114A具有第一楊氏模數(Young’s modulus),第二應力層114B具有小於第一楊氏模數的第二楊氏模數。
在本實施例中,第一應力層114A是藉由化學氣相沉積法(chemical vapor deposition,CVD)形成的氮化矽(SiN)層。在一些示例中,相應的CVD沉積溫度範圍從500℃到550℃。形成第一應力層114A的CVD製程的前驅物包含二氯矽烷(dichlorosilane(DCS)或SiH2Cl2)、氨(NH3)和H2。特別地,將氫氣H2添加到前
驅物中,以增加第一應力層114A的密度。第一應力層114A的壓縮應力範圍在0.2GPa和0.4GPa之間,根據一些示例,第一應力層114A的楊氏模數範圍在200GPa和300GPa之間。在一些示例中,第一應力層114A的厚度範圍在10nm和20nm之間。
第二應力層114B沉積在第一區102A和第二區102B的第一應力層114A上。在本實施例中,第二應力層114B也是藉由CVD形成的氮化矽(SiN)。相應的CVD沉積溫度範圍為480℃至520℃。形成第二應力層114B的相應CVD製程的前驅物包含二氯矽烷(DCS)和NH3,但不含H2。因此,如上所述,第二應力層114B的壓縮應力大於第一應力層114A的壓縮應力,並且第二應力層114B的密度小於第一應力層114A的密度。此外,第二應力層114B具有較低的楊氏模數,並且具有相對於第一應力層114A更大的厚度。在一些示例中,第二應力層114B具有壓縮應力範圍在2.8GPa和3.0GPa之間,楊氏模數範圍在160GPa和270GPa之間。在一些示例中,第二應力層114B的厚度範圍在15nm和25nm之間。
在如第3B圖所示的一些其他實施例中,複合應力層114(第3B圖中的複合應力層114標示為114-2)包含介於第一和第二應力層之間的第三應力層114C。在本實施例中,第三應力層114C包含藉由CVD形成的非晶矽。然而,所形成的第三應力層114C具有拉伸應力,例如在-0.3GPa和-0.5GPa之間的拉伸應力。形成第三應力層114C的前驅物包含Si2H6或其他合適的化學物質。相應的CVD沉積溫度低於形成第一應力層114A和第二應力層114B的沉積溫度。在本示例中,形成第三應力層114C的相應CVD沉積溫度範圍在350℃至400℃。根據一些示例,第三應力層114C具有楊氏模數範圍在150GPa和170GPa之間。根據一些示例,第三應力層114C具有厚度範圍在5nm和10nm之間。這些應力層統稱為複合應力層114(或114-2),這些應力層與設計用來解決鰭片彎曲問題的各自特性相結合,並且還做為用來形成鰭片主動區106的硬遮罩。
在如第3C圖所示的一些其他實施例中,複合應力層114(第3C圖中的複合應力層114標示為114-3)還包含介於第二應力層114B和第三應力層114C之間的第四應力層114D。第四應力層114D具有與其他應力層不同的組成。在本實施例中,第四應力層114D包含碳氮化矽(SiCN)。第四應力層114D與具有工程應力的其他應力層組合,使得複合應力層114-3具有應力和機械強度,以通過調整第四應力層114D的應力和厚度來消除或最小化鰭片彎曲問題。第四應力層114D可以由合適的沉積技術形成,例如在適當條件下的CVD。例如,可以通過沉積持續時間來調整第四應力層114D的厚度,並且可以通過沉積溫度和沉積前驅物的分壓來調整第四應力層114D的應力。
參考第4、5和6圖,方法200進行到操作206,以形成各種鰭片主動區106,統稱為鰭結構。在操作206中,圖案化半導體基底102(包含SiGe層107)和複合應力層114,以形成鰭片主動區106和在相鄰的鰭片主動區106之間的溝槽。
在本示例中,通過微影圖案化和蝕刻來圖案化複合應力層114。如第4圖的透視圖所示,可以在複合應力層114上形成用於定義鰭結構的光阻(photoresist或resist)層252。光阻層252包含感光材料,感光材料在曝露於光時,例如紫外(UV)光、深紫外(DUV)光或極紫外(EUV)光,使光阻層252發生性質變化。利用此性質變化,可藉由顯影製程選擇性地去除光阻層252的曝光或未曝光部分,形成圖案化光阻層252的過程也稱為微影圖案化或微影製程。在一實施例中,通過微影圖案化製程將光阻層252圖案化,留下部分的光阻材料在半導體結構100上。在光阻層252已經圖案化之後,對半導體結構100進行蝕刻製程,藉此將開口從光阻層252轉移到複合應力層114,讓複合應力層114產生開口,如第5圖的透視圖所示。在複合應力層114進行圖案化之後,通過濕法剝離或電漿灰化去除剩餘的光阻層252。在一些示例中,微影製程包含旋轉塗布光阻層、軟烤光
阻層、光罩對準、曝光、曝光後烘烤、顯影光阻層、潤洗和乾燥(例如,硬烤)。另外,可以通過例如無光罩微影、電子束寫入和離子束寫入的其他方法來實現、輔助或替換微影製程。圖案化複合應力層114的蝕刻製程可包含濕蝕刻、乾蝕刻或其組合。蝕刻製程可包含多個蝕刻步驟。例如,複合應力層114中的非晶矽膜可以藉由KOH溶液蝕刻,且氮化矽膜可以藉由磷酸溶液蝕刻。
之後,使用複合應力層114作為蝕刻遮罩,對包含SiGe層107的半導體基底102施加另一蝕刻製程,藉此形成溝槽118和鰭片主動區106,如第6圖的剖面圖所示。蝕刻製程可以包含任何合適的蝕刻技術,例如乾蝕刻、濕蝕刻和/或其他蝕刻方法(例如,反應離子蝕刻(reactive ion etching,RIE))。在一些實施例中,蝕刻製程包含具有不同蝕刻化學物質的多個蝕刻步驟,其設計來蝕刻基底以形成具有特定溝槽輪廓的溝槽,以改善裝置效能和圖案密度。在一些示例中,可以使用氟基蝕刻劑的乾蝕刻製程來蝕刻基底的半導體材料。特別地,可以通過控制蝕刻時間或通過控制其他蝕刻參數,來達到控制施加到基底的蝕刻製程,使得半導體基底102被部分蝕刻。在蝕刻製程之後,具有各種鰭片主動區106的鰭結構形成在半導體基底102上並從半導體基底102延伸。
在操作206的各種蝕刻製程期間和其他後續製程期間,例如使淺溝槽隔離(STI)部件凹陷的製程,鰭片主動區106經歷各種應力和機械力,這可能使鰭片主動區106由於位在半導體基底102上方及具有高深寬比而產生變形。設計複合應力層114使其具有堆疊的多個應力膜和相應的物理特性,例如應力、楊氏模數、密度、組成和厚度,以補償鰭片應力和/或製程引起的應力,增強鰭片強度,並減少/消除鰭片彎曲。
參考第7圖的剖面圖,方法200進行到操作208,在溝槽118中形成各種STI部件104。在操作208中,以一或多種介電材料填充溝槽118來形成STI部件104。在本實施例中,如第6圖所示,通過CVD或原子層沉積(atomic layer
deposition,ALD)在溝槽118的側壁和底表面上沉積內襯材料層104A,例如氮化矽,以防止鰭片主動區106氧化。之後,在溝槽118中填充一或多種介電材料以形成STI部件104。合適的填充介電材料包含半導體氧化物、半導體氮化物、半導體氮氧化物、氟化石英玻璃(fluorinated silica glass,FSG)、低介電常數(K)介電材料、和/或前述之組合。在各種實施例中,使用高密度電漿CVD(high-density plasma-CVD,HDP-CVD)製程、次大氣壓CVD(sub-atmospheric CVD,SACVD)製程、高深寬比製程(high-aspect ratio process,HARP)、可流動CVD(flowable CVD,FCVD)和/或旋塗製程來沉積介電材料。
操作208可以進一步包含化學機械研磨(CMP)製程,以去除多餘的介電材料並平坦化半導體結構100的頂表面。CMP製程可以使用複合應力層114作為研磨停止層,以防止研磨到包含SiGe層107的半導體基底102。操作208還可以包含蝕刻製程,以選擇性地使STI部件104凹陷,讓鰭片主動區106突出於STI部件104的頂表面上方,如第7圖所示。在相應的CMP製程和蝕刻製程期間,位於凹陷的STI部件104上方的內襯材料層104A的部分也被移除。
複合應力層114在操作206期間用作硬遮罩,並且在操作208期間用作研磨停止層,以形成鰭片主動區106和STI部件104。如第7圖所示,複合應力層114的一部分可能在各種蝕刻和研磨製程期間損耗,並且複合應力層114的其他部分保留在鰭片主動區106的頂表面上。在一些示例中,僅第一應力層114A保留在鰭片頂表面上。在一些示例中,第一應力層114A和第三應力層114C保留在鰭片頂表面上。在又一些示例中,第一應力層114A和第三應力層114C以及至少一部分的第二應力層114B保留在鰭片頂表面上。在又一些示例中,第一應力層114A、第三應力層114C和第四應力層114D以及至少一部分的第二應力層114B保留在鰭片頂表面上。在一些實施例中,由於蝕刻損耗和蝕刻特性,剩餘的複合應力層114具有圓角形狀。因此,複合應力層114的剩餘部分介於閘極堆疊110
和鰭片主動區106之間。即使介於閘極介電層110A和鰭片主動區106之間的複合應力層114可以改變閘極電極110B和通道119之間的耦合,由於鰭片主動區106的高深寬比,複合應力層114對於閘極電極110B和通道119之間的耦合影響相對較小。每個鰭片主動區106具有從隔離部件104的頂表面測量的高度「H」和寬度「W」。在先進技術節點中,H/W的比值遠大於1。在一些示例中,高度H的範圍為50nm至55nm,寬度W的範圍為2nm至5nm,並且H/W的比值大於10。閘極從鰭片主動區106的兩個側壁到通道119的耦合與2*H成比例(例如,在此示例中為100nm或更大),且閘極從鰭片主動區106的頂表面到通道119的耦合與W成比例(例如,在此示例中為5nm或更小),使得複合應力層114在鰭片主動區106頂部的影響相對較小。如前所述,在一些實施例中,第一應力層114A的厚度T範圍在10nm和20nm之間,第一應力層114A的寬度W範圍在2nm至5nm。此外,第一應力層114A的T/W比值大於2,例如在2和10之間。
參考第8圖的剖面圖,方法200進行至操作210,在鰭片主動區106和STI部件104上形成各種虛置閘極120。在本實施例中,虛置閘極120具有細長形狀,並且當鰭片主動區106的方向在X方向時,虛置閘極120的方向在Y方向。每個虛置閘極120可以設置在多個鰭片主動區106上。特別地,一些虛置閘極120或其部分形成在鰭片主動區106上,並且一些虛置閘極120或其部分形成在STI部件104上。在一些實施例中,一或多個虛置閘極120設置在鰭片主動區106的端部上,使得此虛置閘極部分地落在鰭片主動區106上,並且部分地落在STI部件104上,這些邊緣被配置來降低邊緣效應並改善整體裝置效能。
每個虛置閘極120可以包含多晶矽,並且還可以包含在多晶矽底下的氧化矽。虛置閘極120的形成包含沉積閘極材料(在本示例中包含多晶矽);以及通過微影圖案化和蝕刻來圖案化閘極材料。可以在閘極材料上形成閘極硬遮罩122,並且在虛置閘極120的形成期間用作蝕刻遮罩。閘極硬遮罩122可以包含
具有蝕刻選擇性的任何合適的材料,例如氧化矽、氮化矽、碳化矽、氮氧化矽、其他合適的材料、和/或前述之組合。在一實施例中,閘極硬遮罩122包含多個膜,例如氧化矽和氮化矽。在一些實施例中,用於形成虛置閘極120的圖案化製程包含通過微影製程在閘極硬遮罩122上形成圖案化的光阻層;使用圖案化的光阻層作為蝕刻遮罩,蝕刻閘極硬遮罩122;使用圖案化的閘極硬遮罩122作為蝕刻遮罩,蝕刻閘極材料以形成虛置閘極120。
一個或多個閘極側壁部件或間隔物112形成在虛置閘極120的側壁和鰭片主動區106的側壁上。間隔物112可以用於讓隨後形成的源極/汲極部件的位置偏移,並且可以用於約束或修改源極/汲極的結構輪廓。間隔物112可包含任何合適的介電材料,例如半導體氧化物、半導體氮化物、半導體碳化物、半導體氮氧化物、其他合適的介電材料、和/或前述之組合。間隔物112可以具有多個膜,例如兩個膜(氧化矽膜和氮化矽膜)或三個膜(氧化矽膜、氮化矽膜和氧化矽膜)。間隔物112的形成包含沉積和非等向性蝕刻,例如乾蝕刻。
虛置閘極120配置在用於各種場效電晶體的鰭片主動區106中,因此相應的FET也稱為FinFET。在本示例中,場效電晶體包含第一區102A的p型FET和第二區102B的n型FET。在其他示例中,那些場效電晶體被配置為形成邏輯電路、記憶體電路(例如一或多個靜態隨機存取記憶體(static random-access memory,SRAM)單元或其他合適的電路。
參考第9圖的透視圖,方法200進行到操作212,形成各種源極和汲極108到相應的FinFET。源極和汲極108可以包含輕摻雜汲極(light doped drain,LDD)部件及重摻雜源極和汲極(S/D)。每個場效電晶體包含形成在相應的鰭片主動區上的源極和汲極,並且虛置閘極120介於源極和汲極之間。通道119形成在鰭片主動區的一部分中,此部分位於虛置閘極120底下,並且通道119橫跨在源極和汲極108之間。
可以通過選擇性磊晶成長形成凸起的源極和汲極108,以達到具有增強的載子遷移率和裝置效能之應變效應。虛置閘極120和間隔物112約束源極和汲極108,以適當的輪廓選擇性地成長在源極/汲極區內。在一些實施例中,源極和汲極108通過一或多個磊晶(epi)製程形成,使得Si部件、SiGe部件、SiC部件和/或其他合適的部件在鰭片主動區106上以結晶態生長。另外,在磊晶成長之前施加蝕刻製程使源極/汲極區凹陷。合適的磊晶製程包含CVD沉積技術(例如,氣相磊晶(vapor-phase epitaxy,VPE)和/或超高真空CVD(ultra-high vacuum CVD,UHV-CVD))、分子束磊晶和/或其他合適的製程。磊晶製程可以使用氣態和/或液態前驅物,其與鰭片主動區106的組成反應。在一些實施例中,相鄰的源極/汲極可以生長而合併在一起,以增加接觸面積並降低接觸阻抗,這可以通過控制磊晶成長製程來達成。
源極和汲極108可以在磊晶製程期間通過引入摻雜物種而原位(in-situ)摻雜,摻雜物種包含:p型摻雜劑,例如硼或BF2;n型摻雜劑,例如磷或砷;和/或其他合適的摻雜劑,其包含前述之組合。如果源極和汲極108未被原位摻雜,則進行植入製程以將相應的摻雜劑引入源極和汲極108中。在一實施例中,nFET中的源極和汲極108包含摻雜有磷的SiC或Si,而pFET中的源極和汲極108包含摻雜有硼的Ge或SiGe。在一些其他實施例中,凸起的源極和汲極108包含一個以上的半導體材料層。例如,在源極/汲極區內的基底上磊晶成長矽鍺層,並在矽鍺層上磊晶成長矽層。之後可以進行一或多個退火製程,以活化源極和汲極108。合適的退火製程包含快速熱退火(rapid thermal annealing,RTA)、雷射退火製程、其他合適的退火技術或前述之組合。
源極和汲極108設置在虛置閘極120的兩側,通道119位於相應的虛置閘極120底下,並且介於相應的源極和汲極108之間,通道119具有適當的摻雜濃度和摻雜分佈。例如,通道119是p型摻雜(或n型摻雜),而相應的源極和汲極
108是n型摻雜(或p型摻雜)。經由一或多個步驟引入合適的摻雜劑,例如經由離子植入,以形成通道119。
參照第10圖的透視圖,方法200進行到操作214,ILD層116形成在半導體基底102上,覆蓋源極和汲極108。ILD層116用虛線繪製在第10圖且繪示為透明的,以更好地觀察埋置在ILD層116中的其他部件(例如鰭片主動區106、虛置閘極120以及源極和汲極108)。ILD層116圍繞虛置閘極120讓虛置閘極120可以被移除,並且在所得到的空腔(也稱為閘極溝槽)中形成替換閘極。因此,在這樣的實施例中,在形成ILD層116之後移除虛置閘極120,ILD層116也是電性互連結構的一部分,其將半導體結構100的各種裝置電性互連。在這樣的實施例中,ILD層116作為支撐和隔離導電線路的絕緣體。ILD層116可以包含任何合適的介電材料,例如半導體氧化物、半導體氮化物、半導體氮氧化物、其他合適的介電材料或前述之組合。在一些實施例中,ILD層116包含低k介電材料(其介電常數小於氧化矽的介電常數)。ILD層116的形成可以包含沉積和CMP製程,以提供平坦化的頂表面。可以通過CMP製程或隨後的蝕刻製程去除閘極硬遮罩122。
參考第11圖的透視圖,方法200進行到用於閘極替換的操作216。去除虛置閘極120,並用具有高k介電材料和金屬的閘極堆疊110替換,因此也稱為高k金屬閘極堆疊110。閘極替換製程可包含蝕刻、沉積和研磨。在本實施例中,通過蝕刻選擇性地去除虛置閘極120,藉此產生閘極溝槽。然後,在閘極溝槽中沉積例如高k介電材料和金屬的閘極材料,以形成高k金屬閘極堆疊110,進一步實施CMP製程,以研磨半導體結構100和從半導體結構100去除多餘的閘極材料。
通過適當的過程,例如閘極後製(gate-last)製程或高k後製(high-k-last)製程,在閘極溝槽中形成閘極堆疊110。可理解的是,閘極堆疊110可以具有任何合適的閘極結構,並且可以通過任何合適的過程形成。閘極堆疊
110形成在半導體基底102上,覆蓋鰭片主動區106的通道119。閘極堆疊110包含閘極介電層110A和設置在閘極介電層110A上的閘極電極110B。在本實施例中,閘極介電層110A包含高k介電材料,且閘極電極110B包含金屬或金屬合金。在一些示例中,閘極介電層110A和閘極電極110B皆可包含多個子層。高k介電材料可包含金屬氧化物、金屬氮化物,例如LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化矽(SiON)或其他合適的介電材料。閘極電極可包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Ru、Co或任何合適的導電材料。在一些實施例中,不同的金屬材料用於具有各自的功函數的nFET和pFET裝置,以增強裝置效能。
閘極介電層110A還可以包含夾設在高k介電材料層和相應的鰭片主動區106之間的界面層。界面層可以包含氧化矽、氮化矽、氮氧化矽和/或其他合適的材料。通過合適的方法,例如ALD、CVD、臭氧氧化等方式來沉積界面層。通過合適的技術,例如ALD、CVD、金屬有機CVD(metal-organic CVD,MOCVD)、PVD、熱氧化、前述之組合和/或其他合適的技術,將高k介電層沉積在界面層上(如果存在界面層)。在一些實施例中,在形成虛置閘極120的操作210中,在鰭片主動區106上形成閘極介電層110A。在這種情況下,閘極介電層110A的形狀如第12圖所示。在一些其他實施例中,在高k後製的製程中形成閘極介電層110A,其在操作216中沉積閘極介電層110A於閘極溝槽中。在這種情況下,閘極介電層110A是U形的,如第13圖所示。
閘極電極110B可以包含多種導電材料。在一些實施例中,閘極電極110B包含覆蓋層110B-1、阻擋層110B-2、功函數金屬層110B-3、另一阻擋層110B-4和填充金屬層110B-5。在進一步的實施例中,覆蓋層110B-1包含氮化鈦、
氮化鉭或其他合適的材料,其通過適當的沉積技術如ALD形成。阻擋層110B-2包含氮化鈦、氮化鉭或其他合適的材料,其通過適當的沉積技術如ALD形成。在一些示例中,可以不存在阻擋層110B-2。
功函數金屬層110B-3包含具有適當功函數的金屬或金屬合金之導電層,使得相應的FET增強其裝置效能。功函數(work function,WF)金屬層110B-3的組成對於第一區102A中的pFET和第二區102B中的nFET是不同的,分別稱為p型WF金屬和n型WF金屬。特別地,n型WF金屬是具有第一功函數的金屬,使得相關的nFET的臨界電壓降低。n型WF金屬接近矽導帶能量(Ec)或更低的功函數,使電子逸出更容易。例如,n型WF金屬具有約4.2eV或更低的功函數。p型WF金屬是具有第二功函數的金屬,使得相關的pFET的臨界電壓降低。p型WF金屬接近矽價帶能量(Ev)或更高的功函數,對原子核提供強的電子鍵結能。例如,p型功函數金屬具有約5.2eV或更高的WF。在一些實施例中,n型WF金屬包含鉭(Ta)。在其他實施例中,n型WF金屬包含鈦鋁(TiAl)、氮化鈦鋁(TiAlN)或其組合。在其他實施例中,n型金屬包含Ta、TiAl、TiAlN、氮化鎢(WN)或其組合。在一些實施例中,p型WF金屬包含氮化鈦(TiN)或氮化鉭(TaN)。在其他實施例中,p型金屬包含TiN、TaN、氮化鎢(WN)、鈦鋁(TiAl)或其組合。功函數金屬通過合適的技術沉積,例如PVD。n型WF金屬或p型WF金屬可以包含各種金屬基膜作為疊層,以使裝置效能和製程相容性達到最適化。
阻擋層110B-4包含氮化鈦、氮化鉭或其他合適的材料,其通過適當的沉積技術如ALD形成。在各種實施例中,填充金屬層110B-5包含鋁、鎢、銅或其他合適的金屬,通過合適的技術例如PVD或電鍍沉積填充金屬層110B-5。
方法200可以包含在上述操作之前、期間或之後實施的其他操作218。例如,方法200可以包含在閘極堆疊110的頂部上形成保護層的操作,以保護閘極堆疊110在後續製程期間不會損失。保護層可以包含與ILD層的介電材料
不同的合適材料,其在蝕刻製程期間達到蝕刻選擇性,以形成接觸開口。在一些實施例中,保護層包含氮化矽。在其他示例中,方法200包含在半導體基底102上形成互連結構,以將各種FET和其他裝置連接到電路中。互連結構包含經由合適製程形成的接點、導孔和金屬線。在銅互連結構中,導電部件包含銅,並且還可以包含阻障層。銅互連結構由鑲嵌製程形成。鑲嵌製程包含沉積ILD層;圖案化ILD層以形成溝槽;沉積各種材料(如阻障層和銅);以及進行CMP製程。鑲嵌製程可以是單鑲嵌製程或雙鑲嵌製程。銅的沉積可以包含形成晶種層的PVD,以及在銅晶種層上形成塊狀銅的電鍍。其他金屬,例如釕、鈷、鎢或鋁,也可用於形成互連結構。在一些實施例中,在將導電材料填充於接觸孔中之前,可以在源極和汲極108上形成矽化物,以進一步降低接觸阻抗。矽化物包含矽和金屬,例如矽化鈦、矽化鉭、矽化鎳或矽化鈷。矽化物可以通過稱為自對準矽化物(self-aligned silicide or salicide)的製程形成。此製程包含金屬沉積,退火使金屬與矽反應,以及蝕刻除去未反應的金屬。在一些其他實施例中,一些其他金屬,例如釕或鈷,也可用於接點和/或導孔。
本發明實施例提供具有FinFETs的半導體結構及其製造方法,以減少鰭片彎曲問題。在實施例的方法中,在基底上形成複合應力層,用於圖案化鰭片主動區。複合應力層包含具有工程應力的多個介電膜,以提供組合的物理特性,藉此減少鰭片彎曲,並進一步在隨後的圖案化製程期間用作硬遮罩,以形成鰭片主動區。複合應力層包含具有較高密度和較低應力的第一應力層,以及在第一應力層上具有較低密度和較高應力的第二應力層。這兩層都是具有壓縮應力的介電材料層,並且在本實施例中包含氮化矽。此外,第一應力層具有第一楊氏模數,第二應力層具有小於第一楊氏模數的第二楊氏模數。複合應力層可包含具有拉伸應力的第三應力層,並且第三應力層介於第一和第二應力層之間。在一些實施例中,第三應力層包含非晶矽。通過在各種實施例中實施所
揭示的結構和製造該結構的方法,可以呈現下述的一些優點。然而,應理解的是,在此提供的不同實施例提供了不同的優點,並且在所有實施例中不一定需要特定的優點。作為一個示例,消除或減少了鰭片彎曲問題。在另一個實例中,線端粗糙度(LER)降低至小於2.5nm。
因此,本發明的一些實施例提供製造半導體結構的方法。此方法包含在半導體基底上形成複合應力層,其中複合應力層的形成包含形成具有第一壓縮應力的介電材料的第一應力層和形成具有第二壓縮應力的介電材料的第二應力層在第一應力層上,第二壓縮應力大於第一壓縮應力,以及使用複合應力層作為蝕刻遮罩,對半導體基底進行圖案化以形成鰭片主動區。
在一些實施例中,第一應力層具有第一密度,且第二應力層具有小於第一密度的第二密度。
在一些實施例中,第一應力層的第一壓縮應力小於0.5GPa,且第二應力層的第二壓縮應力大於2.5Gpa。
在一些實施例中,第一應力層的第一壓縮應力在0.2GPa和0.4GPa之間,且第二應力層的第二壓縮應力在2.8GPa和3.0GPa之間。
在一些實施例中,形成第一應力層包括使用包含二氯矽烷(SiH2Cl2)、NH3和H2的第一前驅物,以化學氣相沉積法來沉積第一氮化矽層,且形成第二應力層包括使用包含二氯矽烷和NH3的第二前驅物,以化學氣相沉積法來沉積第二氮化矽層,第二前驅物不含H2。
在一些實施例中,第一應力層具有第一楊氏模數,且第二應力層具有小於第一楊氏模數的第二楊氏模數。
在一些實施例中,複合應力層的形成還包含形成第三應力層設置於第一應力層和第二應力層之間,其中第三應力層具有拉伸應力,且第一應力層和第二應力層具有壓縮應力。
在一些實施例中,形成第三應力層包含形成具有拉伸應力在-0.3GPa和-0.5GPa之間的非晶矽層。
在一些實施例中,形成第一應力層包含以化學氣相沉積法在第一沉積溫度形成第一應力層;形成第二應力層包含以化學氣相沉積法在第二沉積溫度形成第二應力層;且形成第三應力層包含使用具有Si2H6的前驅物,以化學氣相沉積法在小於第一沉積溫度和第二沉積溫度的第三沉積溫度形成非晶矽層。
在一些實施例中,其中圖案化半導體基底以形成該些鰭片主動區還包含:圖案化複合應力層;使用圖案化的複合應力層作為蝕刻遮罩,蝕刻半導體基底以形成多個溝槽;以介電材料填充該些溝槽以形成多個隔離部件;以及將該些隔離部件凹陷,使得該些鰭片主動區突出於凹陷的該些隔離部件上方。
在一些實施例中,更包含在該些鰭片主動區上形成閘極堆疊,閘極堆疊包含高介電常數(k)介電材料和金屬。
本發明的一些其他實施例提供製造半導體結構的方法。此方法包含在半導體基底上形成第一壓縮應力的第一應力層,在第一應力層上形成第二壓縮應力的第二應力層,在第一應力層和第二應力層之間形成拉伸應力的第三應力層,以及使用第一、第二和第三應力層作為蝕刻遮罩,圖案化半導體基底以形成鰭片主動區。
在一些實施例中,形成第一壓縮應力的第一應力層包含形成氮化矽的第一應力層;形成第二壓縮應力的第二應力層包含形成氮化矽的第二應力層;且形成拉伸應力的第三應力層包含形成非晶矽的第三應力層。
在一些實施例中,第二壓縮應力大於第一壓縮應力。
在一些實施例中,第一應力層的第一壓縮應力小於0.5GPa,且第二應力層的第二壓縮應力大於2.5GPa。
在一些實施例中,第一應力層具有第一密度,且第二應力層具有小於第一密度的第二密度。
在一些實施例中,形成第一應力層包括使用包含二氯矽烷(SiH2Cl2)、NH3和H2的第一前驅物,以化學氣相沉積法來沉積第一氮化矽層;且形成第二應力層包括使用包含二氯矽烷和NH3的第二前驅物,以化學氣相沉積法來沉積第二氮化矽層,第二前驅物不含H2。
在一些實施例中,第一應力層具有第一楊氏模數,且第二應力層具有小於第一楊氏模數的第二楊氏模數。
在一些實施例中,第一應力層具有第一厚度;第二應力層具有第二厚度;且第三應力層具有第三厚度,其中第三厚度小於第一厚度,且第一厚度小於第二厚度。
本發明的一些其他實施例提供製造半導體結構的方法。此方法包含使用含有H2的第一前驅物,在半導體基底上形成具有第一應力的氮化矽之第一應力層,使用不含H2的第二前驅物,在第一應力層上形成具有第二應力的氮化矽之第二應力層,第二應力比第一應力大,圖案化第一和第二應力層,以形成具有開口的圖案化硬遮罩,以及通過圖案化硬遮罩的開口蝕刻半導體基底,以形成鰭片主動區。
本發明的一些實施例提供半導體結構。此半導體結構包含突出於半導體基底上方的鰭片主動區,閘極堆疊設置在鰭片主動區的頂表面和側壁上,其中閘極堆疊包含閘極介電層和閘極電極,以及介於鰭片主動區的頂表面和閘極介電層之間的複合應力層,複合應力層具有工程應力的氮化矽,以防止鰭片彎曲。
以上概述了數個實施例的部件、使得在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的概念。在本發明所屬技術領域中具有
通常知識者應該理解、可以使用本發明實施例作為基礎、來設計或修改其他製程和結構、以實現與在此所介紹的實施例相同的目的及/或達到相同的好處。在本發明所屬技術領域中具有通常知識者也應該理解、這些等效的結構並不背離本發明的精神和範圍、並且在不背離本發明的精神和範圍的情況下、在此可以做出各種改變、取代和其他選擇。因此、本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:半導體結構
102:半導體基底
102A:第一區
102B:第二區
107:矽鍺(SiGe)層
114-1:複合應力層
114A:第一應力層
114B:第二應力層
Claims (13)
- 一種積體電路結構的形成方法,包括:在一半導體基底上形成一複合應力層,其中該複合應力層的形成包含形成具有一第一壓縮應力的一介電材料的一第一應力層,及形成具有一第二壓縮應力的該介電材料的一第二應力層於該第一應力層上,該第二壓縮應力大於該第一壓縮應力;以及使用該複合應力層作為蝕刻遮罩,圖案化該半導體基底以形成多個鰭片主動區。
- 如申請專利範圍第1項所述之積體電路結構的形成方法,其中該第一應力層具有一第一密度,且該第二應力層具有小於該第一密度的一第二密度。
- 如申請專利範圍第1或2項所述之積體電路結構的形成方法,其中該第一應力層的該第一壓縮應力在0.2GPa和0.4GPa之間,且該第二應力層的該第二壓縮應力在2.8GPa和3.0GPa之間。
- 如申請專利範圍第3項所述之積體電路結構的形成方法,其中形成該第一應力層包括使用包含二氯矽烷(SiH2Cl2)、NH3和H2的一第一前驅物,以化學氣相沉積法來沉積一第一氮化矽層,且形成該第二應力層包括使用包含二氯矽烷和NH3的一第二前驅物,以化學氣相沉積法來沉積一第二氮化矽層,該第二前驅物不含H2。
- 如申請專利範圍第1或2項所述之積體電路結構的形成方法,其中該第一應力層具有一第一楊氏模數,且該第二應力層具有小於該第一楊氏模數的一第二楊氏模數。
- 如申請專利範圍第1或2項所述之積體電路結構的形成方法,其中該複合應力層的形成還包括形成一第三應力層設置於該第一應力層和該第二應 力層之間,其中該第三應力層具有拉伸應力,且該第一應力層和該第二應力層具有壓縮應力。
- 如申請專利範圍第6項所述之積體電路結構的形成方法,其中形成該第三應力層包括形成具有拉伸應力在-0.3GPa和-0.5GPa之間的一非晶矽層。
- 如申請專利範圍第7項所述之積體電路結構的形成方法,其中:形成該第一應力層包括以化學氣相沉積法在一第一沉積溫度形成該第一應力層;形成該第二應力層包括以化學氣相沉積法在一第二沉積溫度形成該第二應力層;以及形成該第三應力層包括使用具有Si2H6的前驅物,以化學氣相沉積法在小於該第一沉積溫度和該第二沉積溫度的一第三沉積溫度形成該非晶矽層。
- 如申請專利範圍第1或2項所述之積體電路結構的形成方法,其中圖案化該半導體基底以形成該些鰭片主動區還包括:圖案化該複合應力層;使用圖案化的該複合應力層作為蝕刻遮罩,蝕刻該半導體基底以形成多個溝槽;以介電材料填充該些溝槽以形成多個隔離部件;以及將該些隔離部件凹陷,使得該些鰭片主動區突出於凹陷的該些隔離部件上方。
- 一種積體電路結構的形成方法,包括:在一半導體基底上形成一第一壓縮應力的一第一應力層;在該第一應力層之上形成一第二壓縮應力的一第二應力層;在該第一應力層和該第二應力層之間形成一拉伸應力的一第三應力層;以及 使用該第一應力層、該第二應力層和該第三應力層作為蝕刻遮罩,圖案化該半導體基底以形成多個鰭片主動區。
- 如申請專利範圍第10項所述之積體電路結構的形成方法,其中該第一應力層的該第一壓縮應力小於0.5GPa,且該第二應力層的該第二壓縮應力大於2.5GPa。
- 如申請專利範圍第10或11項所述之積體電路結構的形成方法,其中:該第一應力層具有一第一厚度;該第二應力層具有一第二厚度;且該第三應力層具有一第三厚度,其中該第三厚度小於該第一厚度,且該第一厚度小於該第二厚度。
- 一種半導體結構,包括:一鰭片主動區,突出於一半導體基底上方;一閘極堆疊,設置在該鰭片主動區的一頂表面和側壁上,其中該閘極堆疊包含一閘極介電層和一閘極電極;以及一複合應力層,介於該鰭片主動區的該頂表面與該閘極介電層之間,其中該複合應力層包含一第一氮化矽層和在該第一氮化矽層上的一第二氮化矽層,該第一氮化矽層具有一第一壓縮應力,且該第二氮化矽層具有大於該第一壓縮應力的一第二壓縮應力。
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